****** START compiling Stream:Read(struct):int:this (MethodHash=dbd77fdf) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = true OPTIONS: compProcedureSplittingEH = true OPTIONS: Jit invoked for ngen OPTIONS: Stack probing is DISABLED IL to import: IL_0000 28 30 05 00 0a call 0xA000530 IL_0005 0f 01 ldarga.s 0x1 IL_0007 28 87 00 00 0a call 0xA000087 IL_000c 6f 31 05 00 0a callvirt 0xA000531 IL_0011 0a stloc.0 IL_0012 02 ldarg.0 IL_0013 06 ldloc.0 IL_0014 16 ldc.i4.0 IL_0015 0f 01 ldarga.s 0x1 IL_0017 28 87 00 00 0a call 0xA000087 IL_001c 6f c4 1d 00 06 callvirt 0x6001DC4 IL_0021 0b stloc.1 IL_0022 07 ldloc.1 IL_0023 6e conv.u8 IL_0024 0f 01 ldarga.s 0x1 IL_0026 28 87 00 00 0a call 0xA000087 IL_002b 6a conv.i8 IL_002c 31 0b ble.s 11 (IL_0039) IL_002e 28 0d 0e 00 06 call 0x6000E0D IL_0033 73 68 1e 00 06 newobj 0x6001E68 IL_0038 7a throw IL_0039 06 ldloc.0 IL_003a 16 ldc.i4.0 IL_003b 07 ldloc.1 IL_003c 73 46 05 00 0a newobj 0xA000546 IL_0041 0c stloc.2 IL_0042 12 02 ldloca.s 0x2 IL_0044 03 ldarg.1 IL_0045 28 47 05 00 0a call 0xA000547 IL_004a 07 ldloc.1 IL_004b 0d stloc.3 IL_004c de 0d leave.s 13 (IL_005b) IL_004e 28 30 05 00 0a call 0xA000530 IL_0053 06 ldloc.0 IL_0054 16 ldc.i4.0 IL_0055 6f 32 05 00 0a callvirt 0xA000532 IL_005a dc endfinally IL_005b 09 ldloc.3 IL_005c 2a ret lvaSetClass: setting class for V00 to (0000017DD4C58460) Stream Set preferred register for V00 to [rcx] 'this' passed in register rcx Set preferred register for V01 to [rdx] Arg #1 passed in register(s) rdx lvaSetClass: setting class for V02 to (0000017DD20B5AF2) (null) ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 struct (16) ; V02 loc0 ref class-hnd ; V03 loc1 int ; V04 loc2 struct (16) ; V05 loc3 int *************** In compInitDebuggingInfo() for Stream:Read(struct):int:this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 6 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 05Dh 1: 01h 01h V01 arg1 000h 05Dh 2: 02h 02h V02 loc0 000h 05Dh 3: 03h 03h V03 loc1 000h 05Dh 4: 04h 04h V04 loc2 000h 05Dh 5: 05h 05h V05 loc3 000h 05Dh info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0007h ( STACK_EMPTY NOP CALL_SITE ) *************** In fgFindBasicBlocks() for Stream:Read(struct):int:this Jump targets: IL_0012 addr IL_0039 IL_004e addr IL_005b New Basic Block BB01 [0000] created. BB01 [000..012) New Basic Block BB02 [0001] created. BB02 [012..02E) New Basic Block BB03 [0002] created. BB03 [02E..039) New Basic Block BB04 [0003] created. BB04 [039..04E) New Basic Block BB05 [0004] created. BB05 [04E..05B) New Basic Block BB06 [0005] created. BB06 [05B..05D) EH clause #0: Flags: 0x2 (finally) TryOffset: 0x12 TryLength: 0x3c HandlerOffset: 0x4e HandlerLength: 0xd ClassToken: 0x0 *************** After fgFindBasicBlocks() has created the EH table *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) *************** In fgNormalizeEH() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 rare BB04 [0003] 1 0 1 [039..04E)-> BB06 (leave ) T0 } BB05 [0004] 1 0 1 [04E..05B) (finret) H0 finally { } keep label target BB06 [0005] 1 1 [05B..05D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) No EH normalization performed. INLINER: during 'prejit' result 'failed this callee' reason 'has exception handling' for 'n/a' calling 'Stream:Read(struct):int:this' INLINER: Marking Stream:Read(struct):int:this as NOINLINE because of has exception handling INLINER: during 'prejit' result 'failed this callee' reason 'has exception handling' IL Code Size,Instr 93, 39, Basic Block count 6, Local Variable Num,Ref count 6, 17 for method Stream:Read(struct):int:this OPTIONS: opts.MinOpts() == false Basic block list for 'Stream:Read(struct):int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 rare BB04 [0003] 1 0 1 [039..04E)-> BB06 (leave ) T0 } BB05 [0004] 1 0 1 [04E..05B) (finret) H0 finally { } keep label target BB06 [0005] 1 1 [05B..05D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Stream:Read(struct):int:this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Stream:Read(struct):int:this' [ 0] 0 (0x000) call 0A000530 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [000002] ------------ * STMT void (IL 0x000... ???) [000001] I-C-G------- \--* CALL ref ArrayPool`1.get_Shared (exactContextHnd=0x0000017DD4DBCE69) [ 1] 5 (0x005) ldarga.s 1 [ 2] 7 (0x007) call 0A000087 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 lvaGrabTemp returning 6 (V06 tmp0) called for impAppendStmt. [000010] ------------ * STMT void (IL ???... ???) [000003] --C--------- | /--* RET_EXPR ref (inl return from call [000001]) [000009] -AC--------- \--* ASG ref [000008] D------N---- \--* LCL_VAR ref V06 tmp0 lvaSetClass: setting class for V06 to (0000017DD4DBCE68) ArrayPool`1 [000007] ------------ * STMT void (IL ???... ???) [000006] I-C-G------- \--* CALL int Span`1.get_Length (exactContextHnd=0x0000017DD4D6C239) [000005] L----------- this in rcx \--* ADDR byref [000004] ------------ \--* LCL_VAR struct V01 arg1 [ 2] 12 (0x00c) callvirt 0A000531 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is ref, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is ArrayPool`1 (attrib 20000400) base method is ArrayPool`1::Rent devirt to ArrayPool`1::Rent -- speculative [000013] --C-G------- * CALLV ind ref ArrayPool`1.Rent [000011] ------------ this in rcx +--* LCL_VAR ref V06 tmp0 [000012] --C--------- arg1 \--* RET_EXPR int (inl return from call [000006]) Class not final or exact, method not final, no devirtualization INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Stream:Read(struct):int:this' calling 'ArrayPool`1:Rent(int):ref:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 17 (0x011) stloc.0 [000017] ------------ * STMT void (IL ???... ???) [000013] --C-G------- | /--* CALLV ind ref ArrayPool`1.Rent [000011] ------------ this in rcx | | +--* LCL_VAR ref V06 tmp0 [000012] --C--------- arg1 | | \--* RET_EXPR int (inl return from call [000006]) [000016] -AC-G------- \--* ASG ref [000015] D------N---- \--* LCL_VAR ref V02 loc0 impImportBlockPending for BB02 impImportBlockPending for BB05 Importing BB02 (PC=018) of 'Stream:Read(struct):int:this' [ 0] 18 (0x012) ldarg.0 [ 1] 19 (0x013) ldloc.0 [ 2] 20 (0x014) ldc.i4.0 0 [ 3] 21 (0x015) ldarga.s 1 [ 4] 23 (0x017) call 0A000087 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000025] ------------ * STMT void (IL 0x012... ???) [000024] I-C-G------- \--* CALL int Span`1.get_Length (exactContextHnd=0x0000017DD4D6C239) [000023] L----------- this in rcx \--* ADDR byref [000022] ------------ \--* LCL_VAR struct V01 arg1 [ 4] 28 (0x01c) callvirt 06001DC4 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is int, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is Stream (attrib 21000400) base method is Stream::Read devirt to Stream::Read -- speculative [000027] --C-G------- * CALLV ind int Stream.Read [000019] ------------ this in rcx +--* LCL_VAR ref V00 this [000020] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000021] ------------ arg2 +--* CNS_INT int 0 [000026] --C--------- arg3 \--* RET_EXPR int (inl return from call [000024]) Class not final or exact, method not final, no devirtualization INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Stream:Read(struct):int:this' calling 'Stream:Read(ref,int,int):int:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 33 (0x021) stloc.1 [000033] ------------ * STMT void (IL ???... ???) [000027] --C-G------- | /--* CALLV ind int Stream.Read [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this [000020] ------------ arg1 | | +--* LCL_VAR ref V02 loc0 [000021] ------------ arg2 | | +--* CNS_INT int 0 [000026] --C--------- arg3 | | \--* RET_EXPR int (inl return from call [000024]) [000032] -AC-G------- \--* ASG int [000031] D------N---- \--* LCL_VAR int V03 loc1 [ 0] 34 (0x022) ldloc.1 [ 1] 35 (0x023) conv.u8 [ 1] 36 (0x024) ldarga.s 1 [ 2] 38 (0x026) call 0A000087 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000039] ------------ * STMT void (IL 0x022... ???) [000038] I-C-G------- \--* CALL int Span`1.get_Length (exactContextHnd=0x0000017DD4D6C239) [000037] L----------- this in rcx \--* ADDR byref [000036] ------------ \--* LCL_VAR struct V01 arg1 [ 2] 43 (0x02b) conv.i8 [ 2] 44 (0x02c) ble.s [000044] ------------ * STMT void (IL ???... ???) [000043] --C--------- \--* JTRUE void [000041] --C--------- | /--* CAST long <- int [000040] --C--------- | | \--* RET_EXPR int (inl return from call [000038]) [000042] --C--------- \--* LE int [000035] ---------U-- \--* CAST long <- ulong <- uint [000034] ------------ \--* LCL_VAR int V03 loc1 impImportBlockPending for BB03 impImportBlockPending for BB04 Importing BB04 (PC=057) of 'Stream:Read(struct):int:this' [ 0] 57 (0x039) ldloc.0 [ 1] 58 (0x03a) ldc.i4.0 0 [ 2] 59 (0x03b) ldloc.1 [ 3] 60 (0x03c) newobj lvaGrabTemp returning 7 (V07 tmp1) called for NewObj constructor temp. [000052] ------------ * STMT void (IL 0x039... ???) [000050] ------------ | /--* CNS_INT int 0 [000051] IA------R--- \--* ASG struct (init) [000049] D------N---- \--* LCL_VAR struct V07 tmp1 0A000546 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000059] ------------ * STMT void (IL ???... ???) [000055] I-C-G------- \--* CALL void Span`1..ctor (exactContextHnd=0x0000017DD4D6C239) [000054] L----------- this in rcx +--* ADDR byref [000053] ------------ | \--* LCL_VAR struct V07 tmp1 [000046] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000047] ------------ arg2 +--* CNS_INT int 0 [000048] ------------ arg3 \--* LCL_VAR int V03 loc1 [ 1] 65 (0x041) stloc.2 [000064] ------------ * STMT void (IL 0x041... ???) [000060] ------------ | /--* LCL_VAR struct V07 tmp1 [000063] -A------R--- \--* ASG struct (copy) [000061] D----------- \--* LCL_VAR struct V04 loc2 [ 0] 66 (0x042) ldloca.s 2 [ 1] 68 (0x044) ldarg.1 [ 2] 69 (0x045) call 0A000547 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 Calling impNormStructVal on: [000067] ------------ * LCL_VAR struct V01 arg1 resulting tree: [000070] x----------- * OBJ(16) struct [000069] L----------- \--* ADDR byref [000067] ------------ \--* LCL_VAR struct V01 arg1 [000072] ------------ * STMT void (IL 0x042... ???) [000068] I-C-G------- \--* CALL void Span`1.CopyTo (exactContextHnd=0x0000017DD4D6C239) [000066] L----------- this in rcx +--* ADDR byref [000065] ------------ | \--* LCL_VAR struct V04 loc2 [000070] x----------- arg1 \--* OBJ(16) struct [000069] L----------- \--* ADDR byref [000067] ------------ \--* LCL_VAR struct V01 arg1 [ 0] 74 (0x04a) ldloc.1 [ 1] 75 (0x04b) stloc.3 [000076] ------------ * STMT void (IL 0x04A... ???) [000073] ------------ | /--* LCL_VAR int V03 loc1 [000075] -A---------- \--* ASG int [000074] D------N---- \--* LCL_VAR int V05 loc3 [ 0] 76 (0x04c) leave.s 005B Before import CEE_LEAVE in BB04 (targetting BB06): -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 rare BB04 [0003] 1 0 1 [039..04E)-> BB06 (leave ) T0 } BB05 [0004] 1 0 1 [04E..05B) (finret) H0 finally { } keep label target BB06 [0005] 1 1 [05B..05D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB04, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=8, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB04 New Basic Block BB07 [0006] created. impImportLeave - jumping out of a finally-protected try (EH#0), convert block BB04 to BBJ_ALWAYS, add BBJ_CALLFINALLY block BB07 New Basic Block BB08 [0007] created. impImportLeave - jumping out of a finally-protected try (EH#0), created step (BBJ_ALWAYS) block BB08 impImportLeave - final destination of step blocks set to BB06 impImportBlockPending for BB06 After import CEE_LEAVE: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 rare BB04 [0003] 1 0 1 [039..04E)-> BB07 (always) T0 } BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) (finret) H0 finally { } keep label target BB06 [0005] 1 1 [05B..05D) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) impImportBlockPending for BB07 Importing BB06 (PC=091) of 'Stream:Read(struct):int:this' [ 0] 91 (0x05b) ldloc.3 [ 1] 92 (0x05c) ret [000080] ------------ * STMT void (IL 0x05B... ???) [000079] ------------ \--* RETURN int [000078] ------------ \--* LCL_VAR int V05 loc3 Importing BB03 (PC=046) of 'Stream:Read(struct):int:this' [ 0] 46 (0x02e) call 06000E0D In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [000083] ------------ * STMT void (IL 0x02E... ???) [000082] I-C-G------- \--* CALL ref SR.get_IO_StreamTooLong (exactContextHnd=0x0000017DD20EA681) [ 1] 51 (0x033) newobj lvaGrabTemp returning 8 (V08 tmp2) called for NewObj constructor temp. [000089] ------------ * STMT void (IL ???... ???) [000086] ------------ | /--* ALLOCOBJ ref [000085] ------------ | | \--* CNS_INT(h) long 0x17dd3b22ac8 method [000088] -A---------- \--* ASG ref [000087] D------N---- \--* LCL_VAR ref V08 tmp2 lvaSetClass: setting class for V08 to (0000017DD4C57C08) IOException [exact] 06001E68 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000093] ------------ * STMT void (IL ???... ???) [000091] I-C-G------- \--* CALL void IOException..ctor (exactContextHnd=0x0000017DD4C57C09) [000090] ------------ this in rcx +--* LCL_VAR ref V08 tmp2 [000084] --C--------- arg1 \--* RET_EXPR ref (inl return from call [000082]) [ 1] 56 (0x038) throw [000097] ------------ * STMT void (IL 0x038... ???) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW [000094] ------------ arg0 \--* LCL_VAR ref V08 tmp2 Importing BB05 (PC=078) of 'Stream:Read(struct):int:this' [ 0] 78 (0x04e) call 0A000530 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [000100] ------------ * STMT void (IL 0x04E... ???) [000099] I-C-G------- \--* CALL ref ArrayPool`1.get_Shared (exactContextHnd=0x0000017DD4DBCE69) [ 1] 83 (0x053) ldloc.0 [ 2] 84 (0x054) ldc.i4.0 0 [ 3] 85 (0x055) callvirt 0A000532 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is void, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is ArrayPool`1 (attrib 20000400) base method is ArrayPool`1::Return devirt to ArrayPool`1::Return -- speculative [000104] --C-G------- * CALLV ind void ArrayPool`1.Return [000101] --C--------- this in rcx +--* RET_EXPR ref (inl return from call [000099]) [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 Class not final or exact, method not final, no devirtualization INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Stream:Read(struct):int:this' calling 'ArrayPool`1:Return(ref,bool):this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [000107] ------------ * STMT void (IL ???... ???) [000104] --C-G------- \--* CALLV ind void ArrayPool`1.Return [000101] --C--------- this in rcx +--* RET_EXPR ref (inl return from call [000099]) [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 [ 0] 90 (0x05a) endfinally [000109] ------------ * STMT void (IL 0x05A... ???) [000108] ------------ \--* RETFILT void After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E)-> BB07 (always) T0 } i BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) (finret) H0 finally { } keep i label target BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- New BlockSet epoch 1, # of blocks (including unused BB00): 9, bitset array size: 1 (short) *************** In fgMorph() *************** In fgDebugCheckBBlist *************** In fgInline() Expanding INLINE_CANDIDATE in statement [000002] in BB01: [000002] ------------ * STMT void (IL 0x000...0x011) [000001] I-C-G------- \--* CALL ref ArrayPool`1.get_Shared (exactContextHnd=0x0000017DD4DBCE69) INLINER: inlineInfo.tokenLookupContextHandle for ArrayPool`1:get_Shared():ref set to 0x0000017DD4DBCE69: Invoking compiler for the inlinee method ArrayPool`1:get_Shared():ref : IL to import: IL_0000 d0 a6 00 00 1b ldtoken 0x1B0000A6 IL_0005 28 2a 09 00 06 call 0x600092A IL_000a d0 a5 00 00 02 ldtoken 0x20000A5 IL_000f 28 2a 09 00 06 call 0x600092A IL_0014 28 31 09 00 06 call 0x6000931 IL_0019 2c 0b brfalse.s 11 (IL_0026) IL_001b 28 d7 18 00 06 call 0x60018D7 IL_0020 74 4e 00 00 1b castclass 0x1B00004E IL_0025 2a ret IL_0026 d0 a6 00 00 1b ldtoken 0x1B0000A6 IL_002b 28 2a 09 00 06 call 0x600092A IL_0030 d0 a6 00 00 02 ldtoken 0x20000A6 IL_0035 28 2a 09 00 06 call 0x600092A IL_003a 28 31 09 00 06 call 0x6000931 IL_003f 2c 0b brfalse.s 11 (IL_004c) IL_0041 28 d8 18 00 06 call 0x60018D8 IL_0046 74 4e 00 00 1b castclass 0x1B00004E IL_004b 2a ret IL_004c 7e 5e 04 00 0a ldsfld 0xA00045E IL_0051 2a ret INLINER impTokenLookupContextHandle for ArrayPool`1:get_Shared():ref is 0x0000017DD4DBCE69. *************** In fgFindBasicBlocks() for ArrayPool`1:get_Shared():ref Jump targets: IL_0026 IL_004c New Basic Block BB09 [0008] created. BB09 [000..01B) New Basic Block BB10 [0009] created. BB10 [01B..026) New Basic Block BB11 [0010] created. BB11 [026..041) New Basic Block BB12 [0011] created. BB12 [041..04C) New Basic Block BB13 [0012] created. BB13 [04C..052) lvaGrabTemp returning 9 (V09 tmp3) (a long lifetime temp) called for Inline return value spill temp. lvaSetClass: setting class for V09 to (0000017DD4DBCE68) ArrayPool`1 Basic block list for 'ArrayPool`1:get_Shared():ref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB09 [0008] 1 1 [000..01B)-> BB11 ( cond ) BB10 [0009] 1 1 [01B..026) (return) BB11 [0010] 1 1 [026..041)-> BB13 ( cond ) BB12 [0011] 1 1 [041..04C) (return) BB13 [0012] 1 1 [04C..052) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for ArrayPool`1:get_Shared():ref impImportBlockPending for BB09 Importing BB09 (PC=000) of 'ArrayPool`1:get_Shared():ref' [ 0] 0 (0x000) ldtoken [ 1] 5 (0x005) call 0600092A In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 1] 10 (0x00a) ldtoken [ 2] 15 (0x00f) call 0600092A In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 2] 20 (0x014) call 06000931 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Importing Type.op_*Equality intrinsic Folding call to Type:op_Equality to a simple compare via EQ Optimizing compare of types-from-handles to instead compare handles Asking runtime to compare 0000017DD209A650 (Byte) and 0000017DD209A650 (Byte) for equality Runtime reports comparison is known at jit time: 1 [ 1] 25 (0x019) brfalse.s Folding operator with constant nodes into a constant: [000119] ------------ /--* CNS_INT int 0 [000120] ------------ * EQ int [000118] ------------ \--* CNS_INT int 1 Bashed to int constant: [000120] ------------ * CNS_INT int 0 The block falls through into the next BB10 impImportBlockPending for BB10 Importing BB10 (PC=027) of 'ArrayPool`1:get_Shared():ref' [ 0] 27 (0x01b) call 060018D7 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [000123] ------------ * STMT void [000122] I-C-G------- \--* CALL ref ArrayPools.get_BytePool (exactContextHnd=0x0000017DD4C39AB1) [ 1] 32 (0x020) castclass 1B00004E Considering optimization of castclass from 0000017DD4DBCFD0 (TlsOverPerCoreLockedStacksArrayPool`1) to 0000017DD4DBCE68 (ArrayPool`1) Cast will succeed, optimizing to simply return input [ 1] 37 (0x025) ret Inlinee Return expression (before normalization) => [000124] --C--------- * RET_EXPR ref (inl return from call [000122]) [000128] ------------ * STMT void [000124] --C--------- | /--* RET_EXPR ref (inl return from call [000122]) [000127] -AC--------- \--* ASG ref [000126] D------N---- \--* LCL_VAR ref V09 tmp3 Inlinee Return expression (after normalization) => [000129] ------------ * LCL_VAR ref V09 tmp3 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB09 [0008] 1 1 [000..01B) i BB10 [0009] 1 1 [01B..026) (return) i BB11 [0010] 1 1 [026..041)-> BB13 ( cond ) BB12 [0011] 1 1 [041..04C) (return) BB13 [0012] 1 1 [04C..052) (return) -------------------------------------------------------------------------------------------------------------------------------------- BB11 was not imported, marked as removed (1) BB12 was not imported, marked as removed (2) BB13 was not imported, marked as removed (3) Renumbering the basic blocks for fgRemoveEmptyBlocks *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB09 [0008] 1 1 [000..01B) i BB10 [0009] 1 1 [01B..026) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) Renumber BB09 to BB14 Renumber BB10 to BB15 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB14 [0008] 1 1 [000..01B) i BB15 [0009] 1 1 [01B..026) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) New BlockSet epoch 1, # of blocks (including unused BB00): 1, bitset array size: 1 (short) lvaUpdateClass: Updating class for V09 from (0000017DD4DBCE68) ArrayPool`1 to (0000017DD4DBCFD0) TlsOverPerCoreLockedStacksArrayPool`1 ----------- Statements (and blocks) added due to the inlining of call [000001] ----------- Inlinee method body:New Basic Block BB16 [0013] created. Convert bbJumpKind of BB15 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB14 [000..001), preds={} succs={BB15} ------------ BB15 [000..001), preds={} succs={BB16} ***** BB15, stmt 1 [000123] ------------ * STMT void (IL 0x000... ???) [000122] I-C-G------- \--* CALL ref ArrayPools.get_BytePool (exactContextHnd=0x0000017DD4C39AB1) ***** BB15, stmt 2 [000128] ------------ * STMT void (IL 0x000... ???) [000124] --C--------- | /--* RET_EXPR ref (inl return from call [000122]) [000127] -AC--------- \--* ASG ref [000126] D------N---- \--* LCL_VAR ref V09 tmp3 ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000001] is [000129] ------------ * LCL_VAR ref V09 tmp3 Successfully inlined ArrayPool`1:get_Shared():ref (82 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB01 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'ArrayPool`1:get_Shared():ref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000123] in BB15: [000123] ------------ * STMT void (IL 0x000... ???) [000122] I-C-G------- \--* CALL ref ArrayPools.get_BytePool (exactContextHnd=0x0000017DD4C39AB1) INLINER: inlineInfo.tokenLookupContextHandle for ArrayPools:get_BytePool():ref set to 0x0000017DD4C39AB1: Invoking compiler for the inlinee method ArrayPools:get_BytePool():ref : IL to import: IL_0000 7e ad 05 00 04 ldsfld 0x40005AD IL_0005 2a ret INLINER impTokenLookupContextHandle for ArrayPools:get_BytePool():ref is 0x0000017DD4C39AB1. *************** In fgFindBasicBlocks() for ArrayPools:get_BytePool():ref Jump targets: none New Basic Block BB17 [0014] created. BB17 [000..006) Basic block list for 'ArrayPools:get_BytePool():ref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB17 [0014] 1 1 [000..006) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for ArrayPools:get_BytePool():ref impImportBlockPending for BB17 Importing BB17 (PC=000) of 'ArrayPools:get_BytePool():ref' [ 0] 0 (0x000) ldsfld 040005AD [ 1] 5 (0x005) ret Inlinee Return expression (before normalization) => [000140] --CXG------- * IND ref [000138] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG------- \--* ADD byref [000137] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----------- arg0 +--* IND long [000132] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] ------------ arg1 \--* CNS_INT int 327 Inlinee Return expression (after normalization) => [000140] --CXG------- * IND ref [000138] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG------- \--* ADD byref [000137] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----------- arg0 +--* IND long [000132] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] ------------ arg1 \--* CNS_INT int 327 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB17 [0014] 1 1 [000..006) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000122] ----------- Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000122] is [000140] --CXG------- * IND ref [000138] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG------- \--* ADD byref [000137] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----------- arg0 +--* IND long [000132] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] ------------ arg1 \--* CNS_INT int 327 Successfully inlined ArrayPools:get_BytePool():ref (6 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'ArrayPools:get_BytePool():ref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000124] with [000140] [000124] --C--------- * RET_EXPR ref (inl return from call [000140]) Inserting the inline return expression [000140] --CXG------- * IND ref [000138] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG------- \--* ADD byref [000137] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----------- arg0 +--* IND long [000132] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] ------------ arg1 \--* CNS_INT int 327 Replacing the return expression placeholder [000003] with [000129] [000003] --C--------- * RET_EXPR ref (inl return from call [000129]) Inserting the inline return expression [000129] ------------ * LCL_VAR ref V09 tmp3 Expanding INLINE_CANDIDATE in statement [000007] in BB16: [000007] ------------ * STMT void (IL ???... ???) [000006] I-C-G------- \--* CALL int Span`1.get_Length (exactContextHnd=0x0000017DD4D6C239) [000005] L----------- this in rcx \--* ADDR byref [000004] ------------ \--* LCL_VAR struct V01 arg1 thisArg: is a constant is byref to a struct local [000005] L----------- * ADDR byref [000004] ------------ \--* LCL_VAR struct V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for Span`1:get_Length():int:this set to 0x0000017DD4D6C239: Invoking compiler for the inlinee method Span`1:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b a0 01 00 0a ldfld 0xA0001A0 IL_0006 2a ret INLINER impTokenLookupContextHandle for Span`1:get_Length():int:this is 0x0000017DD4D6C239. *************** In fgFindBasicBlocks() for Span`1:get_Length():int:this Jump targets: none New Basic Block BB18 [0015] created. BB18 [000..007) Basic block list for 'Span`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB18 [0015] 1 1 [000..007) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Span`1:get_Length():int:this impImportBlockPending for BB18 Importing BB18 (PC=000) of 'Span`1:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A0001A0 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000145] ----G------- * FIELD int _length [000143] L----------- \--* ADDR byref [000144] ------------ \--* LCL_VAR struct V01 arg1 Inlinee Return expression (after normalization) => [000145] ----G------- * FIELD int _length [000143] L----------- \--* ADDR byref [000144] ------------ \--* LCL_VAR struct V01 arg1 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB18 [0015] 1 1 [000..007) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000006] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000006] is [000145] ----G------- * FIELD int _length [000143] L----------- \--* ADDR byref [000144] ------------ \--* LCL_VAR struct V01 arg1 Successfully inlined Span`1:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stream:Read(struct):int:this' calling 'Span`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000012] with [000145] [000012] --C--------- * RET_EXPR int (inl return from call [000145]) Inserting the inline return expression [000145] ----G------- * FIELD int _length [000143] L----------- \--* ADDR byref [000144] ------------ \--* LCL_VAR struct V01 arg1 Expanding INLINE_CANDIDATE in statement [000025] in BB02: [000025] ------------ * STMT void (IL 0x012...0x021) [000024] I-C-G------- \--* CALL int Span`1.get_Length (exactContextHnd=0x0000017DD4D6C239) [000023] L----------- this in rcx \--* ADDR byref [000022] ------------ \--* LCL_VAR struct V01 arg1 thisArg: is a constant is byref to a struct local [000023] L----------- * ADDR byref [000022] ------------ \--* LCL_VAR struct V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for Span`1:get_Length():int:this set to 0x0000017DD4D6C239: Invoking compiler for the inlinee method Span`1:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b a0 01 00 0a ldfld 0xA0001A0 IL_0006 2a ret INLINER impTokenLookupContextHandle for Span`1:get_Length():int:this is 0x0000017DD4D6C239. *************** In fgFindBasicBlocks() for Span`1:get_Length():int:this Jump targets: none New Basic Block BB19 [0016] created. BB19 [000..007) Basic block list for 'Span`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB19 [0016] 1 1 [000..007) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Span`1:get_Length():int:this impImportBlockPending for BB19 Importing BB19 (PC=000) of 'Span`1:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A0001A0 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000150] ----G------- * FIELD int _length [000148] L----------- \--* ADDR byref [000149] ------------ \--* LCL_VAR struct V01 arg1 Inlinee Return expression (after normalization) => [000150] ----G------- * FIELD int _length [000148] L----------- \--* ADDR byref [000149] ------------ \--* LCL_VAR struct V01 arg1 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB19 [0016] 1 1 [000..007) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000024] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000024] is [000150] ----G------- * FIELD int _length [000148] L----------- \--* ADDR byref [000149] ------------ \--* LCL_VAR struct V01 arg1 Successfully inlined Span`1:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stream:Read(struct):int:this' calling 'Span`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000026] with [000150] [000026] --C--------- * RET_EXPR int (inl return from call [000150]) Inserting the inline return expression [000150] ----G------- * FIELD int _length [000148] L----------- \--* ADDR byref [000149] ------------ \--* LCL_VAR struct V01 arg1 Expanding INLINE_CANDIDATE in statement [000039] in BB02: [000039] ------------ * STMT void (IL 0x022...0x02C) [000038] I-C-G------- \--* CALL int Span`1.get_Length (exactContextHnd=0x0000017DD4D6C239) [000037] L----------- this in rcx \--* ADDR byref [000036] ------------ \--* LCL_VAR struct V01 arg1 thisArg: is a constant is byref to a struct local [000037] L----------- * ADDR byref [000036] ------------ \--* LCL_VAR struct V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for Span`1:get_Length():int:this set to 0x0000017DD4D6C239: Invoking compiler for the inlinee method Span`1:get_Length():int:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b a0 01 00 0a ldfld 0xA0001A0 IL_0006 2a ret INLINER impTokenLookupContextHandle for Span`1:get_Length():int:this is 0x0000017DD4D6C239. *************** In fgFindBasicBlocks() for Span`1:get_Length():int:this Jump targets: none New Basic Block BB20 [0017] created. BB20 [000..007) Basic block list for 'Span`1:get_Length():int:this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB20 [0017] 1 1 [000..007) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Span`1:get_Length():int:this impImportBlockPending for BB20 Importing BB20 (PC=000) of 'Span`1:get_Length():int:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A0001A0 [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000155] ----G------- * FIELD int _length [000153] L----------- \--* ADDR byref [000154] ------------ \--* LCL_VAR struct V01 arg1 Inlinee Return expression (after normalization) => [000155] ----G------- * FIELD int _length [000153] L----------- \--* ADDR byref [000154] ------------ \--* LCL_VAR struct V01 arg1 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB20 [0017] 1 1 [000..007) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000038] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000038] is [000155] ----G------- * FIELD int _length [000153] L----------- \--* ADDR byref [000154] ------------ \--* LCL_VAR struct V01 arg1 Successfully inlined Span`1:get_Length():int:this (7 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stream:Read(struct):int:this' calling 'Span`1:get_Length():int:this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000040] with [000155] [000040] --C--------- * RET_EXPR int (inl return from call [000155]) Inserting the inline return expression [000155] ----G------- * FIELD int _length [000153] L----------- \--* ADDR byref [000154] ------------ \--* LCL_VAR struct V01 arg1 Expanding INLINE_CANDIDATE in statement [000083] in BB03: [000083] ------------ * STMT void (IL 0x02E...0x038) [000082] I-C-G------- \--* CALL ref SR.get_IO_StreamTooLong (exactContextHnd=0x0000017DD20EA681) INLINER: inlineInfo.tokenLookupContextHandle for SR:get_IO_StreamTooLong():ref set to 0x0000017DD20EA681: Invoking compiler for the inlinee method SR:get_IO_StreamTooLong():ref : IL to import: IL_0000 72 04 e9 00 70 ldstr 0x7000E904 IL_0005 14 ldnull IL_0006 28 85 0a 00 06 call 0x6000A85 IL_000b 2a ret INLINER impTokenLookupContextHandle for SR:get_IO_StreamTooLong():ref is 0x0000017DD20EA681. *************** In fgFindBasicBlocks() for SR:get_IO_StreamTooLong():ref Jump targets: none New Basic Block BB21 [0018] created. BB21 [000..00C) Basic block list for 'SR:get_IO_StreamTooLong():ref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB21 [0018] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for SR:get_IO_StreamTooLong():ref impImportBlockPending for BB21 Importing BB21 (PC=000) of 'SR:get_IO_StreamTooLong():ref' [ 0] 0 (0x000) ldstr 7000E904 [ 1] 5 (0x005) ldnull [ 2] 6 (0x006) call 06000A85 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'SR:get_IO_StreamTooLong():ref' calling 'SR:GetResourceString(ref,ref):ref' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000160] --C-G------- * CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null Inlinee Return expression (after normalization) => [000160] --C-G------- * CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB21 [0018] 1 1 [000..00C) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000082] ----------- Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000082] is [000160] --C-G------- * CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null Successfully inlined SR:get_IO_StreamTooLong():ref (12 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stream:Read(struct):int:this' calling 'SR:get_IO_StreamTooLong():ref' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement [000093] in BB03: [000093] ------------ * STMT void (IL ???... ???) [000091] I-C-G------- \--* CALL void IOException..ctor (exactContextHnd=0x0000017DD4C57C09) [000090] ------------ this in rcx +--* LCL_VAR ref V08 tmp2 [000084] --C--------- arg1 \--* RET_EXPR ref (inl return from call [000160]) thisArg: is a local var [000090] ------------ * LCL_VAR ref V08 tmp2 Argument #1: has global refs has side effects [000160] --C-G------- * CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null INLINER: inlineInfo.tokenLookupContextHandle for IOException:.ctor(ref):this set to 0x0000017DD4C57C09: Invoking compiler for the inlinee method IOException:.ctor(ref):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 28 1a 16 00 06 call 0x600161A IL_0007 02 ldarg.0 IL_0008 20 20 16 13 80 ldc.i4 0x80131620 IL_000d 28 03 03 00 06 call 0x6000303 IL_0012 2a ret INLINER impTokenLookupContextHandle for IOException:.ctor(ref):this is 0x0000017DD4C57C09. *************** In fgFindBasicBlocks() for IOException:.ctor(ref):this weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 10 : state 3 [ ldarg.0 ] weight= 38 : state 33 [ ldc.i4 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] multiplier in instance constructors increased to 1.5. Inline candidate looks like a wrapper method. Multiplier increased to 2.5. Inline candidate is mostly loads and stores. Multiplier increased to 5.5. Inline candidate callsite is rare. Multiplier limited to 1.3. calleeNativeSizeEstimate=251 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 25.1 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Stream:Read(struct):int:this' calling 'IOException:.ctor(ref):this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000084] with [000160] [000084] --C--------- * RET_EXPR ref (inl return from call [000160]) Inserting the inline return expression [000160] --C-G------- * CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null Expanding INLINE_CANDIDATE in statement [000059] in BB04: [000059] ------------ * STMT void (IL ???... ???) [000055] I-C-G------- \--* CALL void Span`1..ctor (exactContextHnd=0x0000017DD4D6C239) [000054] L----------- this in rcx +--* ADDR byref [000053] ------------ | \--* LCL_VAR struct V07 tmp1 [000046] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000047] ------------ arg2 +--* CNS_INT int 0 [000048] ------------ arg3 \--* LCL_VAR int V03 loc1 thisArg: is a constant is byref to a struct local [000054] L----------- * ADDR byref [000053] ------------ \--* LCL_VAR struct V07 tmp1 Argument #1: is a local var [000046] ------------ * LCL_VAR ref V02 loc0 Argument #2: is a constant [000047] ------------ * CNS_INT int 0 Argument #3: is a local var [000048] ------------ * LCL_VAR int V03 loc1 INLINER: inlineInfo.tokenLookupContextHandle for Span`1:.ctor(ref,int,int):this set to 0x0000017DD4D6C239: Invoking compiler for the inlinee method Span`1:.ctor(ref,int,int):this : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 06 brtrue.s 6 (IL_0009) IL_0003 18 ldc.i4.2 IL_0004 28 c9 01 00 06 call 0x60001C9 IL_0009 12 00 ldloca.s 0x0 IL_000b fe 15 a6 00 00 1b initobj 0x1B0000A6 IL_0011 06 ldloc.0 IL_0012 8c a6 00 00 1b box 0x1B0000A6 IL_0017 2d 1c brtrue.s 28 (IL_0035) IL_0019 03 ldarg.1 IL_001a 6f 1e 01 00 06 callvirt 0x600011E IL_001f d0 4a 01 00 1b ldtoken 0x1B00014A IL_0024 28 2a 09 00 06 call 0x600092A IL_0029 28 32 09 00 06 call 0x6000932 IL_002e 2c 05 brfalse.s 5 (IL_0035) IL_0030 28 b7 01 00 06 call 0x60001B7 IL_0035 04 ldarg.2 IL_0036 03 ldarg.1 IL_0037 8e ldlen IL_0038 69 conv.i4 IL_0039 35 08 bgt.un.s 8 (IL_0043) IL_003b 05 ldarg.3 IL_003c 03 ldarg.1 IL_003d 8e ldlen IL_003e 69 conv.i4 IL_003f 04 ldarg.2 IL_0040 59 sub IL_0041 36 05 ble.un.s 5 (IL_0048) IL_0043 28 ba 01 00 06 call 0x60001BA IL_0048 02 ldarg.0 IL_0049 03 ldarg.1 IL_004a 28 87 45 00 06 call 0x6004587 IL_004f 28 eb 00 00 2b call 0x2B0000EB IL_0054 04 ldarg.2 IL_0055 28 ec 00 00 2b call 0x2B0000EC IL_005a 73 86 01 00 0a newobj 0xA000186 IL_005f 7d 9f 01 00 0a stfld 0xA00019F IL_0064 02 ldarg.0 IL_0065 05 ldarg.3 IL_0066 7d a0 01 00 0a stfld 0xA0001A0 IL_006b 2a ret INLINER impTokenLookupContextHandle for Span`1:.ctor(ref,int,int):this is 0x0000017DD4D6C239. *************** In fgFindBasicBlocks() for Span`1:.ctor(ref,int,int):this Jump targets: IL_0009 IL_0035 multi IL_0043 IL_0048 New Basic Block BB22 [0019] created. BB22 [000..003) New Basic Block BB23 [0020] created. BB23 [003..009) New Basic Block BB24 [0021] created. BB24 [009..019) New Basic Block BB25 [0022] created. BB25 [019..030) New Basic Block BB26 [0023] created. BB26 [030..035) New Basic Block BB27 [0024] created. BB27 [035..03B) New Basic Block BB28 [0025] created. BB28 [03B..043) New Basic Block BB29 [0026] created. BB29 [043..048) New Basic Block BB30 [0027] created. BB30 [048..06C) Basic block list for 'Span`1:.ctor(ref,int,int):this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB22 [0019] 1 1 [000..003)-> BB24 ( cond ) BB23 [0020] 1 1 [003..009) BB24 [0021] 2 1 [009..019)-> BB27 ( cond ) BB25 [0022] 1 1 [019..030)-> BB27 ( cond ) BB26 [0023] 1 1 [030..035) BB27 [0024] 3 1 [035..03B)-> BB29 ( cond ) BB28 [0025] 1 1 [03B..043)-> BB30 ( cond ) BB29 [0026] 2 1 [043..048) BB30 [0027] 2 1 [048..06C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Span`1:.ctor(ref,int,int):this impImportBlockPending for BB22 Importing BB22 (PC=000) of 'Span`1:.ctor(ref,int,int):this' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) brtrue.s [000168] ------------ * STMT void [000167] ------------ \--* JTRUE void [000165] ------------ | /--* CNS_INT ref null [000166] ------------ \--* NE int [000046] ------------ \--* LCL_VAR ref V02 loc0 impImportBlockPending for BB23 impImportBlockPending for BB24 Importing BB24 (PC=009) of 'Span`1:.ctor(ref,int,int):this' [ 0] 9 (0x009) ldloca.s 0 lvaGrabTemp returning 10 (V10 tmp4) (a long lifetime temp) called for Inline ldloca(s) first use temp. [ 1] 11 (0x00b) initobj 1B0000A6 [000175] ------------ * STMT void [000172] ------------ | /--* CNS_INT int 0 [000174] IA------R--- \--* ASG struct (init) [000173] -------N---- \--* BLK(1) struct [000171] L----------- \--* ADDR byref [000170] ------------ \--* LCL_VAR int V10 tmp4 [ 0] 17 (0x011) ldloc.0 [ 1] 18 (0x012) box 1B0000A6 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 11 (V11 tmp5) called for Single-def Box Helper. lvaSetClass: setting class for V11 to (0000017DD209A650) Byte [exact] [000181] ------------ * STMT void [000178] ------------ | /--* ALLOCOBJ ref [000177] ------------ | | \--* CNS_INT(h) long 0x17dd3b21478 class [000180] -A---------- \--* ASG ref [000179] D------N---- \--* LCL_VAR ref V11 tmp5 [000188] ------------ * STMT void [000185] ------------ | /--* CAST ubyte <- int [000176] ------------ | | \--* LCL_VAR int V10 tmp4 [000187] -A---------- \--* ASG ubyte [000186] -------N---- \--* IND ubyte [000183] ------------ | /--* CNS_INT long 8 [000184] ------------ \--* ADD byref [000182] ------------ \--* LCL_VAR ref V11 tmp5 [ 1] 23 (0x017) brtrue.s Attempting to optimize BOX(valueType) NE null [000192] gtTryRemoveBoxUpstreamEffects: attempting to remove side effects of BOX (valuetype) [000190] (assign/newobj [000181] copy [000188]) Bashing NEWOBJ [000180] to NOP Bashing COPY [000187] to NOP; no source side effects. Success: replacing BOX(valueType) NE null with 1 The conditional jump becomes an unconditional jump to BB27 impImportBlockPending for BB27 Importing BB27 (PC=053) of 'Span`1:.ctor(ref,int,int):this' [ 0] 53 (0x035) ldarg.2 [ 1] 54 (0x036) ldarg.1 [ 2] 55 (0x037) ldlen [ 2] 56 (0x038) conv.i4 [ 2] 57 (0x039) bgt.un.s [000201] ------------ * STMT void [000200] ---X-------- \--* JTRUE void [000198] ---X-------- | /--* CAST int <- int [000197] ---X-------- | | \--* ARR_LENGTH int [000196] ------------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-----U-- \--* GT int [000195] ------------ \--* CNS_INT int 0 impImportBlockPending for BB28 impImportBlockPending for BB29 Importing BB29 (PC=067) of 'Span`1:.ctor(ref,int,int):this' [ 0] 67 (0x043) call 060001BA In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000204] ------------ * STMT void [000203] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException (exactContextHnd=0x0000017DD20D90D1) impImportBlockPending for BB30 Importing BB30 (PC=072) of 'Span`1:.ctor(ref,int,int):this' [ 0] 72 (0x048) ldarg.0 [ 1] 73 (0x049) ldarg.1 [ 2] 74 (0x04a) call 06004587 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 [000211] ------------ * STMT void [000209] I-C-G------- \--* CALL byref JitHelpers.GetRawSzArrayData (exactContextHnd=0x0000017DD4CFEC91) [000208] ------------ arg0 \--* LCL_VAR ref V02 loc0 [ 2] 79 (0x04f) call 2B0000EB In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 [000215] ------------ * STMT void [000213] I-C-G------- \--* CALL byref Unsafe.As (exactContextHnd=0x0000017DD5052698) [000212] --C--------- arg0 \--* RET_EXPR byref (inl return from call [000209]) [ 2] 84 (0x054) ldarg.2 [ 3] 85 (0x055) call 2B0000EC In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 [000221] ------------ * STMT void [000218] I-C-G------- \--* CALL byref Unsafe.Add (exactContextHnd=0x0000017DD5476D70) [000216] --C--------- arg0 +--* RET_EXPR byref (inl return from call [000213]) [000217] ------------ arg1 \--* CNS_INT int 0 [ 2] 90 (0x05a) newobj lvaGrabTemp returning 12 (V12 tmp6) called for NewObj constructor temp. [000226] ------------ * STMT void [000224] ------------ | /--* CNS_INT int 0 [000225] IA------R--- \--* ASG struct (init) [000223] D------N---- \--* LCL_VAR struct V12 tmp6 0A000186 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000232] ------------ * STMT void [000222] --C--------- | /--* RET_EXPR byref (inl return from call [000218]) [000230] -AC--------- \--* ASG byref [000229] -------N---- \--* FIELD byref _value [000228] L----------- \--* ADDR byref [000227] ------------ \--* LCL_VAR struct V12 tmp6 [ 2] 95 (0x05f) stfld 0A00019F [000237] ------------ * STMT void [000231] ------------ | /--* LCL_VAR struct V12 tmp6 [000236] -A------R--- \--* ASG struct (copy) [000235] ------------ \--* OBJ(8) struct [000234] ------------ \--* ADDR byref [000233] ------------ \--* FIELD struct _pointer [000206] L----------- \--* ADDR byref [000207] ------------ \--* LCL_VAR struct V07 tmp1 [ 0] 100 (0x064) ldarg.0 [ 1] 101 (0x065) ldarg.3 [ 2] 102 (0x066) stfld 0A0001A0 [000242] ------------ * STMT void [000048] ------------ | /--* LCL_VAR int V03 loc1 [000241] -A---------- \--* ASG int [000240] -------N---- \--* FIELD int _length [000238] L----------- \--* ADDR byref [000239] ------------ \--* LCL_VAR struct V07 tmp1 [ 0] 107 (0x06b) ret Importing BB28 (PC=059) of 'Span`1:.ctor(ref,int,int):this' [ 0] 59 (0x03b) ldarg.3 [ 1] 60 (0x03c) ldarg.1 [ 2] 61 (0x03d) ldlen [ 2] 62 (0x03e) conv.i4 [ 2] 63 (0x03f) ldarg.2 [ 3] 64 (0x040) sub [ 2] 65 (0x041) ble.un.s [000251] ------------ * STMT void [000250] ---X-------- \--* JTRUE void [000247] ---X-------- | /--* CAST int <- int [000246] ---X-------- | | \--* ARR_LENGTH int [000245] ------------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-----U-- \--* LE int [000244] ------------ \--* LCL_VAR int V03 loc1 impImportBlockPending for BB29 impImportBlockPending for BB30 Importing BB23 (PC=003) of 'Span`1:.ctor(ref,int,int):this' [ 0] 3 (0x003) ldc.i4.2 2 [ 1] 4 (0x004) call 060001C9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000256] ------------ * STMT void [000254] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentNullException (exactContextHnd=0x0000017DD20D90D1) [000253] ------------ arg0 \--* CNS_INT int 2 impImportBlockPending for BB24 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB22 [0019] 1 1 [000..003)-> BB24 ( cond ) i BB23 [0020] 1 1 [003..009) i BB24 [0021] 2 1 [009..019)-> BB27 (always) i newobj BB25 [0022] 1 1 [019..030)-> BB27 ( cond ) BB26 [0023] 1 1 [030..035) BB27 [0024] 3 1 [035..03B)-> BB29 ( cond ) i idxlen BB28 [0025] 1 1 [03B..043)-> BB30 ( cond ) i idxlen BB29 [0026] 2 1 [043..048) i BB30 [0027] 2 1 [048..06C) (return) i -------------------------------------------------------------------------------------------------------------------------------------- BB25 was not imported, marked as removed (1) BB26 was not imported, marked as removed (2) Renumbering the basic blocks for fgRemoveEmptyBlocks *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB22 [0019] 1 1 [000..003)-> BB24 ( cond ) i BB23 [0020] 1 1 [003..009) i BB24 [0021] 2 1 [009..019)-> BB27 (always) i newobj BB27 [0024] 3 1 [035..03B)-> BB29 ( cond ) i idxlen BB28 [0025] 1 1 [03B..043)-> BB30 ( cond ) i idxlen BB29 [0026] 2 1 [043..048) i BB30 [0027] 2 1 [048..06C) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) Renumber BB22 to BB31 Renumber BB23 to BB32 Renumber BB24 to BB33 Renumber BB27 to BB34 Renumber BB28 to BB35 Renumber BB29 to BB36 Renumber BB30 to BB37 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB31 [0019] 1 1 [000..003)-> BB33 ( cond ) i BB32 [0020] 1 1 [003..009) i BB33 [0021] 2 1 [009..019)-> BB34 (always) i newobj BB34 [0024] 3 1 [035..03B)-> BB36 ( cond ) i idxlen BB35 [0025] 1 1 [03B..043)-> BB37 ( cond ) i idxlen BB36 [0026] 2 1 [043..048) i BB37 [0027] 2 1 [048..06C) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB04 [012..04E), Finally at BB05..BB05 [04E..05B) New BlockSet epoch 1, # of blocks (including unused BB00): 1, bitset array size: 1 (short) ----------- Statements (and blocks) added due to the inlining of call [000055] ----------- Arguments setup: Inlinee method body:New Basic Block BB38 [0028] created. EH#0: New last block of try: BB38 Convert bbJumpKind of BB37 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB31 [000..000) -> BB33 (cond), preds={} succs={BB32,BB33} ***** BB31, stmt 1 [000168] ------------ * STMT void (IL ???... ???) [000167] ------------ \--* JTRUE void [000165] ------------ | /--* CNS_INT ref null [000166] ------------ \--* NE int [000046] ------------ \--* LCL_VAR ref V02 loc0 ------------ BB32 [000..000), preds={} succs={BB33} ***** BB32, stmt 2 [000256] ------------ * STMT void (IL ???... ???) [000254] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentNullException (exactContextHnd=0x0000017DD20D90D1) [000253] ------------ arg0 \--* CNS_INT int 2 ------------ BB33 [000..000) -> BB34 (always), preds={} succs={BB34} ***** BB33, stmt 3 [000175] ------------ * STMT void (IL ???... ???) [000172] ------------ | /--* CNS_INT int 0 [000174] IA------R--- \--* ASG struct (init) [000173] -------N---- \--* BLK(1) struct [000171] L----------- \--* ADDR byref [000170] ------------ \--* LCL_VAR int V10 tmp4 ***** BB33, stmt 4 [000181] ------------ * STMT void (IL ???... ???) [000180] ------------ \--* NOP void ***** BB33, stmt 5 [000188] ------------ * STMT void (IL ???... ???) [000187] ------------ \--* NOP void ------------ BB34 [000..000) -> BB36 (cond), preds={} succs={BB35,BB36} ***** BB34, stmt 6 [000201] ------------ * STMT void (IL ???... ???) [000200] ---X-------- \--* JTRUE void [000198] ---X-------- | /--* CAST int <- int [000197] ---X-------- | | \--* ARR_LENGTH int [000196] ------------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-----U-- \--* GT int [000195] ------------ \--* CNS_INT int 0 ------------ BB35 [000..000) -> BB37 (cond), preds={} succs={BB36,BB37} ***** BB35, stmt 7 [000251] ------------ * STMT void (IL ???... ???) [000250] ---X-------- \--* JTRUE void [000247] ---X-------- | /--* CAST int <- int [000246] ---X-------- | | \--* ARR_LENGTH int [000245] ------------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-----U-- \--* LE int [000244] ------------ \--* LCL_VAR int V03 loc1 ------------ BB36 [000..000), preds={} succs={BB37} ***** BB36, stmt 8 [000204] ------------ * STMT void (IL ???... ???) [000203] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException (exactContextHnd=0x0000017DD20D90D1) ------------ BB37 [000..000), preds={} succs={BB38} ***** BB37, stmt 9 [000211] ------------ * STMT void (IL ???... ???) [000209] I-C-G------- \--* CALL byref JitHelpers.GetRawSzArrayData (exactContextHnd=0x0000017DD4CFEC91) [000208] ------------ arg0 \--* LCL_VAR ref V02 loc0 ***** BB37, stmt 10 [000215] ------------ * STMT void (IL ???... ???) [000213] I-C-G------- \--* CALL byref Unsafe.As (exactContextHnd=0x0000017DD5052698) [000212] --C--------- arg0 \--* RET_EXPR byref (inl return from call [000209]) ***** BB37, stmt 11 [000221] ------------ * STMT void (IL ???... ???) [000218] I-C-G------- \--* CALL byref Unsafe.Add (exactContextHnd=0x0000017DD5476D70) [000216] --C--------- arg0 +--* RET_EXPR byref (inl return from call [000213]) [000217] ------------ arg1 \--* CNS_INT int 0 ***** BB37, stmt 12 [000226] ------------ * STMT void (IL ???... ???) [000224] ------------ | /--* CNS_INT int 0 [000225] IA------R--- \--* ASG struct (init) [000223] D------N---- \--* LCL_VAR struct V12 tmp6 ***** BB37, stmt 13 [000232] ------------ * STMT void (IL ???... ???) [000222] --C--------- | /--* RET_EXPR byref (inl return from call [000218]) [000230] -AC--------- \--* ASG byref [000229] -------N---- \--* FIELD byref _value [000228] L----------- \--* ADDR byref [000227] ------------ \--* LCL_VAR struct V12 tmp6 ***** BB37, stmt 14 [000237] ------------ * STMT void (IL ???... ???) [000231] ------------ | /--* LCL_VAR struct V12 tmp6 [000236] -A------R--- \--* ASG struct (copy) [000235] ------------ \--* OBJ(8) struct [000234] ------------ \--* ADDR byref [000233] ------------ \--* FIELD struct _pointer [000206] L----------- \--* ADDR byref [000207] ------------ \--* LCL_VAR struct V07 tmp1 ***** BB37, stmt 15 [000242] ------------ * STMT void (IL ???... ???) [000048] ------------ | /--* LCL_VAR int V03 loc1 [000241] -A---------- \--* ASG int [000240] -------N---- \--* FIELD int _length [000238] L----------- \--* ADDR byref [000239] ------------ \--* LCL_VAR struct V07 tmp1 ------------------------------------------------------------------------------------------------------------------- Successfully inlined Span`1:.ctor(ref,int,int):this (108 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'Span`1:.ctor(ref,int,int):this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000256] in BB32: [000256] ------------ * STMT void (IL ???... ???) [000254] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentNullException (exactContextHnd=0x0000017DD20D90D1) [000253] ------------ arg0 \--* CNS_INT int 2 Argument #0: is a constant [000253] ------------ * CNS_INT int 2 INLINER: inlineInfo.tokenLookupContextHandle for ThrowHelper:ThrowArgumentNullException(int) set to 0x0000017DD20D90D1: Invoking compiler for the inlinee method ThrowHelper:ThrowArgumentNullException(int) : IL to import: IL_0000 02 ldarg.0 IL_0001 28 c8 01 00 06 call 0x60001C8 IL_0006 7a throw INLINER impTokenLookupContextHandle for ThrowHelper:ThrowArgumentNullException(int) is 0x0000017DD20D90D1. *************** In fgFindBasicBlocks() for ThrowHelper:ThrowArgumentNullException(int) Jump targets: none New Basic Block BB39 [0029] created. BB39 [000..007) Basic block list for 'ThrowHelper:ThrowArgumentNullException(int)' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB39 [0029] 1 0 [000..007) (throw ) rare -------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'Stream:Read(struct):int:this' calling 'ThrowHelper:ThrowArgumentNullException(int)' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement [000204] in BB36: [000204] ------------ * STMT void (IL ???... ???) [000203] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException (exactContextHnd=0x0000017DD20D90D1) INLINER: inlineInfo.tokenLookupContextHandle for ThrowHelper:ThrowArgumentOutOfRangeException() set to 0x0000017DD20D90D1: Invoking compiler for the inlinee method ThrowHelper:ThrowArgumentOutOfRangeException() : IL to import: IL_0000 73 b4 0f 00 06 newobj 0x6000FB4 IL_0005 7a throw INLINER impTokenLookupContextHandle for ThrowHelper:ThrowArgumentOutOfRangeException() is 0x0000017DD20D90D1. *************** In fgFindBasicBlocks() for ThrowHelper:ThrowArgumentOutOfRangeException() Jump targets: none New Basic Block BB40 [0029] created. BB40 [000..006) Basic block list for 'ThrowHelper:ThrowArgumentOutOfRangeException()' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB40 [0029] 1 0 [000..006) (throw ) rare -------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'Stream:Read(struct):int:this' calling 'ThrowHelper:ThrowArgumentOutOfRangeException()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement [000211] in BB37: [000211] ------------ * STMT void (IL ???... ???) [000209] I-C-G------- \--* CALL byref JitHelpers.GetRawSzArrayData (exactContextHnd=0x0000017DD4CFEC91) [000208] ------------ arg0 \--* LCL_VAR ref V02 loc0 Argument #0: is a local var [000208] ------------ * LCL_VAR ref V02 loc0 INLINER: inlineInfo.tokenLookupContextHandle for JitHelpers:GetRawSzArrayData(ref):byref set to 0x0000017DD4CFEC91: Invoking compiler for the inlinee method JitHelpers:GetRawSzArrayData(ref):byref : IL to import: IL_0000 02 ldarg.0 IL_0001 7c 9c 17 00 04 ldflda 0x400179C IL_0006 2a ret INLINER impTokenLookupContextHandle for JitHelpers:GetRawSzArrayData(ref):byref is 0x0000017DD4CFEC91. *************** In fgFindBasicBlocks() for JitHelpers:GetRawSzArrayData(ref):byref Jump targets: none New Basic Block BB41 [0029] created. BB41 [000..007) Basic block list for 'JitHelpers:GetRawSzArrayData(ref):byref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB41 [0029] 1 1 [000..007) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for JitHelpers:GetRawSzArrayData(ref):byref impImportBlockPending for BB41 Importing BB41 (PC=000) of 'JitHelpers:GetRawSzArrayData(ref):byref' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldflda 0400179C [ 1] 6 (0x006) ret Inlinee Return expression (before normalization) => [000260] ---XG------- * ADDR byref [000259] ---XG------- \--* FIELD ubyte m_arrayData [000208] ------------ \--* LCL_VAR ref V02 loc0 Inlinee Return expression (after normalization) => [000260] ---XG------- * ADDR byref [000259] ---XG------- \--* FIELD ubyte m_arrayData [000208] ------------ \--* LCL_VAR ref V02 loc0 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB41 [0029] 1 1 [000..007) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000209] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000209] is [000260] ---XG------- * ADDR byref [000259] ---XG------- \--* FIELD ubyte m_arrayData [000208] ------------ \--* LCL_VAR ref V02 loc0 Successfully inlined JitHelpers:GetRawSzArrayData(ref):byref (7 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stream:Read(struct):int:this' calling 'JitHelpers:GetRawSzArrayData(ref):byref' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement [000215] in BB37: [000215] ------------ * STMT void (IL ???... ???) [000213] I-C-G------- \--* CALL byref Unsafe.As (exactContextHnd=0x0000017DD5052698) [000212] --C--------- arg0 \--* RET_EXPR byref (inl return from call [000260]) Argument #0: has global refs has side effects [000260] ---XG------- * ADDR byref [000259] ---XG------- \--* FIELD ubyte m_arrayData [000208] ------------ \--* LCL_VAR ref V02 loc0 INLINER: inlineInfo.tokenLookupContextHandle for Unsafe:As(byref):byref set to 0x0000017DD5052698: Invoking compiler for the inlinee method Unsafe:As(byref):byref : IL to import: IL_0000 02 ldarg.0 IL_0001 2a ret INLINER impTokenLookupContextHandle for Unsafe:As(byref):byref is 0x0000017DD5052698. *************** In fgFindBasicBlocks() for Unsafe:As(byref):byref Jump targets: none New Basic Block BB42 [0030] created. BB42 [000..002) Basic block list for 'Unsafe:As(byref):byref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB42 [0030] 1 1 [000..002) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Unsafe:As(byref):byref impImportBlockPending for BB42 Importing BB42 (PC=000) of 'Unsafe:As(byref):byref' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 13 (V13 tmp7) called for Inlining Arg. [ 1] 1 (0x001) ret Inlinee Return expression (before normalization) => [000263] ------------ * LCL_VAR byref V13 tmp7 Inlinee Return expression (after normalization) => [000263] ------------ * LCL_VAR byref V13 tmp7 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB42 [0030] 1 1 [000..002) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000213] ----------- Arguments setup: [000266] ------------ * STMT void (IL ???... ???) [000260] ---XG------- | /--* ADDR byref [000259] ---XG------- | | \--* FIELD ubyte m_arrayData [000208] ------------ | | \--* LCL_VAR ref V02 loc0 [000265] -A-XG------- \--* ASG byref [000264] D------N---- \--* LCL_VAR byref V13 tmp7 Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000213] is [000263] ------------ * LCL_VAR byref V13 tmp7 Successfully inlined Unsafe:As(byref):byref (2 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'Unsafe:As(byref):byref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000221] in BB37: [000221] ------------ * STMT void (IL ???... ???) [000218] I-C-G------- \--* CALL byref Unsafe.Add (exactContextHnd=0x0000017DD5476D70) [000216] --C--------- arg0 +--* RET_EXPR byref (inl return from call [000263]) [000217] ------------ arg1 \--* CNS_INT int 0 Argument #0: is a local var [000263] ------------ * LCL_VAR byref V13 tmp7 Argument #1: is a constant [000217] ------------ * CNS_INT int 0 INLINER: inlineInfo.tokenLookupContextHandle for Unsafe:Add(byref,int):byref set to 0x0000017DD5476D70: Invoking compiler for the inlinee method Unsafe:Add(byref,int):byref : IL to import: IL_0000 03 ldarg.1 IL_0001 fe 1c ad 00 00 1b sizeof 0x1B0000AD IL_0007 d3 conv.i IL_0008 5a mul IL_0009 02 ldarg.0 IL_000a 58 add IL_000b 2a ret INLINER impTokenLookupContextHandle for Unsafe:Add(byref,int):byref is 0x0000017DD5476D70. *************** In fgFindBasicBlocks() for Unsafe:Add(byref,int):byref Jump targets: none New Basic Block BB43 [0031] created. BB43 [000..00C) Basic block list for 'Unsafe:Add(byref,int):byref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB43 [0031] 1 1 [000..00C) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Unsafe:Add(byref,int):byref impImportBlockPending for BB43 Importing BB43 (PC=000) of 'Unsafe:Add(byref,int):byref' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) sizeof 1B0000AD [ 2] 7 (0x007) conv.i [ 2] 8 (0x008) mul [ 1] 9 (0x009) ldarg.0 [ 2] 10 (0x00a) add [ 1] 11 (0x00b) ret Inlinee Return expression (before normalization) => [000263] ------------ /--* LCL_VAR byref V13 tmp7 [000274] ------------ * ADD byref [000271] ------------ | /--* CAST long <- int [000270] ------------ | | \--* CNS_INT int 1 [000273] ------------ \--* MUL long [000272] ------------ \--* CAST long <- int [000269] ------------ \--* CNS_INT int 0 Inlinee Return expression (after normalization) => [000263] ------------ /--* LCL_VAR byref V13 tmp7 [000274] ------------ * ADD byref [000271] ------------ | /--* CAST long <- int [000270] ------------ | | \--* CNS_INT int 1 [000273] ------------ \--* MUL long [000272] ------------ \--* CAST long <- int [000269] ------------ \--* CNS_INT int 0 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB43 [0031] 1 1 [000..00C) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000218] ----------- Arguments setup: Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000218] is [000263] ------------ /--* LCL_VAR byref V13 tmp7 [000274] ------------ * ADD byref [000271] ------------ | /--* CAST long <- int [000270] ------------ | | \--* CNS_INT int 1 [000273] ------------ \--* MUL long [000272] ------------ \--* CAST long <- int [000269] ------------ \--* CNS_INT int 0 Successfully inlined Unsafe:Add(byref,int):byref (12 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'Unsafe:Add(byref,int):byref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000222] with [000274] [000222] --C--------- * RET_EXPR byref (inl return from call [000274]) Inserting the inline return expression [000263] ------------ /--* LCL_VAR byref V13 tmp7 [000274] ------------ * ADD byref [000271] ------------ | /--* CAST long <- int [000270] ------------ | | \--* CNS_INT int 1 [000273] ------------ \--* MUL long [000272] ------------ \--* CAST long <- int [000269] ------------ \--* CNS_INT int 0 Expanding INLINE_CANDIDATE in statement [000072] in BB38: [000072] ------------ * STMT void (IL 0x042...0x04B) [000068] I-C-G------- \--* CALL void Span`1.CopyTo (exactContextHnd=0x0000017DD4D6C239) [000066] L----------- this in rcx +--* ADDR byref [000065] ------------ | \--* LCL_VAR struct V04 loc2 [000070] x----------- arg1 \--* OBJ(16) struct [000069] L----------- \--* ADDR byref [000067] ------------ \--* LCL_VAR struct V01 arg1 thisArg: is a constant is byref to a struct local [000066] L----------- * ADDR byref [000065] ------------ \--* LCL_VAR struct V04 loc2 Argument #1: has caller local ref [000070] x----------- * OBJ(16) struct [000069] L----------- \--* ADDR byref [000067] ------------ \--* LCL_VAR struct V01 arg1 INLINER: inlineInfo.tokenLookupContextHandle for Span`1:CopyTo(struct):this set to 0x0000017DD4D6C239: Invoking compiler for the inlinee method Span`1:CopyTo(struct):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 28 68 01 00 0a call 0xA000168 IL_0007 2d 05 brtrue.s 5 (IL_000e) IL_0009 28 bb 01 00 06 call 0x60001BB IL_000e 2a ret INLINER impTokenLookupContextHandle for Span`1:CopyTo(struct):this is 0x0000017DD4D6C239. *************** In fgFindBasicBlocks() for Span`1:CopyTo(struct):this Jump targets: IL_000e New Basic Block BB44 [0032] created. BB44 [000..009) New Basic Block BB45 [0033] created. BB45 [009..00E) New Basic Block BB46 [0034] created. BB46 [00E..00F) Basic block list for 'Span`1:CopyTo(struct):this' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB44 [0032] 1 1 [000..009)-> BB46 ( cond ) BB45 [0033] 1 1 [009..00E) BB46 [0034] 2 1 [00E..00F) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for Span`1:CopyTo(struct):this impImportBlockPending for BB44 Importing BB44 (PC=000) of 'Span`1:CopyTo(struct):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 14 (V14 tmp8) called for Inlining Arg. [ 2] 2 (0x002) call 0A000168 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Calling impNormStructVal on: [000279] ------------ * LCL_VAR struct V14 tmp8 resulting tree: [000282] x----------- * OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 [000284] ------------ * STMT void [000280] I-C-G------- \--* CALL int Span`1.TryCopyTo (exactContextHnd=0x0000017DD4D6C239) [000277] L----------- this in rcx +--* ADDR byref [000278] ------------ | \--* LCL_VAR struct V04 loc2 [000282] x----------- arg1 \--* OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 [ 1] 7 (0x007) brtrue.s [000289] ------------ * STMT void [000288] --C--------- \--* JTRUE void [000286] ------------ | /--* CNS_INT int 0 [000287] --C--------- \--* NE int [000285] --C--------- \--* RET_EXPR int (inl return from call [000280]) impImportBlockPending for BB45 impImportBlockPending for BB46 Importing BB46 (PC=014) of 'Span`1:CopyTo(struct):this' [ 0] 14 (0x00e) ret Importing BB45 (PC=009) of 'Span`1:CopyTo(struct):this' [ 0] 9 (0x009) call 060001BB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000293] ------------ * STMT void [000292] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort (exactContextHnd=0x0000017DD20D90D1) impImportBlockPending for BB46 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB44 [0032] 1 1 [000..009)-> BB46 ( cond ) i BB45 [0033] 1 1 [009..00E) i BB46 [0034] 2 1 [00E..00F) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000068] ----------- Arguments setup: [000297] ------------ * STMT void (IL 0x042... ???) [000070] x----------- | /--* OBJ(16) struct [000069] L----------- | | \--* ADDR byref [000067] ------------ | | \--* LCL_VAR struct V01 arg1 [000296] -A------R--- \--* ASG struct (copy) [000294] D----------- \--* LCL_VAR struct V14 tmp8 Inlinee method body:New Basic Block BB47 [0035] created. EH#0: New last block of try: BB47 Convert bbJumpKind of BB46 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB44 [042..043) -> BB46 (cond), preds={} succs={BB45,BB46} ***** BB44, stmt 1 [000284] ------------ * STMT void (IL 0x042... ???) [000280] I-C-G------- \--* CALL int Span`1.TryCopyTo (exactContextHnd=0x0000017DD4D6C239) [000277] L----------- this in rcx +--* ADDR byref [000278] ------------ | \--* LCL_VAR struct V04 loc2 [000282] x----------- arg1 \--* OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 ***** BB44, stmt 2 [000289] ------------ * STMT void (IL 0x042... ???) [000288] --C--------- \--* JTRUE void [000286] ------------ | /--* CNS_INT int 0 [000287] --C--------- \--* NE int [000285] --C--------- \--* RET_EXPR int (inl return from call [000280]) ------------ BB45 [042..043), preds={} succs={BB46} ***** BB45, stmt 3 [000293] ------------ * STMT void (IL 0x042... ???) [000292] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort (exactContextHnd=0x0000017DD20D90D1) ------------ BB46 [042..043), preds={} succs={BB47} ------------------------------------------------------------------------------------------------------------------- Successfully inlined Span`1:CopyTo(struct):this (15 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Stream:Read(struct):int:this' calling 'Span`1:CopyTo(struct):this' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement [000284] in BB44: [000284] ------------ * STMT void (IL 0x042... ???) [000280] I-C-G------- \--* CALL int Span`1.TryCopyTo (exactContextHnd=0x0000017DD4D6C239) [000277] L----------- this in rcx +--* ADDR byref [000278] ------------ | \--* LCL_VAR struct V04 loc2 [000282] x----------- arg1 \--* OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 thisArg: is a constant is byref to a struct local [000277] L----------- * ADDR byref [000278] ------------ \--* LCL_VAR struct V04 loc2 Argument #1: [000282] x----------- * OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 INLINER: inlineInfo.tokenLookupContextHandle for Span`1:TryCopyTo(struct):bool:this set to 0x0000017DD4D6C239: Invoking compiler for the inlinee method Span`1:TryCopyTo(struct):bool:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b a0 01 00 0a ldfld 0xA0001A0 IL_0006 0f 01 ldarga.s 0x1 IL_0008 28 8c 01 00 0a call 0xA00018C IL_000d 36 02 ble.un.s 2 (IL_0011) IL_000f 16 ldc.i4.0 IL_0010 2a ret IL_0011 03 ldarg.1 IL_0012 7b 9f 01 00 0a ldfld 0xA00019F IL_0017 0a stloc.0 IL_0018 12 00 ldloca.s 0x0 IL_001a 28 8a 01 00 0a call 0xA00018A IL_001f 02 ldarg.0 IL_0020 7b 9f 01 00 0a ldfld 0xA00019F IL_0025 0a stloc.0 IL_0026 12 00 ldloca.s 0x0 IL_0028 28 8a 01 00 0a call 0xA00018A IL_002d 02 ldarg.0 IL_002e 7b a0 01 00 0a ldfld 0xA0001A0 IL_0033 28 ee 00 00 2b call 0x2B0000EE IL_0038 17 ldc.i4.1 IL_0039 2a ret INLINER impTokenLookupContextHandle for Span`1:TryCopyTo(struct):bool:this is 0x0000017DD4D6C239. *************** In fgFindBasicBlocks() for Span`1:TryCopyTo(struct):bool:this weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight=147 : state 54 [ ble.un.s ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 19 : state 42 [ ret ] weight= 29 : state 192 [ ldarg.1 -> ldfld ] weight= 6 : state 11 [ stloc.0 ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 6 : state 11 [ stloc.0 ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 79 : state 40 [ call ] weight= 28 : state 24 [ ldc.i4.1 ] weight= 19 : state 42 [ ret ] multiplier in methods of promotable struct increased to 3. Inline candidate callsite is boring. Multiplier increased to 4.3. calleeNativeSizeEstimate=877 callsiteNativeSizeEstimate=135 benefit multiplier=4.3 threshold=580 Native estimate for function size exceeds threshold for inlining 87.7 > 58 (multiplier = 4.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Stream:Read(struct):int:this' calling 'Span`1:TryCopyTo(struct):bool:this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000285] with [000280] [000285] --C--------- * RET_EXPR int (inl return from call [000280]) Inserting the inline return expression [000280] --C-G------- * CALL int Span`1.TryCopyTo [000277] L----------- this in rcx +--* ADDR byref [000278] ------------ | \--* LCL_VAR struct V04 loc2 [000282] x----------- arg1 \--* OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 Expanding INLINE_CANDIDATE in statement [000293] in BB45: [000293] ------------ * STMT void (IL 0x042... ???) [000292] I-C-G------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort (exactContextHnd=0x0000017DD20D90D1) INLINER: inlineInfo.tokenLookupContextHandle for ThrowHelper:ThrowArgumentException_DestinationTooShort() set to 0x0000017DD20D90D1: Invoking compiler for the inlinee method ThrowHelper:ThrowArgumentException_DestinationTooShort() : IL to import: IL_0000 28 b4 0b 00 06 call 0x6000BB4 IL_0005 73 a7 0f 00 06 newobj 0x6000FA7 IL_000a 7a throw INLINER impTokenLookupContextHandle for ThrowHelper:ThrowArgumentException_DestinationTooShort() is 0x0000017DD20D90D1. *************** In fgFindBasicBlocks() for ThrowHelper:ThrowArgumentException_DestinationTooShort() Jump targets: none New Basic Block BB48 [0036] created. BB48 [000..00B) Basic block list for 'ThrowHelper:ThrowArgumentException_DestinationTooShort()' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB48 [0036] 1 0 [000..00B) (throw ) rare -------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'Stream:Read(struct):int:this' calling 'ThrowHelper:ThrowArgumentException_DestinationTooShort()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement [000100] in BB05: [000100] ------------ * STMT void (IL 0x04E...0x05A) [000099] I-C-G------- \--* CALL ref ArrayPool`1.get_Shared (exactContextHnd=0x0000017DD4DBCE69) INLINER: inlineInfo.tokenLookupContextHandle for ArrayPool`1:get_Shared():ref set to 0x0000017DD4DBCE69: Invoking compiler for the inlinee method ArrayPool`1:get_Shared():ref : IL to import: IL_0000 d0 a6 00 00 1b ldtoken 0x1B0000A6 IL_0005 28 2a 09 00 06 call 0x600092A IL_000a d0 a5 00 00 02 ldtoken 0x20000A5 IL_000f 28 2a 09 00 06 call 0x600092A IL_0014 28 31 09 00 06 call 0x6000931 IL_0019 2c 0b brfalse.s 11 (IL_0026) IL_001b 28 d7 18 00 06 call 0x60018D7 IL_0020 74 4e 00 00 1b castclass 0x1B00004E IL_0025 2a ret IL_0026 d0 a6 00 00 1b ldtoken 0x1B0000A6 IL_002b 28 2a 09 00 06 call 0x600092A IL_0030 d0 a6 00 00 02 ldtoken 0x20000A6 IL_0035 28 2a 09 00 06 call 0x600092A IL_003a 28 31 09 00 06 call 0x6000931 IL_003f 2c 0b brfalse.s 11 (IL_004c) IL_0041 28 d8 18 00 06 call 0x60018D8 IL_0046 74 4e 00 00 1b castclass 0x1B00004E IL_004b 2a ret IL_004c 7e 5e 04 00 0a ldsfld 0xA00045E IL_0051 2a ret INLINER impTokenLookupContextHandle for ArrayPool`1:get_Shared():ref is 0x0000017DD4DBCE69. *************** In fgFindBasicBlocks() for ArrayPool`1:get_Shared():ref Jump targets: IL_0026 IL_004c New Basic Block BB49 [0036] created. BB49 [000..01B) New Basic Block BB50 [0037] created. BB50 [01B..026) New Basic Block BB51 [0038] created. BB51 [026..041) New Basic Block BB52 [0039] created. BB52 [041..04C) New Basic Block BB53 [0040] created. BB53 [04C..052) lvaGrabTemp returning 15 (V15 tmp9) (a long lifetime temp) called for Inline return value spill temp. lvaSetClass: setting class for V15 to (0000017DD4DBCE68) ArrayPool`1 Basic block list for 'ArrayPool`1:get_Shared():ref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB49 [0036] 1 1 [000..01B)-> BB51 ( cond ) BB50 [0037] 1 1 [01B..026) (return) BB51 [0038] 1 1 [026..041)-> BB53 ( cond ) BB52 [0039] 1 1 [041..04C) (return) BB53 [0040] 1 1 [04C..052) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for ArrayPool`1:get_Shared():ref impImportBlockPending for BB49 Importing BB49 (PC=000) of 'ArrayPool`1:get_Shared():ref' [ 0] 0 (0x000) ldtoken [ 1] 5 (0x005) call 0600092A In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 1] 10 (0x00a) ldtoken [ 2] 15 (0x00f) call 0600092A In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 2] 20 (0x014) call 06000931 In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Importing Type.op_*Equality intrinsic Folding call to Type:op_Equality to a simple compare via EQ Optimizing compare of types-from-handles to instead compare handles Asking runtime to compare 0000017DD209A650 (Byte) and 0000017DD209A650 (Byte) for equality Runtime reports comparison is known at jit time: 1 [ 1] 25 (0x019) brfalse.s Folding operator with constant nodes into a constant: [000309] ------------ /--* CNS_INT int 0 [000310] ------------ * EQ int [000308] ------------ \--* CNS_INT int 1 Bashed to int constant: [000310] ------------ * CNS_INT int 0 The block falls through into the next BB50 impImportBlockPending for BB50 Importing BB50 (PC=027) of 'ArrayPool`1:get_Shared():ref' [ 0] 27 (0x01b) call 060018D7 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [000313] ------------ * STMT void [000312] I-C-G------- \--* CALL ref ArrayPools.get_BytePool (exactContextHnd=0x0000017DD4C39AB1) [ 1] 32 (0x020) castclass 1B00004E Considering optimization of castclass from 0000017DD4DBCFD0 (TlsOverPerCoreLockedStacksArrayPool`1) to 0000017DD4DBCE68 (ArrayPool`1) Cast will succeed, optimizing to simply return input [ 1] 37 (0x025) ret Inlinee Return expression (before normalization) => [000314] --C--------- * RET_EXPR ref (inl return from call [000312]) [000318] ------------ * STMT void [000314] --C--------- | /--* RET_EXPR ref (inl return from call [000312]) [000317] -AC--------- \--* ASG ref [000316] D------N---- \--* LCL_VAR ref V15 tmp9 Inlinee Return expression (after normalization) => [000319] ------------ * LCL_VAR ref V15 tmp9 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB49 [0036] 1 1 [000..01B) i BB50 [0037] 1 1 [01B..026) (return) i BB51 [0038] 1 1 [026..041)-> BB53 ( cond ) BB52 [0039] 1 1 [041..04C) (return) BB53 [0040] 1 1 [04C..052) (return) -------------------------------------------------------------------------------------------------------------------------------------- BB51 was not imported, marked as removed (1) BB52 was not imported, marked as removed (2) BB53 was not imported, marked as removed (3) Renumbering the basic blocks for fgRemoveEmptyBlocks *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB49 [0036] 1 1 [000..01B) i BB50 [0037] 1 1 [01B..026) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB05 [04E..05B) Renumber BB49 to BB54 Renumber BB50 to BB55 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB54 [0036] 1 1 [000..01B) i BB55 [0037] 1 1 [01B..026) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB05 [04E..05B) New BlockSet epoch 1, # of blocks (including unused BB00): 1, bitset array size: 1 (short) lvaUpdateClass: Updating class for V15 from (0000017DD4DBCE68) ArrayPool`1 to (0000017DD4DBCFD0) TlsOverPerCoreLockedStacksArrayPool`1 ----------- Statements (and blocks) added due to the inlining of call [000099] ----------- Inlinee method body:New Basic Block BB56 [0041] created. EH#0: New last block of handler: BB56 Convert bbJumpKind of BB55 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB54 [04E..04F), preds={} succs={BB55} ------------ BB55 [04E..04F), preds={} succs={BB56} ***** BB55, stmt 1 [000313] ------------ * STMT void (IL 0x04E... ???) [000312] I-C-G------- \--* CALL ref ArrayPools.get_BytePool (exactContextHnd=0x0000017DD4C39AB1) ***** BB55, stmt 2 [000318] ------------ * STMT void (IL 0x04E... ???) [000314] --C--------- | /--* RET_EXPR ref (inl return from call [000312]) [000317] -AC--------- \--* ASG ref [000316] D------N---- \--* LCL_VAR ref V15 tmp9 ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000099] is [000319] ------------ * LCL_VAR ref V15 tmp9 Successfully inlined ArrayPool`1:get_Shared():ref (82 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- BB05 becomes empty INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'ArrayPool`1:get_Shared():ref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement [000313] in BB55: [000313] ------------ * STMT void (IL 0x04E... ???) [000312] I-C-G------- \--* CALL ref ArrayPools.get_BytePool (exactContextHnd=0x0000017DD4C39AB1) INLINER: inlineInfo.tokenLookupContextHandle for ArrayPools:get_BytePool():ref set to 0x0000017DD4C39AB1: Invoking compiler for the inlinee method ArrayPools:get_BytePool():ref : IL to import: IL_0000 7e ad 05 00 04 ldsfld 0x40005AD IL_0005 2a ret INLINER impTokenLookupContextHandle for ArrayPools:get_BytePool():ref is 0x0000017DD4C39AB1. *************** In fgFindBasicBlocks() for ArrayPools:get_BytePool():ref Jump targets: none New Basic Block BB57 [0042] created. BB57 [000..006) Basic block list for 'ArrayPools:get_BytePool():ref' -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB57 [0042] 1 1 [000..006) (return) -------------------------------------------------------------------------------------------------------------------------------------- *************** In impImport() for ArrayPools:get_BytePool():ref impImportBlockPending for BB57 Importing BB57 (PC=000) of 'ArrayPools:get_BytePool():ref' [ 0] 0 (0x000) ldsfld 040005AD [ 1] 5 (0x005) ret Inlinee Return expression (before normalization) => [000330] --CXG------- * IND ref [000328] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG------- \--* ADD byref [000327] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----------- arg0 +--* IND long [000322] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] ------------ arg1 \--* CNS_INT int 327 Inlinee Return expression (after normalization) => [000330] --CXG------- * IND ref [000328] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG------- \--* ADD byref [000327] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----------- arg0 +--* IND long [000322] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] ------------ arg1 \--* CNS_INT int 327 After impImport() added block for try,catch,finally -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB57 [0042] 1 1 [000..006) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ----------- Statements (and blocks) added due to the inlining of call [000312] ----------- Inlinee method body:fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000312] is [000330] --CXG------- * IND ref [000328] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG------- \--* ADD byref [000327] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----------- arg0 +--* IND long [000322] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] ------------ arg1 \--* CNS_INT int 327 Successfully inlined ArrayPools:get_BytePool():ref (6 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'Stream:Read(struct):int:this' calling 'ArrayPools:get_BytePool():ref' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Replacing the return expression placeholder [000314] with [000330] [000314] --C--------- * RET_EXPR ref (inl return from call [000330]) Inserting the inline return expression [000330] --CXG------- * IND ref [000328] ------------ | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG------- \--* ADD byref [000327] H-CXG------- \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----------- arg0 +--* IND long [000322] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] ------------ arg1 \--* CNS_INT int 327 Replacing the return expression placeholder [000101] with [000319] [000101] --C--------- * RET_EXPR ref (inl return from call [000319]) Inserting the inline return expression [000319] ------------ * LCL_VAR ref V15 tmp9 **** Late devirt opportunity [000104] --C-G------- * CALLV ind void ArrayPool`1.Return [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is TlsOverPerCoreLockedStacksArrayPool`1 [final] (attrib 21000010) base method is ArrayPool`1::Return devirt to TlsOverPerCoreLockedStacksArrayPool`1::Return -- final class [000104] --C-G------- * CALLV ind void ArrayPool`1.Return [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 final class; can devirtualize ... after devirt... [000104] --C-G------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 *************** After fgInline() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) H0 finally { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..012), preds={} succs={BB14} ------------ BB14 [000..001), preds={} succs={BB15} ------------ BB15 [000..001), preds={} succs={BB16} ***** BB15, stmt 1 [000128] ------------ * STMT void (IL 0x000... ???) [000140] --CXG------- | /--* IND ref [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG------- | | \--* ADD byref [000137] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----------- arg0 | | +--* IND long [000132] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] ------------ arg1 | | \--* CNS_INT int 327 [000127] -AC--------- \--* ASG ref [000126] D------N---- \--* LCL_VAR ref V09 tmp3 ------------ BB16 [???..???), preds={} succs={BB02} ***** BB16, stmt 2 [000010] ------------ * STMT void (IL ???... ???) [000129] ------------ | /--* LCL_VAR ref V09 tmp3 [000009] -AC--------- \--* ASG ref [000008] D------N---- \--* LCL_VAR ref V06 tmp0 ***** BB16, stmt 3 [000017] ------------ * STMT void (IL ???... ???) [000013] --C-G------- | /--* CALLV ind ref ArrayPool`1.Rent [000011] ------------ this in rcx | | +--* LCL_VAR ref V06 tmp0 [000145] ----G------- arg1 | | \--* FIELD int _length [000143] L----------- | | \--* ADDR byref [000144] ------------ | | \--* LCL_VAR struct V01 arg1 [000016] -AC-G------- \--* ASG ref [000015] D------N---- \--* LCL_VAR ref V02 loc0 ------------ BB02 [012..02E) -> BB04 (cond), preds={} succs={BB03,BB04} ***** BB02, stmt 4 [000033] ------------ * STMT void (IL ???... ???) [000027] --C-G------- | /--* CALLV ind int Stream.Read [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this [000020] ------------ arg1 | | +--* LCL_VAR ref V02 loc0 [000021] ------------ arg2 | | +--* CNS_INT int 0 [000150] ----G------- arg3 | | \--* FIELD int _length [000148] L----------- | | \--* ADDR byref [000149] ------------ | | \--* LCL_VAR struct V01 arg1 [000032] -AC-G------- \--* ASG int [000031] D------N---- \--* LCL_VAR int V03 loc1 ***** BB02, stmt 5 [000044] ------------ * STMT void (IL ???... ???) [000043] --C--------- \--* JTRUE void [000041] --C--------- | /--* CAST long <- int [000155] ----G------- | | \--* FIELD int _length [000153] L----------- | | \--* ADDR byref [000154] ------------ | | \--* LCL_VAR struct V01 arg1 [000042] --C--------- \--* LE int [000035] ---------U-- \--* CAST long <- ulong <- uint [000034] ------------ \--* LCL_VAR int V03 loc1 ------------ BB03 [02E..039) (throw), preds={} succs={} ***** BB03, stmt 6 [000089] ------------ * STMT void (IL ???... ???) [000086] ------------ | /--* ALLOCOBJ ref [000085] ------------ | | \--* CNS_INT(h) long 0x17dd3b22ac8 method [000088] -A---------- \--* ASG ref [000087] D------N---- \--* LCL_VAR ref V08 tmp2 ***** BB03, stmt 7 [000093] ------------ * STMT void (IL ???... ???) [000091] --C-G------- \--* CALL void IOException..ctor [000090] ------------ this in rcx +--* LCL_VAR ref V08 tmp2 [000160] --C-G------- arg1 \--* CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null ***** BB03, stmt 8 [000097] ------------ * STMT void (IL 0x038... ???) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW [000094] ------------ arg0 \--* LCL_VAR ref V08 tmp2 ------------ BB04 [039..04E), preds={} succs={BB31} ***** BB04, stmt 9 [000052] ------------ * STMT void (IL 0x039...0x041) [000050] ------------ | /--* CNS_INT int 0 [000051] IA------R--- \--* ASG struct (init) [000049] D------N---- \--* LCL_VAR struct V07 tmp1 ------------ BB31 [000..000) -> BB33 (cond), preds={} succs={BB32,BB33} ***** BB31, stmt 10 [000168] ------------ * STMT void (IL ???... ???) [000167] ------------ \--* JTRUE void [000165] ------------ | /--* CNS_INT ref null [000166] ------------ \--* NE int [000046] ------------ \--* LCL_VAR ref V02 loc0 ------------ BB32 [000..000), preds={} succs={BB33} ***** BB32, stmt 11 [000256] ------------ * STMT void (IL ???... ???) [000254] --C-G------- \--* CALL void ThrowHelper.ThrowArgumentNullException [000253] ------------ arg0 \--* CNS_INT int 2 ------------ BB33 [000..000) -> BB34 (always), preds={} succs={BB34} ***** BB33, stmt 12 [000175] ------------ * STMT void (IL ???... ???) [000172] ------------ | /--* CNS_INT int 0 [000174] IA------R--- \--* ASG struct (init) [000173] -------N---- \--* BLK(1) struct [000171] L----------- \--* ADDR byref [000170] ------------ \--* LCL_VAR int V10 tmp4 ***** BB33, stmt 13 [000181] ------------ * STMT void (IL ???... ???) [000180] ------------ \--* NOP void ***** BB33, stmt 14 [000188] ------------ * STMT void (IL ???... ???) [000187] ------------ \--* NOP void ------------ BB34 [000..000) -> BB36 (cond), preds={} succs={BB35,BB36} ***** BB34, stmt 15 [000201] ------------ * STMT void (IL ???... ???) [000200] ---X-------- \--* JTRUE void [000198] ---X-------- | /--* CAST int <- int [000197] ---X-------- | | \--* ARR_LENGTH int [000196] ------------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-----U-- \--* GT int [000195] ------------ \--* CNS_INT int 0 ------------ BB35 [000..000) -> BB37 (cond), preds={} succs={BB36,BB37} ***** BB35, stmt 16 [000251] ------------ * STMT void (IL ???... ???) [000250] ---X-------- \--* JTRUE void [000247] ---X-------- | /--* CAST int <- int [000246] ---X-------- | | \--* ARR_LENGTH int [000245] ------------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-----U-- \--* LE int [000244] ------------ \--* LCL_VAR int V03 loc1 ------------ BB36 [000..000), preds={} succs={BB37} ***** BB36, stmt 17 [000204] ------------ * STMT void (IL ???... ???) [000203] --C-G------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException ------------ BB37 [000..000), preds={} succs={BB38} ***** BB37, stmt 18 [000266] ------------ * STMT void (IL ???... ???) [000260] ---XG------- | /--* ADDR byref [000259] ---XG------- | | \--* FIELD ubyte m_arrayData [000208] ------------ | | \--* LCL_VAR ref V02 loc0 [000265] -A-XG------- \--* ASG byref [000264] D------N---- \--* LCL_VAR byref V13 tmp7 ***** BB37, stmt 19 [000226] ------------ * STMT void (IL ???... ???) [000224] ------------ | /--* CNS_INT int 0 [000225] IA------R--- \--* ASG struct (init) [000223] D------N---- \--* LCL_VAR struct V12 tmp6 ***** BB37, stmt 20 [000232] ------------ * STMT void (IL ???... ???) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 [000274] ------------ | /--* ADD byref [000271] ------------ | | | /--* CAST long <- int [000270] ------------ | | | | \--* CNS_INT int 1 [000273] ------------ | | \--* MUL long [000272] ------------ | | \--* CAST long <- int [000269] ------------ | | \--* CNS_INT int 0 [000230] -AC--------- \--* ASG byref [000229] -------N---- \--* FIELD byref _value [000228] L----------- \--* ADDR byref [000227] ------------ \--* LCL_VAR struct V12 tmp6 ***** BB37, stmt 21 [000237] ------------ * STMT void (IL ???... ???) [000231] ------------ | /--* LCL_VAR struct V12 tmp6 [000236] -A------R--- \--* ASG struct (copy) [000235] ------------ \--* OBJ(8) struct [000234] ------------ \--* ADDR byref [000233] ------------ \--* FIELD struct _pointer [000206] L----------- \--* ADDR byref [000207] ------------ \--* LCL_VAR struct V07 tmp1 ***** BB37, stmt 22 [000242] ------------ * STMT void (IL ???... ???) [000048] ------------ | /--* LCL_VAR int V03 loc1 [000241] -A---------- \--* ASG int [000240] -------N---- \--* FIELD int _length [000238] L----------- \--* ADDR byref [000239] ------------ \--* LCL_VAR struct V07 tmp1 ------------ BB38 [???..???), preds={} succs={BB44} ***** BB38, stmt 23 [000064] ------------ * STMT void (IL 0x041... ???) [000060] ------------ | /--* LCL_VAR struct V07 tmp1 [000063] -A------R--- \--* ASG struct (copy) [000061] D----------- \--* LCL_VAR struct V04 loc2 ***** BB38, stmt 24 [000297] ------------ * STMT void (IL 0x042... ???) [000070] x----------- | /--* OBJ(16) struct [000069] L----------- | | \--* ADDR byref [000067] ------------ | | \--* LCL_VAR struct V01 arg1 [000296] -A------R--- \--* ASG struct (copy) [000294] D----------- \--* LCL_VAR struct V14 tmp8 ------------ BB44 [042..043) -> BB46 (cond), preds={} succs={BB45,BB46} ***** BB44, stmt 25 [000289] ------------ * STMT void (IL 0x042... ???) [000288] --C--------- \--* JTRUE void [000286] ------------ | /--* CNS_INT int 0 [000287] --C--------- \--* NE int [000280] --C-G------- \--* CALL int Span`1.TryCopyTo [000277] L----------- this in rcx +--* ADDR byref [000278] ------------ | \--* LCL_VAR struct V04 loc2 [000282] x----------- arg1 \--* OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct V14 tmp8 ------------ BB45 [042..043), preds={} succs={BB46} ***** BB45, stmt 26 [000293] ------------ * STMT void (IL 0x042... ???) [000292] --C-G------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort ------------ BB46 [042..043), preds={} succs={BB47} ------------ BB47 [???..???) -> BB07 (always), preds={} succs={BB07} ***** BB47, stmt 27 [000076] ------------ * STMT void (IL 0x04A... ???) [000073] ------------ | /--* LCL_VAR int V03 loc1 [000075] -A---------- \--* ASG int [000074] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB07 [???..???) -> BB05 (callf), preds={} succs={BB05} ------------ BB08 [???..???) -> BB06 (ALWAYS), preds={} succs={BB06} ------------ BB05 [04E..05B), preds={} succs={BB54} ------------ BB54 [04E..04F), preds={} succs={BB55} ------------ BB55 [04E..04F), preds={} succs={BB56} ***** BB55, stmt 28 [000318] ------------ * STMT void (IL 0x04E... ???) [000330] --CXG------- | /--* IND ref [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG------- | | \--* ADD byref [000327] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----------- arg0 | | +--* IND long [000322] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] ------------ arg1 | | \--* CNS_INT int 327 [000317] -AC--------- \--* ASG ref [000316] D------N---- \--* LCL_VAR ref V15 tmp9 ------------ BB56 [???..???) (finret), preds={} succs={BB08} ***** BB56, stmt 29 [000107] ------------ * STMT void (IL ???... ???) [000104] --C-G------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 ***** BB56, stmt 30 [000109] ------------ * STMT void (IL 0x05A... ???) [000108] ------------ \--* RETFILT void ------------ BB06 [05B..05D) (return), preds={} succs={} ***** BB06, stmt 31 [000080] ------------ * STMT void (IL 0x05B...0x05C) [000079] ------------ \--* RETURN int [000078] ------------ \--* LCL_VAR int V05 loc3 ------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB56 [04E..05B) **************** Inline Tree Inlines into 06001DC5 Stream:Read(struct):int:this [1 IL=0000 TR=000001 060018DA] [aggressive inline attribute] ArrayPool`1:get_Shared():ref [2 IL=0027 TR=000122 060018D7] [aggressive inline attribute] ArrayPools:get_BytePool():ref [3 IL=0007 TR=000006 060015C5] [below ALWAYS_INLINE size] Span`1:get_Length():int:this [0 IL=0012 TR=000013 060018DD] [FAILED: target not direct] ArrayPool`1:Rent(int):ref:this [4 IL=0023 TR=000024 060015C5] [below ALWAYS_INLINE size] Span`1:get_Length():int:this [0 IL=0028 TR=000027 06001DC4] [FAILED: target not direct] Stream:Read(ref,int,int):int:this [5 IL=0038 TR=000038 060015C5] [below ALWAYS_INLINE size] Span`1:get_Length():int:this [6 IL=0046 TR=000082 06000E0D] [below ALWAYS_INLINE size] SR:get_IO_StreamTooLong():ref [0 IL=0051 TR=000091 06001E68] [FAILED: unprofitable inline] IOException:.ctor(ref):this [7 IL=0060 TR=000055 060015BF] [aggressive inline attribute] Span`1:.ctor(ref,int,int):this [0 IL=0004 TR=000254 060001C9] [FAILED: does not return] ThrowHelper:ThrowArgumentNullException(int) [0 IL=0067 TR=000203 060001BA] [FAILED: does not return] ThrowHelper:ThrowArgumentOutOfRangeException() [8 IL=0074 TR=000209 06004587] [below ALWAYS_INLINE size] JitHelpers:GetRawSzArrayData(ref):byref [9 IL=0079 TR=000213 060000A5] [aggressive inline attribute] Unsafe:As(byref):byref [10 IL=0085 TR=000218 060000A6] [aggressive inline attribute] Unsafe:Add(byref,int):byref [11 IL=0069 TR=000068 060015CA] [below ALWAYS_INLINE size] Span`1:CopyTo(struct):this [0 IL=0002 TR=000280 060015CB] [FAILED: unprofitable inline] Span`1:TryCopyTo(struct):bool:this [0 IL=0009 TR=000292 060001BB] [FAILED: does not return] ThrowHelper:ThrowArgumentException_DestinationTooShort() [12 IL=0078 TR=000099 060018DA] [aggressive inline attribute] ArrayPool`1:get_Shared():ref [13 IL=0027 TR=000312 060018D7] [aggressive inline attribute] ArrayPools:get_BytePool():ref [0 IL=0085 TR=000104 060018DE] [FAILED: target not direct] ArrayPool`1:Return(ref,bool):this Budget: initialTime=339, finalTime=863, initialBudget=3390, currentBudget=3902 Budget: increased by 512 because of force inlines Budget: initialSize=2251, finalSize=2251 *************** After fgAddInternal() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) H0 finally { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB56 [04E..05B) *************** In fgDebugCheckBBlist *************** In fgRemoveEmptyTry() *************** Before fgRemoveEmptyTry() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) H0 finally { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB56 [04E..05B) EH#0 first try block BB02 not empty; skipping. *************** In fgRemoveEmptyFinally() *************** Before fgRemoveEmptyFinally() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) H0 finally { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB56 [04E..05B) EH#0 finally has multiple basic blocks; skipping. *************** In fgMergeFinallyChains() *************** Before fgMergeFinallyChains() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) H0 finally { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB56 [04E..05B) Examining callfinallys for EH#0. EH#0 has 1 callfinallys, 1 continuations EH#0 does not have any mergeable callfinallys Method had try-finallys, but did not have any mergeable finally chains. *************** In fgCloneFinally() *************** Before fgCloneFinally() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???)-> BB05 (callf ) i internal BB08 [0007] 0 1 [???..???)-> BB06 (ALWAYS) i internal KEEP BB05 [0004] 1 0 1 [04E..05B) H0 finally { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Finally at BB05..BB56 [04E..05B) EH#0 is a candidate for finally cloning: 4 blocks, 3 statements Chose path to clone: try block BB47 jumps to callfinally at BB07; the call returns to BB08 which jumps to BB06 Will update callfinally block BB07 to jump to the clone; clone will jump to BB06 fgFindInsertPoint(regionIndex=0, putInTryRegion=true, startBlk=BB01, endBlk=BB00, nearBlk=BB08, jumpBlk=BB00, runRarely=false) fgNewBBinRegion(jumpKind=5, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=false): inserting after BB08 New Basic Block BB58 [0043] created. New Basic Block BB59 [0044] created. New Basic Block BB60 [0045] created. New Basic Block BB61 [0046] created. Cloned finally blocks are: BB58 ... BB61 Removing statement [000352] in BB61 as useless: [000352] ------------ * STMT void (IL ???... ???) [000351] ------------ \--* RETFILT void fgRemoveBlock BB08 Removing unreachable BB08 All callfinallys retargeted; changing finally to fault. Done with EH#0 fgCloneFinally() cloned 1 finally handlers *************** After fgCloneFinally() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0.50 [000..000) T0 i internal BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0.50 [000..000) T0 i internal BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0.50 [042..043) T0 i BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???) i internal BB58 [0043] 2 1 [04E..05B) keep i label target cfb BB59 [0044] 1 1 [04E..04F) i BB60 [0045] 1 1 [04E..04F) i BB61 [0046] 1 1 [???..???)-> BB06 (always) keep internal label cfe BB05 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Fault at BB05..BB56 [04E..05B) *************** In fgDebugCheckBBlist *************** In fgMarkImplicitByRefs() *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 struct (16) ld-addr-op ; V02 loc0 ref class-hnd ; V03 loc1 int ; V04 loc2 struct (16) ld-addr-op ; V05 loc3 int ; V06 tmp0 ref class-hnd ; V07 tmp1 struct (16) ; V08 tmp2 ref class-hnd exact ; V09 tmp3 ref class-hnd ; V10 tmp4 ubyte ld-addr-op ; V11 tmp5 ref class-hnd exact ; V12 tmp6 struct ( 8) ; V13 tmp7 byref ; V14 tmp8 struct (16) ; V15 tmp9 ref class-hnd Promoting struct local V01 (Span`1): lvaGrabTemp returning 16 (V16 tmp10) (a long lifetime temp) called for field V01._pointer (fldOffset=0x0). Set preferred register for V16 to [rdx] New refCnts for V16: refCnt = 1, refCntWtd = 1 lvaGrabTemp returning 17 (V17 tmp11) (a long lifetime temp) called for field V01._length (fldOffset=0x8). Set preferred register for V17 to [rdx] New refCnts for V17: refCnt = 1, refCntWtd = 1 Promoting struct local V04 (Span`1): lvaGrabTemp returning 18 (V18 tmp12) (a long lifetime temp) called for field V04._pointer (fldOffset=0x0). lvaGrabTemp returning 19 (V19 tmp13) (a long lifetime temp) called for field V04._length (fldOffset=0x8). Promoting struct local V07 (Span`1): lvaGrabTemp returning 20 (V20 tmp14) (a long lifetime temp) called for field V07._pointer (fldOffset=0x0). lvaGrabTemp returning 21 (V21 tmp15) (a long lifetime temp) called for field V07._length (fldOffset=0x8). Promoting struct local V12 (ByReference`1): lvaGrabTemp returning 22 (V22 tmp16) (a long lifetime temp) called for field V12._value (fldOffset=0x0). Promoting struct local V14 (Span`1): lvaGrabTemp returning 23 (V23 tmp17) (a long lifetime temp) called for field V14._pointer (fldOffset=0x0). lvaGrabTemp returning 24 (V24 tmp18) (a long lifetime temp) called for field V14._length (fldOffset=0x8). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 struct (16) ld-addr-op ; V02 loc0 ref class-hnd ; V03 loc1 int ; V04 loc2 struct (16) ld-addr-op ; V05 loc3 int ; V06 tmp0 ref class-hnd ; V07 tmp1 struct (16) ; V08 tmp2 ref class-hnd exact ; V09 tmp3 ref class-hnd ; V10 tmp4 ubyte ld-addr-op ; V11 tmp5 ref class-hnd exact ; V12 tmp6 struct ( 8) ; V13 tmp7 byref ; V14 tmp8 struct (16) ; V15 tmp9 ref class-hnd ; V16 tmp10 byref V01._pointer(offs=0x00) P-INDEP ; V17 tmp11 int V01._length(offs=0x08) P-INDEP ; V18 tmp12 byref V04._pointer(offs=0x00) P-INDEP ; V19 tmp13 int V04._length(offs=0x08) P-INDEP ; V20 tmp14 byref V07._pointer(offs=0x00) P-INDEP ; V21 tmp15 int V07._length(offs=0x08) P-INDEP ; V22 tmp16 byref V12._value(offs=0x00) P-INDEP ; V23 tmp17 byref V14._pointer(offs=0x00) P-INDEP ; V24 tmp18 int V14._length(offs=0x08) P-INDEP *************** In fgMarkAddressExposedLocals() Incrementing ref count from 0 to 1 for V01 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: [000013] --C-G------- /--* CALLV ind ref ArrayPool`1.Rent [000011] ------------ this in rcx | +--* LCL_VAR ref V06 tmp0 [000145] ------------ arg1 | \--* LCL_VAR int V17 tmp11 [000016] -AC-G------- * ASG ref [000015] D------N---- \--* LCL_VAR ref V02 loc0 Incrementing ref count from 1 to 2 for V01 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: [000027] --C-G------- /--* CALLV ind int Stream.Read [000019] ------------ this in rcx | +--* LCL_VAR ref V00 this [000020] ------------ arg1 | +--* LCL_VAR ref V02 loc0 [000021] ------------ arg2 | +--* CNS_INT int 0 [000150] ------------ arg3 | \--* LCL_VAR int V17 tmp11 [000032] -AC-G------- * ASG int [000031] D------N---- \--* LCL_VAR int V03 loc1 Incrementing ref count from 2 to 3 for V01 in fgMorphStructField for promoted struct Replacing the field in promoted struct with a local var: [000043] --C--------- * JTRUE void [000041] --C--------- | /--* CAST long <- int [000155] ------------ | | \--* LCL_VAR int V17 tmp11 [000042] --C--------- \--* LE int [000035] ---------U-- \--* CAST long <- ulong <- uint [000034] ------------ \--* LCL_VAR int V03 loc1 Replacing the field in promoted struct with a local var: [000263] ------------ /--* LCL_VAR byref V13 tmp7 [000274] ------------ /--* ADD byref [000271] ------------ | | /--* CAST long <- int [000270] ------------ | | | \--* CNS_INT int 1 [000273] ------------ | \--* MUL long [000272] ------------ | \--* CAST long <- int [000269] ------------ | \--* CNS_INT int 0 [000230] -AC--------- * ASG byref [000229] D------N---- \--* LCL_VAR byref V22 tmp16 Replacing the field in promoted struct with a local var: [000231] ------------ /--* LCL_VAR struct(P) V12 tmp6 /--* byref V12._value (offs=0x00) -> V22 tmp16 [000236] -A------R--- * ASG struct (copy) [000235] ------------ \--* OBJ(8) struct [000234] ------------ \--* ADDR byref [000233] ------------ \--* LCL_VAR byref V20 tmp14 Replacing the field in promoted struct with a local var: [000048] ------------ /--* LCL_VAR int V03 loc1 [000241] -A---------- * ASG int [000240] D------N---- \--* LCL_VAR int V21 tmp15 Incrementing ref count from 3 to 4 for V01 in fgMorphStructField Local V18 should not be enregistered because: it is address exposed Local V19 should not be enregistered because: it is address exposed Local V04 should not be enregistered because: it is address exposed *************** In fgRetypeImplicitByRefArgs() lvaGrabTemp returning 25 (V25 tmp19) (a long lifetime temp) called for Promoted implicit byref. New Basic Block BB62 [0047] created. New scratch BB62 Changing the lvType for struct parameter V01 to TYP_BYREF. *************** In fgMorphBlocks() Morphing BB62 of 'Stream:Read(struct):int:this' fgMorphTree BB62, stmt 1 (before) [000355] ------------ /--* BLK(16) struct [000354] ------------ | \--* LCL_VAR byref (P?!) V01 arg1 [000356] -A---------- * ASG struct (copy) [000353] D------N---- \--* LCL_VAR struct(P) V25 tmp19 \--* byref V25._pointer (offs=0x00) -> V16 tmp10 \--* int V25._length (offs=0x08) -> V17 tmp11 fgMorphCopyBlock:block assignment to morph: [000355] x----+------ /--* BLK(16) struct [000354] -----+------ | \--* LCL_VAR byref (P?!) V01 arg1 [000356] -A---------- * ASG struct (copy) [000353] D----+-N---- \--* LCL_VAR struct(P) V25 tmp19 \--* byref V25._pointer (offs=0x00) -> V16 tmp10 \--* int V25._length (offs=0x08) -> V17 tmp11 (destDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000370] -A---------- * ASG int In BB62 New Local Subrange Assertion: V17 in [-2147483648..2147483647] index=#01, mask=0000000000000001 fgMorphCopyBlock (after): [000369] x----------- /--* IND int [000367] ------------ | | /--* CNS_INT long 8 Fseq[_length] [000368] ------------ | \--* ADD byref [000366] ------------ | \--* LCL_VAR byref (P?!) V01 arg1 [000370] -A---------- /--* ASG int [000365] D------N---- | \--* LCL_VAR int V17 tmp11 [000371] -A---+------ * COMMA void [000363] x----------- | /--* IND byref [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000362] ------------ | | \--* ADD byref [000360] ------------ | | \--* LCL_VAR byref (P?!) V01 arg1 [000364] -A---------- \--* ASG byref [000359] D------N---- \--* LCL_VAR byref V16 tmp10 fgMorphTree BB62, stmt 1 (after) [000369] x----------- /--* IND int [000367] ------------ | | /--* CNS_INT long 8 Fseq[_length] [000368] ------------ | \--* ADD byref [000366] ------------ | \--* LCL_VAR byref (P?!) V01 arg1 [000370] -A---------- /--* ASG int [000365] D------N---- | \--* LCL_VAR int V17 tmp11 [000371] -A---+------ * COMMA void [000363] x----------- | /--* IND byref [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000362] ------------ | | \--* ADD byref [000360] ------------ | | \--* LCL_VAR byref (P?!) V01 arg1 [000364] -A---------- \--* ASG byref [000359] D------N---- \--* LCL_VAR byref V16 tmp10 Morphing BB01 of 'Stream:Read(struct):int:this' Morphing BB14 of 'Stream:Read(struct):int:this' Morphing BB15 of 'Stream:Read(struct):int:this' fgMorphTree BB15, stmt 2 (before) [000140] --CXG------- /--* IND ref [000138] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG------- | \--* ADD byref [000137] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----------- arg0 | +--* IND long [000132] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] ------------ arg1 | \--* CNS_INT int 327 [000127] -AC--------- * ASG ref [000126] D------N---- \--* LCL_VAR ref V09 tmp3 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000133] #----+------ * IND long [000132] -----+------ \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid Replaced with placeholder node: [000372] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000134] -----+------ * CNS_INT int 327 Replaced with placeholder node: [000374] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 133.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 134.CNS_INT, rdx, regs=1, align=1, lateArgInx=1, processed] fgMorphTree BB15, stmt 2 (after) [000140] --CXG+------ /--* IND ref [000138] -----+------ | | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG+------ | \--* ADD byref [000137] H-CXG+------ | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----+------ arg0 in rcx | +--* IND long [000132] -----+------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] -----+------ arg1 in rdx | \--* CNS_INT int 327 [000127] -ACXG+------ * ASG ref [000126] D----+-N---- \--* LCL_VAR ref V09 tmp3 Morphing BB16 of 'Stream:Read(struct):int:this' fgMorphTree BB16, stmt 3 (before) [000129] ------------ /--* LCL_VAR ref V09 tmp3 [000009] -AC--------- * ASG ref [000008] D------N---- \--* LCL_VAR ref V06 tmp0 GenTreeNode creates assertion: [000009] -A---------- * ASG ref In BB16 New Local Copy Assertion: V06 == V09 index=#01, mask=0000000000000001 fgMorphTree BB16, stmt 4 (before) [000013] --C-G------- /--* CALLV ind ref ArrayPool`1.Rent [000011] ------------ this in rcx | +--* LCL_VAR ref V06 tmp0 [000145] ------------ arg1 | \--* LCL_VAR int V17 tmp11 [000016] -AC-G------- * ASG ref [000015] D------N---- \--* LCL_VAR ref V02 loc0 Assertion prop in BB16: Copy Assertion: V06 == V09 index=#01, mask=0000000000000001 [000011] ------------ * LCL_VAR ref V09 tmp3 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000011] -----+------ * LCL_VAR ref V09 tmp3 Replaced with placeholder node: [000376] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000145] -----+------ * LCL_VAR int V17 tmp11 Replaced with placeholder node: [000378] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 11.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 145.LCL_VAR, rdx, regs=1, align=1, lateArgInx=1, processed] GenTreeNode creates assertion: [000013] --CXG------- * CALLV ind ref ArrayPool`1.Rent In BB16 New Local Constant Assertion: V09 != null index=#02, mask=0000000000000002 fgMorphTree BB16, stmt 4 (after) [000013] --CXG+------ /--* CALLV ind ref ArrayPool`1.Rent [000011] -----+------ this in rcx | +--* LCL_VAR ref V09 tmp3 [000145] -----+------ arg1 in rdx | \--* LCL_VAR int V17 tmp11 [000016] -ACXG+------ * ASG ref [000015] D----+-N---- \--* LCL_VAR ref V02 loc0 Morphing BB02 of 'Stream:Read(struct):int:this' fgMorphTree BB02, stmt 5 (before) [000027] --C-G------- /--* CALLV ind int Stream.Read [000019] ------------ this in rcx | +--* LCL_VAR ref V00 this [000020] ------------ arg1 | +--* LCL_VAR ref V02 loc0 [000021] ------------ arg2 | +--* CNS_INT int 0 [000150] ------------ arg3 | \--* LCL_VAR int V17 tmp11 [000032] -AC-G------- * ASG int [000031] D------N---- \--* LCL_VAR int V03 loc1 argSlots=4, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000019] -----+------ * LCL_VAR ref V00 this Replaced with placeholder node: [000380] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000020] -----+------ * LCL_VAR ref V02 loc0 Replaced with placeholder node: [000382] ----------L- * ARGPLACE ref Deferred argument ('r9'): [000150] -----+------ * LCL_VAR int V17 tmp11 Replaced with placeholder node: [000384] ----------L- * ARGPLACE int Deferred argument ('r8'): [000021] -----+------ * CNS_INT int 0 Replaced with placeholder node: [000386] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r9 r8 fgArgTabEntry[arg 0 19.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 20.LCL_VAR, rdx, regs=1, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 3 150.LCL_VAR, r9, regs=1, align=1, lateArgInx=2, processed] fgArgTabEntry[arg 2 21.CNS_INT, r8, regs=1, align=1, lateArgInx=3, processed] GenTreeNode creates assertion: [000027] --CXG------- * CALLV ind int Stream.Read In BB02 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB02, stmt 5 (after) [000027] --CXG+------ /--* CALLV ind int Stream.Read [000019] -----+------ this in rcx | +--* LCL_VAR ref V00 this [000020] -----+------ arg1 in rdx | +--* LCL_VAR ref V02 loc0 [000150] -----+------ arg3 in r9 | +--* LCL_VAR int V17 tmp11 [000021] -----+------ arg2 in r8 | \--* CNS_INT int 0 [000032] -ACXG+------ * ASG int [000031] D----+-N---- \--* LCL_VAR int V03 loc1 fgMorphTree BB02, stmt 6 (before) [000043] --C--------- * JTRUE void [000041] --C--------- | /--* CAST long <- int [000155] ------------ | | \--* LCL_VAR int V17 tmp11 [000042] --C--------- \--* LE int [000035] ---------U-- \--* CAST long <- ulong <- uint [000034] ------------ \--* LCL_VAR int V03 loc1 Morphing BB03 of 'Stream:Read(struct):int:this' fgMorphTree BB03, stmt 7 (before) [000086] ------------ /--* ALLOCOBJ ref [000085] ------------ | \--* CNS_INT(h) long 0x17dd3b22ac8 method [000088] -A---------- * ASG ref [000087] D------N---- \--* LCL_VAR ref V08 tmp2 fgMorphTree BB03, stmt 8 (before) [000091] --C-G------- * CALL void IOException..ctor [000090] ------------ this in rcx +--* LCL_VAR ref V08 tmp2 [000160] --C-G------- arg1 \--* CALL ref SR.GetResourceString [000158] ------------ arg0 +--* CNS_STR ref [000159] ------------ arg1 \--* CNS_INT ref null argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000388] -----+------ * CNS_INT int 0xE904 Replaced with placeholder node: [000391] ----------L- * ARGPLACE int Shuffled argument table: rcx fgArgTabEntry[arg 0 388.CNS_INT, rcx, regs=1, align=1, lateArgInx=0, processed] argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000390] --CXG+------ * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx \--* CNS_INT int 0xE904 lvaGrabTemp returning 26 (V26 tmp20) called for argument with side effect. Evaluate to a temp: [000390] --CXG+------ /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- * ASG ref [000393] D------N---- \--* LCL_VAR ref V26 tmp20 Deferred argument ('rdx'): [000159] -----+------ * CNS_INT ref null Replaced with placeholder node: [000397] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 395.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V26, isTmp, processed] fgArgTabEntry[arg 1 159.CNS_INT, rdx, regs=1, align=1, lateArgInx=1, processed] argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000160] --CXG+------ * CALL ref SR.GetResourceString [000390] --CXG+------ | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- arg0 SETUP +--* ASG ref [000393] D------N---- | \--* LCL_VAR ref V26 tmp20 [000395] ------------ arg0 in rcx +--* LCL_VAR ref V26 tmp20 [000159] -----+------ arg1 in rdx \--* CNS_INT ref null lvaGrabTemp returning 27 (V27 tmp21) called for argument with side effect. Evaluate to a temp: [000160] --CXG+------ /--* CALL ref SR.GetResourceString [000390] --CXG+------ | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | | | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- arg0 SETUP | +--* ASG ref [000393] D------N---- | | \--* LCL_VAR ref V26 tmp20 [000395] ------------ arg0 in rcx | +--* LCL_VAR ref V26 tmp20 [000159] -----+------ arg1 in rdx | \--* CNS_INT ref null [000400] -ACXG-----L- * ASG ref [000399] D------N---- \--* LCL_VAR ref V27 tmp21 Deferred argument ('rcx'): [000090] -----+------ * LCL_VAR ref V08 tmp2 Replaced with placeholder node: [000403] ----------L- * ARGPLACE ref Shuffled argument table: rdx rcx fgArgTabEntry[arg 1 401.LCL_VAR, rdx, regs=1, align=1, lateArgInx=0, tmpNum=V27, isTmp, processed] fgArgTabEntry[arg 0 90.LCL_VAR, rcx, regs=1, align=1, lateArgInx=1, processed] fgMorphTree BB03, stmt 8 (after) [000091] --CXG+------ * CALL void IOException..ctor [000160] --CXG+------ | /--* CALL ref SR.GetResourceString [000390] --CXG+------ | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- arg0 SETUP | | +--* ASG ref [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 [000159] -----+------ arg1 in rdx | | \--* CNS_INT ref null [000400] -ACXG-----L- arg1 SETUP +--* ASG ref [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 [000090] -----+------ this in rcx \--* LCL_VAR ref V08 tmp2 fgMorphTree BB03, stmt 9 (before) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW [000094] ------------ arg0 \--* LCL_VAR ref V08 tmp2 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000094] -----+------ * LCL_VAR ref V08 tmp2 Replaced with placeholder node: [000405] ----------L- * ARGPLACE ref Shuffled argument table: rcx fgArgTabEntry[arg 0 94.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB03, stmt 9 (after) [000096] --CXG+------ * CALL help void HELPER.CORINFO_HELP_THROW [000094] -----+------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 Morphing BB04 of 'Stream:Read(struct):int:this' fgMorphTree BB04, stmt 10 (before) [000050] ------------ /--* CNS_INT int 0 [000051] IA------R--- * ASG struct (init) [000049] D------N---- \--* LCL_VAR struct(P) V07 tmp1 \--* byref V07._pointer (offs=0x00) -> V20 tmp14 \--* int V07._length (offs=0x08) -> V21 tmp15 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [000409] -A---------- * ASG byref In BB04 New Local Constant Assertion: V20 == 0 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000412] -A---------- * ASG int In BB04 New Local Constant Assertion: V21 == 0 index=#02, mask=0000000000000002 fgMorphInitBlock (after): [000411] ------------ /--* CNS_INT int 0 [000412] -A---------- /--* ASG int [000410] D------N---- | \--* LCL_VAR int V21 tmp15 [000413] -A---+------ * COMMA void [000408] ------------ | /--* CNS_INT byref 0 [000409] -A---------- \--* ASG byref [000407] D------N---- \--* LCL_VAR byref V20 tmp14 fgMorphTree BB04, stmt 10 (after) [000411] ------------ /--* CNS_INT int 0 [000412] -A---------- /--* ASG int [000410] D------N---- | \--* LCL_VAR int V21 tmp15 [000413] -A---+------ * COMMA void [000408] ------------ | /--* CNS_INT byref 0 [000409] -A---------- \--* ASG byref [000407] D------N---- \--* LCL_VAR byref V20 tmp14 Morphing BB31 of 'Stream:Read(struct):int:this' fgMorphTree BB31, stmt 11 (before) [000167] ------------ * JTRUE void [000165] ------------ | /--* CNS_INT ref null [000166] ------------ \--* NE int [000046] ------------ \--* LCL_VAR ref V02 loc0 Morphing BB32 of 'Stream:Read(struct):int:this' fgMorphTree BB32, stmt 12 (before) [000254] --C-G------- * CALL void ThrowHelper.ThrowArgumentNullException [000253] ------------ arg0 \--* CNS_INT int 2 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000253] -----+------ * CNS_INT int 2 Replaced with placeholder node: [000414] ----------L- * ARGPLACE int Shuffled argument table: rcx fgArgTabEntry[arg 0 253.CNS_INT, rcx, regs=1, align=1, lateArgInx=0, processed] fgMorphTree BB32, stmt 12 (after) [000254] --CXG+------ * CALL void ThrowHelper.ThrowArgumentNullException [000253] -----+------ arg0 in rcx \--* CNS_INT int 2 Morphing BB33 of 'Stream:Read(struct):int:this' fgMorphTree BB33, stmt 13 (before) [000172] ------------ /--* CNS_INT int 0 [000174] IA------R--- * ASG struct (init) [000173] -------N---- \--* BLK(1) struct [000171] L----------- \--* ADDR byref [000170] ------------ \--* LCL_VAR int V10 tmp4 fgMorphInitBlock:fgMorphOneAsgBlock (after): [000172] -----+------ /--* CNS_INT int 0 [000174] -A---------- * ASG ubyte [000170] D----+-N---- \--* LCL_VAR int V10 tmp4 using oneAsgTree. GenTreeNode creates assertion: [000174] -A---------- * ASG ubyte In BB33 New Local Constant Assertion: V10 == 0 index=#01, mask=0000000000000001 fgMorphTree BB33, stmt 13 (after) [000172] -----+------ /--* CNS_INT int 0 [000174] -A---+------ * ASG ubyte [000170] D----+-N---- \--* LCL_VAR int V10 tmp4 fgMorphTree BB33, stmt 14 (before) [000180] ------------ * NOP void fgMorphTree BB33, stmt 15 (before) [000187] ------------ * NOP void Morphing BB34 of 'Stream:Read(struct):int:this' fgMorphTree BB34, stmt 16 (before) [000200] ---X-------- * JTRUE void [000198] ---X-------- | /--* CAST int <- int [000197] ---X-------- | | \--* ARR_LENGTH int [000196] ------------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-----U-- \--* GT int [000195] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000197] ---X-------- * ARR_LENGTH int In BB34 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree BB34, stmt 16 (after) [000200] ---X-+------ * JTRUE void [000197] ---X-+------ | /--* ARR_LENGTH int [000196] -----+------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-+-N-U-- \--* GT int [000195] -----+------ \--* CNS_INT int 0 Morphing BB35 of 'Stream:Read(struct):int:this' fgMorphTree BB35, stmt 17 (before) [000250] ---X-------- * JTRUE void [000247] ---X-------- | /--* CAST int <- int [000246] ---X-------- | | \--* ARR_LENGTH int [000245] ------------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-----U-- \--* LE int [000244] ------------ \--* LCL_VAR int V03 loc1 GenTreeNode creates assertion: [000246] ---X-------- * ARR_LENGTH int In BB35 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree BB35, stmt 17 (after) [000250] ---X-+------ * JTRUE void [000246] ---X-+------ | /--* ARR_LENGTH int [000245] -----+------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-+-N-U-- \--* LE int [000244] -----+------ \--* LCL_VAR int V03 loc1 Morphing BB36 of 'Stream:Read(struct):int:this' fgMorphTree BB36, stmt 18 (before) [000203] --C-G------- * CALL void ThrowHelper.ThrowArgumentOutOfRangeException argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Morphing BB37 of 'Stream:Read(struct):int:this' fgMorphTree BB37, stmt 19 (before) [000260] ---XG------- /--* ADDR byref [000259] ---XG------- | \--* FIELD ubyte m_arrayData [000208] ------------ | \--* LCL_VAR ref V02 loc0 [000265] -A-XG------- * ASG byref [000264] D------N---- \--* LCL_VAR byref V13 tmp7 Before explicit null check morphing: [000259] ---XG--N---- * FIELD ubyte m_arrayData [000208] ------------ \--* LCL_VAR ref V02 loc0 After adding explicit null check: [000259] ---XG--N---- * IND ubyte [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] [000420] ------------ | /--* ADD byref [000418] ------------ | | \--* LCL_VAR ref V02 loc0 [000421] ---X-------- \--* COMMA byref [000417] ---X---N---- \--* NULLCHECK byte [000416] ------------ \--* LCL_VAR ref V02 loc0 GenTreeNode creates assertion: [000417] ---X---N---- * NULLCHECK byte In BB37 New Local Constant Assertion: V02 != null index=#01, mask=0000000000000001 fgMorphTree BB37, stmt 19 (after) [000419] -----+------ /--* CNS_INT long 16 field offset Fseq[m_arrayData] [000420] -----+------ /--* ADD byref [000418] -----+------ | \--* LCL_VAR ref V02 loc0 [000421] ---XG+-N---- /--* COMMA byref [000417] ---X-+-N---- | \--* NULLCHECK byte [000416] -----+------ | \--* LCL_VAR ref V02 loc0 [000265] -A-XG+------ * ASG byref [000264] D----+-N---- \--* LCL_VAR byref V13 tmp7 fgMorphTree BB37, stmt 20 (before) [000224] ------------ /--* CNS_INT int 0 [000225] IA------R--- * ASG struct (init) [000223] D------N---- \--* LCL_VAR struct(P) V12 tmp6 \--* byref V12._value (offs=0x00) -> V22 tmp16 fgMorphInitBlock: (destDoFldAsg=true) using field by field initialization. GenTreeNode creates assertion: [000425] -A---------- * ASG byref In BB37 New Local Constant Assertion: V22 == 0 index=#02, mask=0000000000000002 fgMorphInitBlock (after): [000424] ------------ /--* CNS_INT byref 0 [000425] -A---+------ * ASG byref [000423] D------N---- \--* LCL_VAR byref V22 tmp16 The assignment [000425] using V22 removes: Constant Assertion: V22 == 0 GenTreeNode creates assertion: [000425] -A---+------ * ASG byref In BB37 New Local Constant Assertion: V22 == 0 index=#02, mask=0000000000000002 fgMorphTree BB37, stmt 20 (after) [000424] ------------ /--* CNS_INT byref 0 [000425] -A---+------ * ASG byref [000423] D------N---- \--* LCL_VAR byref V22 tmp16 fgMorphTree BB37, stmt 21 (before) [000263] ------------ /--* LCL_VAR byref V13 tmp7 [000274] ------------ /--* ADD byref [000271] ------------ | | /--* CAST long <- int [000270] ------------ | | | \--* CNS_INT int 1 [000273] ------------ | \--* MUL long [000272] ------------ | \--* CAST long <- int [000269] ------------ | \--* CNS_INT int 0 [000230] -AC--------- * ASG byref [000229] D------N---- \--* LCL_VAR byref V22 tmp16 Folding long operator with constant nodes into a constant: [000272] ------------ * CAST long <- int [000269] -----+------ \--* CNS_INT int 0 Bashed to long constant: [000272] ------------ * CNS_INT long 0 Folding long operator with constant nodes into a constant: [000271] ------------ * CAST long <- int [000270] -----+------ \--* CNS_INT int 1 Bashed to long constant: [000271] ------------ * CNS_INT long 1 Folding long operator with constant nodes into a constant: [000271] -----+------ /--* CNS_INT long 1 [000273] ------------ * MUL long [000272] -----+------ \--* CNS_INT long 0 Bashed to long constant: [000273] ------------ * CNS_INT long 0 The assignment [000230] using V22 removes: Constant Assertion: V22 == 0 GenTreeNode creates assertion: [000230] -A---------- * ASG byref In BB37 New Local Copy Assertion: V22 == V13 index=#02, mask=0000000000000002 fgMorphTree BB37, stmt 21 (after) [000263] -----+------ /--* LCL_VAR byref V13 tmp7 [000230] -A---+------ * ASG byref [000229] D----+-N---- \--* LCL_VAR byref V22 tmp16 fgMorphTree BB37, stmt 22 (before) [000231] ------------ /--* LCL_VAR struct(P) V12 tmp6 /--* byref V12._value (offs=0x00) -> V22 tmp16 [000236] -A------R--- * ASG struct (copy) [000235] ------------ \--* OBJ(8) struct [000234] ------------ \--* ADDR byref [000233] ------------ \--* LCL_VAR byref V20 tmp14 fgMorphCopyBlock:block assignment to morph: [000231] -----+------ /--* LCL_VAR struct(P) V12 tmp6 /--* byref V12._value (offs=0x00) -> V22 tmp16 [000236] -A------R--- * ASG struct (copy) [000235] x----+------ \--* OBJ(8) struct [000234] -----+------ \--* ADDR byref [000233] D----+-N---- \--* LCL_VAR byref V20 tmp14 (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000428] -A---------- * ASG byref In BB37 New Local Copy Assertion: V20 == V22 index=#03, mask=0000000000000004 fgMorphCopyBlock (after): [000427] -------N---- /--* LCL_VAR byref V22 tmp16 [000428] -A---+------ * ASG byref [000426] D------N---- \--* LCL_VAR byref V20 tmp14 The assignment [000428] using V20 removes: Copy Assertion: V20 == V22 GenTreeNode creates assertion: [000428] -A---+------ * ASG byref In BB37 New Local Copy Assertion: V20 == V22 index=#03, mask=0000000000000004 fgMorphTree BB37, stmt 22 (after) [000427] -------N---- /--* LCL_VAR byref V22 tmp16 [000428] -A---+------ * ASG byref [000426] D------N---- \--* LCL_VAR byref V20 tmp14 fgMorphTree BB37, stmt 23 (before) [000048] ------------ /--* LCL_VAR int V03 loc1 [000241] -A---------- * ASG int [000240] D------N---- \--* LCL_VAR int V21 tmp15 GenTreeNode creates assertion: [000241] -A---------- * ASG int In BB37 New Local Copy Assertion: V21 == V03 index=#04, mask=0000000000000008 Morphing BB38 of 'Stream:Read(struct):int:this' fgMorphTree BB38, stmt 24 (before) [000060] ------------ /--* LCL_VAR struct(P) V07 tmp1 /--* byref V07._pointer (offs=0x00) -> V20 tmp14 /--* int V07._length (offs=0x08) -> V21 tmp15 [000063] -A------R--- * ASG struct (copy) [000061] D----------- \--* LCL_VAR struct(AX)(P) V04 loc2 \--* byref V04._pointer (offs=0x00) -> V18 tmp12 \--* int V04._length (offs=0x08) -> V19 tmp13 fgMorphCopyBlock:block assignment to morph: [000060] -----+------ /--* LCL_VAR struct(P) V07 tmp1 /--* byref V07._pointer (offs=0x00) -> V20 tmp14 /--* int V07._length (offs=0x08) -> V21 tmp15 [000063] -A--G---R--- * ASG struct (copy) [000061] D---G+-N---- \--* LCL_VAR struct(AX)(P) V04 loc2 \--* byref V04._pointer (offs=0x00) -> V18 tmp12 \--* int V04._length (offs=0x08) -> V19 tmp13 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. fgMorphCopyBlock (after): [000433] -------N---- /--* LCL_VAR int V21 tmp15 [000434] -A--G------- /--* ASG int [000432] D---G--N---- | \--* LCL_VAR int (AX) V19 tmp13 [000435] -A--G+------ * COMMA void [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 [000431] -A--G------- \--* ASG byref [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 fgMorphTree BB38, stmt 24 (after) [000433] -------N---- /--* LCL_VAR int V21 tmp15 [000434] -A--G------- /--* ASG int [000432] D---G--N---- | \--* LCL_VAR int (AX) V19 tmp13 [000435] -A--G+------ * COMMA void [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 [000431] -A--G------- \--* ASG byref [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 fgMorphTree BB38, stmt 25 (before) [000070] x----------- /--* OBJ(16) struct [000069] L----------- | \--* ADDR byref [000067] ------------ | \--* LCL_VAR struct(P?!) V01 arg1 [000296] -A------R--- * ASG struct (copy) [000294] D----------- \--* LCL_VAR struct(P) V14 tmp8 \--* byref V14._pointer (offs=0x00) -> V23 tmp17 \--* int V14._length (offs=0x08) -> V24 tmp18 fgMorphCopyBlock:block assignment to morph: [000070] x----+------ /--* OBJ(16) struct [000069] L----+------ | \--* ADDR byref [000067] -----+-N---- | \--* LCL_VAR struct(P) V25 tmp19 | \--* byref V25._pointer (offs=0x00) -> V16 tmp10 | \--* int V25._length (offs=0x08) -> V17 tmp11 [000296] -A------R--- * ASG struct (copy) [000294] D----+-N---- \--* LCL_VAR struct(P) V14 tmp8 \--* byref V14._pointer (offs=0x00) -> V23 tmp17 \--* int V14._length (offs=0x08) -> V24 tmp18 (destDoFldAsg=true) (srcDoFldAsg=true) using field by field assignments. GenTreeNode creates assertion: [000438] -A---------- * ASG byref In BB38 New Local Copy Assertion: V23 == V16 index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000441] -A---------- * ASG int In BB38 New Local Copy Assertion: V24 == V17 index=#02, mask=0000000000000002 fgMorphCopyBlock (after): [000440] -------N---- /--* LCL_VAR int V17 tmp11 [000441] -A---------- /--* ASG int [000439] D------N---- | \--* LCL_VAR int V24 tmp18 [000442] -A---+------ * COMMA void [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 [000438] -A---------- \--* ASG byref [000436] D------N---- \--* LCL_VAR byref V23 tmp17 fgMorphTree BB38, stmt 25 (after) [000440] -------N---- /--* LCL_VAR int V17 tmp11 [000441] -A---------- /--* ASG int [000439] D------N---- | \--* LCL_VAR int V24 tmp18 [000442] -A---+------ * COMMA void [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 [000438] -A---------- \--* ASG byref [000436] D------N---- \--* LCL_VAR byref V23 tmp17 Morphing BB44 of 'Stream:Read(struct):int:this' fgMorphTree BB44, stmt 26 (before) [000288] --C--------- * JTRUE void [000286] ------------ | /--* CNS_INT int 0 [000287] --C--------- \--* NE int [000280] --C-G------- \--* CALL int Span`1.TryCopyTo [000277] L----------- this in rcx +--* ADDR byref [000278] ------------ | \--* LCL_VAR struct(AX)(P) V04 loc2 | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | \--* int V04._length (offs=0x08) -> V19 tmp13 [000282] x----------- arg1 \--* OBJ(16) struct [000281] L----------- \--* ADDR byref [000279] ------------ \--* LCL_VAR struct(P) V14 tmp8 \--* byref V14._pointer (offs=0x00) -> V23 tmp17 \--* int V14._length (offs=0x08) -> V24 tmp18 lvaGrabTemp returning 28 (V28 tmp22) called for by-value struct argument. New refCnts for V28: refCnt = 1, refCntWtd = 2 fgMorphCopyBlock:block assignment to morph: [000279] -----+-N---- /--* LCL_VAR struct(P) V14 tmp8 /--* byref V14._pointer (offs=0x00) -> V23 tmp17 /--* int V14._length (offs=0x08) -> V24 tmp18 [000444] -A------R--- * ASG struct (copy) [000443] D------N---- \--* LCL_VAR struct V28 tmp22 (srcDoFldAsg=true) using field by field assignments. Local V28 should not be enregistered because: written in a block op lvaGrabTemp returning 29 (V29 tmp23) called for BlockOp address local. Local V28 should not be enregistered because: it is address exposed fgMorphCopyBlock (after): [000461] -------N---- /--* LCL_VAR int V24 tmp18 [000462] -A---------- /--* ASG int indir assign of V28:ud:0->0 [000460] *------N---- | \--* IND int [000458] ------------ | | /--* CNS_INT long 8 Fseq[_length] [000459] ------------ | \--* ADD byref [000457] ------------ | \--* LCL_VAR byref V29 tmp23 [000463] -A---+------ * COMMA void [000454] -------N---- | /--* LCL_VAR byref V23 tmp17 [000455] -A---------- | /--* ASG byref indir assign of V28:ud:0->0 [000453] *------N---- | | \--* IND byref [000451] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000452] ------------ | | \--* ADD byref [000450] ------------ | | \--* LCL_VAR byref V29 tmp23 [000456] -A---------- \--* COMMA void [000446] L----------- | /--* ADDR byref [000447] -------N---- | | \--* LCL_VAR struct(AX) V28 tmp22 [000449] -A---------- \--* ASG byref [000448] D------N---- \--* LCL_VAR byref V29 tmp23 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000277] L----+------ * ADDR byref [000278] ----G+-N---- \--* LCL_VAR struct(AX)(P) V04 loc2 \--* byref V04._pointer (offs=0x00) -> V18 tmp12 \--* int V04._length (offs=0x08) -> V19 tmp13 lvaGrabTemp returning 30 (V30 tmp24) called for argument with side effect. Evaluate to a temp: [000277] L----+------ /--* ADDR byref [000278] ----G+-N---- | \--* LCL_VAR struct(AX)(P) V04 loc2 | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | \--* int V04._length (offs=0x08) -> V19 tmp13 [000465] -A--------L- * ASG byref [000464] D------N---- \--* LCL_VAR byref V30 tmp24 Local V28 should not be enregistered because: it is address exposed Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 466.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, tmpNum=V30, isTmp, processed] fgArgTabEntry[arg 1 469.ADDR, rdx, regs=1, align=1, lateArgInx=1, tmpNum=V28, isTmp, processed] fgMorphTree BB44, stmt 26 (after) [000288] -ACXG+------ * JTRUE void [000286] -----+------ | /--* CNS_INT int 0 [000287] JACXG+-N---- \--* NE int [000280] -ACXG+------ \--* CALL int Span`1.TryCopyTo [000277] L----+------ | /--* ADDR byref [000278] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 [000465] -A--------L- this SETUP +--* ASG byref [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 [000461] -------N---- | /--* LCL_VAR int V24 tmp18 [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 [000460] *------N---- | | \--* IND int [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000459] ------------ | | \--* ADD byref [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 [000463] -A---+----L- arg1 SETUP +--* COMMA void [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 [000453] *------N---- | | | \--* IND byref [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] [000452] ------------ | | | \--* ADD byref [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 [000456] -A---------- | \--* COMMA void [000446] L----------- | | /--* ADDR byref [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 [000449] -A---------- | \--* ASG byref [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 [000469] L----------- arg1 in rdx \--* ADDR byref [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 Morphing BB45 of 'Stream:Read(struct):int:this' fgMorphTree BB45, stmt 27 (before) [000292] --C-G------- * CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort argSlots=0, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Morphing BB46 of 'Stream:Read(struct):int:this' Morphing BB47 of 'Stream:Read(struct):int:this' fgMorphTree BB47, stmt 28 (before) [000073] ------------ /--* LCL_VAR int V03 loc1 [000075] -A---------- * ASG int [000074] D------N---- \--* LCL_VAR int V05 loc3 GenTreeNode creates assertion: [000075] -A---------- * ASG int In BB47 New Local Copy Assertion: V05 == V03 index=#01, mask=0000000000000001 Morphing BB07 of 'Stream:Read(struct):int:this' Morphing BB58 of 'Stream:Read(struct):int:this' Morphing BB59 of 'Stream:Read(struct):int:this' Morphing BB60 of 'Stream:Read(struct):int:this' fgMorphTree BB60, stmt 29 (before) [000334] --CXG------- /--* IND ref [000342] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] [000335] --CXG------- | \--* ADD byref [000336] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000338] #----------- arg0 | +--* IND long [000339] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000341] ------------ arg1 | \--* CNS_INT int 327 [000332] -AC-G------- * ASG ref [000333] D------N---- \--* LCL_VAR ref V15 tmp9 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000338] #----+------ * IND long [000339] -----+------ \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid Replaced with placeholder node: [000471] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000341] -----+------ * CNS_INT int 327 Replaced with placeholder node: [000473] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 338.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 341.CNS_INT, rdx, regs=1, align=1, lateArgInx=1, processed] fgMorphTree BB60, stmt 29 (after) [000334] --CXG+------ /--* IND ref [000342] -----+------ | | /--* CNS_INT int 888 Fseq[k__BackingField] [000335] --CXG+------ | \--* ADD byref [000336] H-CXG+------ | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000338] #----+------ arg0 in rcx | +--* IND long [000339] -----+------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000341] -----+------ arg1 in rdx | \--* CNS_INT int 327 [000332] -ACXG+------ * ASG ref [000333] D----+-N---- \--* LCL_VAR ref V15 tmp9 Morphing BB61 of 'Stream:Read(struct):int:this' fgMorphTree BB61, stmt 30 (before) [000344] --C-G------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 [000347] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000349] ------------ arg2 \--* CNS_INT int 0 argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000345] -----+------ * LCL_VAR ref V15 tmp9 Replaced with placeholder node: [000475] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000347] -----+------ * LCL_VAR ref V02 loc0 Replaced with placeholder node: [000477] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000349] -----+------ * CNS_INT int 0 Replaced with placeholder node: [000479] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r8 fgArgTabEntry[arg 0 345.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 347.LCL_VAR, rdx, regs=1, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 349.CNS_INT, r8, regs=1, align=1, lateArgInx=2, processed] GenTreeNode creates assertion: [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return In BB61 New Local Constant Assertion: V15 != null index=#01, mask=0000000000000001 fgMorphTree BB61, stmt 30 (after) [000344] --CXG+------ * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000345] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000347] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000349] -----+------ arg2 in r8 \--* CNS_INT int 0 Morphing BB05 of 'Stream:Read(struct):int:this' Morphing BB54 of 'Stream:Read(struct):int:this' Morphing BB55 of 'Stream:Read(struct):int:this' fgMorphTree BB55, stmt 31 (before) [000330] --CXG------- /--* IND ref [000328] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG------- | \--* ADD byref [000327] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----------- arg0 | +--* IND long [000322] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] ------------ arg1 | \--* CNS_INT int 327 [000317] -AC--------- * ASG ref [000316] D------N---- \--* LCL_VAR ref V15 tmp9 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000323] #----+------ * IND long [000322] -----+------ \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid Replaced with placeholder node: [000481] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000324] -----+------ * CNS_INT int 327 Replaced with placeholder node: [000483] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx fgArgTabEntry[arg 0 323.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 324.CNS_INT, rdx, regs=1, align=1, lateArgInx=1, processed] fgMorphTree BB55, stmt 31 (after) [000330] --CXG+------ /--* IND ref [000328] -----+------ | | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG+------ | \--* ADD byref [000327] H-CXG+------ | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----+------ arg0 in rcx | +--* IND long [000322] -----+------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] -----+------ arg1 in rdx | \--* CNS_INT int 327 [000317] -ACXG+------ * ASG ref [000316] D----+-N---- \--* LCL_VAR ref V15 tmp9 Morphing BB56 of 'Stream:Read(struct):int:this' fgMorphTree BB56, stmt 32 (before) [000104] --C-G------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] ------------ arg1 +--* LCL_VAR ref V02 loc0 [000103] ------------ arg2 \--* CNS_INT int 0 argSlots=3, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000319] -----+------ * LCL_VAR ref V15 tmp9 Replaced with placeholder node: [000485] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000102] -----+------ * LCL_VAR ref V02 loc0 Replaced with placeholder node: [000487] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000103] -----+------ * CNS_INT int 0 Replaced with placeholder node: [000489] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx r8 fgArgTabEntry[arg 0 319.LCL_VAR, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 102.LCL_VAR, rdx, regs=1, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 2 103.CNS_INT, r8, regs=1, align=1, lateArgInx=2, processed] GenTreeNode creates assertion: [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return In BB56 New Local Constant Assertion: V15 != null index=#01, mask=0000000000000001 fgMorphTree BB56, stmt 32 (after) [000104] --CXG+------ * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000103] -----+------ arg2 in r8 \--* CNS_INT int 0 fgMorphTree BB56, stmt 33 (before) [000108] ------------ * RETFILT void Morphing BB06 of 'Stream:Read(struct):int:this' fgMorphTree BB06, stmt 34 (before) [000079] ------------ * RETURN int [000078] ------------ \--* LCL_VAR int V05 loc3 Method has EH, marking method as fully interruptible Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB62 [0047] 1 1 [???..???) i internal BB01 [0000] 1 1 [000..012) i BB14 [0008] 1 1 [000..001) i BB15 [0009] 1 1 [000..001) i BB16 [0013] 1 1 [???..???) internal gcsafe BB02 [0001] 1 0 1 [012..02E)-> BB04 ( cond ) T0 try { keep i try label gcsafe BB03 [0002] 1 0 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB04 [0003] 1 0 1 [039..04E) T0 i BB31 [0019] 1 0 1 [000..000)-> BB33 ( cond ) T0 i internal BB32 [0020] 1 0 0 [000..000) (throw ) T0 i internal rare gcsafe BB33 [0021] 2 0 0.50 [000..000)-> BB34 (always) T0 i internal newobj BB34 [0024] 3 0 0.50 [000..000)-> BB36 ( cond ) T0 i internal idxlen BB35 [0025] 1 0 0.50 [000..000)-> BB37 ( cond ) T0 i internal idxlen BB36 [0026] 2 0 0 [000..000) (throw ) T0 i internal rare gcsafe BB37 [0027] 2 0 1 [000..000) T0 i internal BB38 [0028] 1 0 1 [???..???) T0 internal BB44 [0032] 1 0 1 [042..043)-> BB46 ( cond ) T0 i BB45 [0033] 1 0 0 [042..043) (throw ) T0 i rare gcsafe BB46 [0034] 2 0 1 [042..043) T0 i BB47 [0035] 1 0 1 [???..???)-> BB07 (always) T0 } internal BB07 [0006] 1 1 [???..???) i internal BB58 [0043] 2 1 [04E..05B) keep i label target cfb BB59 [0044] 1 1 [04E..04F) i BB60 [0045] 1 1 [04E..04F) i BB61 [0046] 1 1 [???..???)-> BB06 (always) keep internal label gcsafe cfe BB05 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB54 [0036] 1 0 1 [04E..04F) H0 i BB55 [0037] 1 0 1 [04E..04F) H0 i BB56 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label gcsafe BB06 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB02..BB47 [012..04E), Fault at BB05..BB56 [04E..05B) Renumber BB62 to BB01 Renumber BB01 to BB02 Renumber BB14 to BB03 Renumber BB15 to BB04 Renumber BB16 to BB05 Renumber BB02 to BB06 Renumber BB03 to BB07 Renumber BB04 to BB08 Renumber BB31 to BB09 Renumber BB32 to BB10 Renumber BB33 to BB11 Renumber BB34 to BB12 Renumber BB35 to BB13 Renumber BB36 to BB14 Renumber BB37 to BB15 Renumber BB38 to BB16 Renumber BB44 to BB17 Renumber BB45 to BB18 Renumber BB46 to BB19 Renumber BB47 to BB20 Renumber BB07 to BB21 Renumber BB58 to BB22 Renumber BB59 to BB23 Renumber BB60 to BB24 Renumber BB61 to BB25 Renumber BB05 to BB26 Renumber BB54 to BB27 Renumber BB55 to BB28 Renumber BB56 to BB29 Renumber BB06 to BB30 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal BB02 [0000] 1 1 [000..012) i BB03 [0008] 1 1 [000..001) i BB04 [0009] 1 1 [000..001) i BB05 [0013] 1 1 [???..???) internal gcsafe BB06 [0001] 1 0 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 1 [039..04E) T0 i BB09 [0019] 1 0 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 2 0 0.50 [000..000)-> BB12 (always) T0 i internal newobj BB12 [0024] 3 0 0.50 [000..000)-> BB14 ( cond ) T0 i internal idxlen BB13 [0025] 1 0 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 0 [000..000) (throw ) T0 i internal rare gcsafe BB15 [0027] 2 0 1 [000..000) T0 i internal BB16 [0028] 1 0 1 [???..???) T0 internal BB17 [0032] 1 0 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 2 0 1 [042..043) T0 i BB20 [0035] 1 0 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 1 [???..???) i internal BB22 [0043] 2 1 [04E..05B) keep i label target cfb BB23 [0044] 1 1 [04E..04F) i BB24 [0045] 1 1 [04E..04F) i BB25 [0046] 1 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB26 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB27 [0036] 1 0 1 [04E..04F) H0 i BB28 [0037] 1 0 1 [04E..04F) H0 i BB29 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label gcsafe BB30 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB20 [012..04E), Fault at BB26..BB29 [04E..05B) New BlockSet epoch 2, # of blocks (including unused BB00): 31, bitset array size: 1 (short) *************** In fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal BB02 [0000] 1 1 [000..012) i BB03 [0008] 1 1 [000..001) i BB04 [0009] 1 1 [000..001) i BB05 [0013] 1 1 [???..???) internal gcsafe BB06 [0001] 1 0 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 1 [039..04E) T0 i BB09 [0019] 1 0 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 2 0 0.50 [000..000)-> BB12 (always) T0 i internal newobj BB12 [0024] 3 0 0.50 [000..000)-> BB14 ( cond ) T0 i internal idxlen BB13 [0025] 1 0 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 0 [000..000) (throw ) T0 i internal rare gcsafe BB15 [0027] 2 0 1 [000..000) T0 i internal BB16 [0028] 1 0 1 [???..???) T0 internal BB17 [0032] 1 0 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 2 0 1 [042..043) T0 i BB20 [0035] 1 0 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 1 [???..???) i internal BB22 [0043] 2 1 [04E..05B) keep i label target cfb BB23 [0044] 1 1 [04E..04F) i BB24 [0045] 1 1 [04E..04F) i BB25 [0046] 1 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB26 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB27 [0036] 1 0 1 [04E..04F) H0 i BB28 [0037] 1 0 1 [04E..04F) H0 i BB29 [0041] 1 0 1 [???..???) (finret) H0 } keep internal label gcsafe BB30 [0005] 1 1 [05B..05D) (return) i -------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i BB03 [0008] 1 BB02 1 [000..001) i BB04 [0009] 1 BB03 1 [000..001) i BB05 [0013] 1 BB04 1 [???..???) internal gcsafe BB06 [0001] 1 0 BB05 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [039..04E) T0 i label target BB09 [0019] 1 0 BB08 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 BB09 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB09 0.50 [000..000)-> BB12 (always) T0 i internal label target newobj BB12 [0024] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen BB13 [0025] 1 0 BB12 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB12,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..000) T0 i internal label target BB16 [0028] 1 0 BB15 1 [???..???) T0 internal BB17 [0032] 1 0 BB16 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 BB17 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB17 1 [042..043) T0 i label target BB20 [0035] 1 0 BB19 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 BB20 1 [???..???) i internal label target BB22 [0043] 1 BB21 1 [04E..05B) keep i label target cfb BB23 [0044] 1 BB22 1 [04E..04F) i BB24 [0045] 1 BB23 1 [04E..04F) i BB25 [0046] 1 BB24 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB26 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB27 [0036] 1 0 BB26 1 [04E..04F) H0 i BB28 [0037] 1 0 BB27 1 [04E..04F) H0 i BB29 [0041] 1 0 BB28 1 [???..???) (finret) H0 } keep internal label gcsafe BB30 [0005] 1 BB25 1 [05B..05D) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgComputeEdgeWeights() fgComputeEdgeWeights() we do not have any profile data so we are not using the edge weights -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i BB03 [0008] 1 BB02 1 [000..001) i BB04 [0009] 1 BB03 1 [000..001) i BB05 [0013] 1 BB04 1 [???..???) internal gcsafe BB06 [0001] 1 0 BB05 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [039..04E) T0 i label target BB09 [0019] 1 0 BB08 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 BB09 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB09 0.50 [000..000)-> BB12 (always) T0 i internal label target newobj BB12 [0024] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen BB13 [0025] 1 0 BB12 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB12,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..000) T0 i internal label target BB16 [0028] 1 0 BB15 1 [???..???) T0 internal BB17 [0032] 1 0 BB16 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 BB17 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB17 1 [042..043) T0 i label target BB20 [0035] 1 0 BB19 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 BB20 1 [???..???) i internal label target BB22 [0043] 1 BB21 1 [04E..05B) keep i label target cfb BB23 [0044] 1 BB22 1 [04E..04F) i BB24 [0045] 1 BB23 1 [04E..04F) i BB25 [0046] 1 BB24 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB26 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB27 [0036] 1 0 BB26 1 [04E..04F) H0 i BB28 [0037] 1 0 BB27 1 [04E..04F) H0 i BB29 [0041] 1 0 BB28 1 [???..???) (finret) H0 } keep internal label gcsafe BB30 [0005] 1 BB25 1 [05B..05D) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- fgComputeEdgeWeights() found inconsistent profile data, not using the edge weights *************** In fgCreateFunclets() Relocating handler range BB26..BB29 (EH#0) to end of BBlist -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i BB03 [0008] 1 BB02 1 [000..001) i BB04 [0009] 1 BB03 1 [000..001) i BB05 [0013] 1 BB04 1 [???..???) internal gcsafe BB06 [0001] 1 0 BB05 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [039..04E) T0 i label target BB09 [0019] 1 0 BB08 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 BB09 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB09 0.50 [000..000)-> BB12 (always) T0 i internal label target newobj BB12 [0024] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen BB13 [0025] 1 0 BB12 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB12,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..000) T0 i internal label target BB16 [0028] 1 0 BB15 1 [???..???) T0 internal BB17 [0032] 1 0 BB16 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 BB17 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB17 1 [042..043) T0 i label target BB20 [0035] 1 0 BB19 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 BB20 1 [???..???) i internal label target BB22 [0043] 1 BB21 1 [04E..05B) keep i label target cfb BB23 [0044] 1 BB22 1 [04E..04F) i BB24 [0045] 1 BB23 1 [04E..04F) i BB25 [0046] 1 BB24 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB26 [0004] 1 0 1 [04E..05B) H0 fault { keep i label target BB27 [0036] 1 0 BB26 1 [04E..04F) H0 i BB28 [0037] 1 0 BB27 1 [04E..04F) H0 i BB29 [0041] 1 0 BB28 1 [???..???) (finret) H0 } keep internal label gcsafe BB30 [0005] 1 BB25 1 [05B..05D) (return) i label target -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB20 [012..04E), Fault at BB26..BB29 [04E..05B) Relocated blocks [BB26..BB29] inserted after BB30 at the end of method Create funclets: moved region *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB20 [012..04E), Fault at BB26..BB29 [04E..05B) After fgCreateFunclets() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i BB03 [0008] 1 BB02 1 [000..001) i BB04 [0009] 1 BB03 1 [000..001) i BB05 [0013] 1 BB04 1 [???..???) internal gcsafe BB06 [0001] 1 0 BB05 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [039..04E) T0 i label target BB09 [0019] 1 0 BB08 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 BB09 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB09 0.50 [000..000)-> BB12 (always) T0 i internal label target newobj BB12 [0024] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen BB13 [0025] 1 0 BB12 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB12,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..000) T0 i internal label target BB16 [0028] 1 0 BB15 1 [???..???) T0 internal BB17 [0032] 1 0 BB16 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 BB17 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB17 1 [042..043) T0 i label target BB20 [0035] 1 0 BB19 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 BB20 1 [???..???) i internal label target BB22 [0043] 1 BB21 1 [04E..05B) keep i label target cfb BB23 [0044] 1 BB22 1 [04E..04F) i BB24 [0045] 1 BB23 1 [04E..04F) i BB25 [0046] 1 BB24 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB30 [0005] 1 BB25 1 [05B..05D) (return) i label target ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB27 [0036] 1 0 BB26 1 [04E..04F) H0 i BB28 [0037] 1 0 BB27 1 [04E..04F) H0 i BB29 [0041] 1 0 BB28 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB20 [012..04E), Fault at BB26..BB29 [04E..05B) *************** In fgDebugCheckBBlist *************** In optOptimizeLayout() *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB20 [012..04E), Fault at BB26..BB29 [04E..05B) *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i BB03 [0008] 1 BB02 1 [000..001) i BB04 [0009] 1 BB03 1 [000..001) i BB05 [0013] 1 BB04 1 [???..???) internal gcsafe BB06 [0001] 1 0 BB05 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [039..04E) T0 i label target BB09 [0019] 1 0 BB08 1 [000..000)-> BB11 ( cond ) T0 i internal BB10 [0020] 1 0 BB09 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB09 0.50 [000..000)-> BB12 (always) T0 i internal label target newobj BB12 [0024] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen BB13 [0025] 1 0 BB12 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB12,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..000) T0 i internal label target BB16 [0028] 1 0 BB15 1 [???..???) T0 internal BB17 [0032] 1 0 BB16 1 [042..043)-> BB19 ( cond ) T0 i BB18 [0033] 1 0 BB17 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB17 1 [042..043) T0 i label target BB20 [0035] 1 0 BB19 1 [???..???)-> BB21 (always) T0 } internal BB21 [0006] 1 BB20 1 [???..???) i internal label target BB22 [0043] 1 BB21 1 [04E..05B) keep i label target cfb BB23 [0044] 1 BB22 1 [04E..04F) i BB24 [0045] 1 BB23 1 [04E..04F) i BB25 [0046] 1 BB24 1 [???..???)-> BB30 (always) keep internal label gcsafe cfe BB30 [0005] 1 BB25 1 [05B..05D) (return) i label target ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB27 [0036] 1 0 BB26 1 [04E..04F) H0 i BB28 [0037] 1 0 BB27 1 [04E..04F) H0 i BB29 [0041] 1 0 BB28 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB02 and BB03: *************** In fgDebugCheckBBlist Compacting blocks BB02 and BB04: *************** In fgDebugCheckBBlist Compacting blocks BB02 and BB05: *************** In fgDebugCheckBBlist Compacting blocks BB08 and BB09: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB11 -> BB12) (converted BB11 to fall-through) Compacting blocks BB11 and BB12: *************** In fgDebugCheckBBlist Compacting blocks BB15 and BB16: *************** In fgDebugCheckBBlist Compacting blocks BB15 and BB17: *************** In fgDebugCheckBBlist Compacting blocks BB19 and BB20: EH#0: New last block of try: BB19 *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB19 -> BB21) (converted BB19 to fall-through) fgRemoveBlock BB21 Removing empty BB21 Compacting blocks BB22 and BB23: *************** In fgDebugCheckBBlist Compacting blocks BB22 and BB24: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB25 -> BB30) (converted BB25 to fall-through) Compacting blocks BB25 and BB30: *************** In fgDebugCheckBBlist Compacting blocks BB26 and BB27: *************** In fgDebugCheckBBlist Compacting blocks BB26 and BB28: *************** In fgDebugCheckBBlist After updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [000..04E)-> BB11 ( cond ) T0 i label target BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..043)-> BB19 ( cond ) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB15 1 [042..043) T0 } i label target BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB19 [012..04E), Fault at BB26..BB29 [04E..05B) *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB08 ( cond ) T0 try { keep i try label gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare gcsafe newobj BB08 [0003] 1 0 BB06 1 [000..04E)-> BB11 ( cond ) T0 i label target BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare gcsafe BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..043)-> BB19 ( cond ) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB15 1 [042..043) T0 } i label target BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB06 branch to BB08 since it falls into a rarely run block fgFindInsertPoint(regionIndex=1, putInTryRegion=true, startBlk=BB06, endBlk=BB22, nearBlk=BB08, jumpBlk=BB00, runRarely=true) Relocated rarely run block BB07 by reversing conditional jump at BB06 Relocated block [BB07..BB07] inserted after BB10 After this change in fgReorderBlocks the BB graph is: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB07 ( cond ) T0 try { keep i try label gcsafe BB08 [0003] 1 0 BB06 1 [000..04E)-> BB11 ( cond ) T0 i label target BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare label target gcsafe newobj BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB15 [0027] 1 0 BB13 1 [000..043)-> BB19 ( cond ) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB15 1 [042..043) T0 } i label target BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB08 branch to BB11 since it falls into a rarely run block fgFindInsertPoint(regionIndex=1, putInTryRegion=true, startBlk=BB06, endBlk=BB22, nearBlk=BB11, jumpBlk=BB00, runRarely=true) Relocated rarely run blocks (BB10 .. BB07) by reversing conditional jump at BB08 Relocated blocks [BB10..BB07] inserted after BB14 After this change in fgReorderBlocks the BB graph is: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB07 ( cond ) T0 try { keep i try label gcsafe BB08 [0003] 1 0 BB06 1 [000..04E)-> BB10 ( cond ) T0 i label target BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB15 ( cond ) T0 i internal idxlen BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare label target gcsafe newobj BB15 [0027] 1 0 BB13 1 [000..043)-> BB19 ( cond ) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare gcsafe BB19 [0034] 1 0 BB15 1 [042..043) T0 } i label target BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB13 branch to BB15 since it falls into a rarely run block fgFindInsertPoint(regionIndex=1, putInTryRegion=true, startBlk=BB06, endBlk=BB22, nearBlk=BB15, jumpBlk=BB00, runRarely=true) Relocated rarely run blocks (BB14 .. BB07) by reversing conditional jump at BB13 Relocated blocks [BB14..BB07] inserted after BB18 After this change in fgReorderBlocks the BB graph is: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB07 ( cond ) T0 try { keep i try label gcsafe BB08 [0003] 1 0 BB06 1 [000..04E)-> BB10 ( cond ) T0 i label target BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal idxlen BB15 [0027] 1 0 BB13 1 [000..043)-> BB19 ( cond ) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare gcsafe BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 i rare label target gcsafe newobj BB19 [0034] 1 0 BB15 1 [042..043) T0 } i label target BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB15 branch to BB19 since it falls into a rarely run block fgFindInsertPoint(regionIndex=1, putInTryRegion=true, startBlk=BB06, endBlk=BB22, nearBlk=BB19, jumpBlk=BB00, runRarely=true) Relocated rarely run blocks (BB18 .. BB07) by reversing conditional jump at BB15 EH#0: New last block of try: BB07 Relocated blocks [BB18..BB07] inserted after BB19 Block BB19 ended with a BBJ_NONE, Changed to an unconditional jump to BB22 After this change in fgReorderBlocks the BB graph is: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB07 ( cond ) T0 try { keep i try label gcsafe BB08 [0003] 1 0 BB06 1 [000..04E)-> BB10 ( cond ) T0 i label target BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal idxlen BB15 [0027] 1 0 BB13 1 [000..043)-> BB18 ( cond ) T0 i label target BB19 [0034] 1 0 BB15 1 [042..043)-> BB22 (always) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare label target gcsafe BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- Decided to straighten unconditional branch at block BB19 branch to BB22 since it is succeeded by a rarely run block fgFindInsertPoint(regionIndex=1, putInTryRegion=true, startBlk=BB06, endBlk=BB22, nearBlk=BB22, jumpBlk=BB00, runRarely=true) Could not relocate blocks (BB18 .. BB07) *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB07 ( cond ) T0 try { keep i try label gcsafe BB08 [0003] 1 0 BB06 1 [000..04E)-> BB10 ( cond ) T0 i label target BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal idxlen BB15 [0027] 1 0 BB13 1 [000..043)-> BB18 ( cond ) T0 i label target BB19 [0034] 1 0 BB15 1 [042..043)-> BB22 (always) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare label target gcsafe BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB06 [0001] 1 0 BB02 1 [012..02E)-> BB07 ( cond ) T0 try { keep i try label gcsafe BB08 [0003] 1 0 BB06 1 [000..04E)-> BB10 ( cond ) T0 i label target BB11 [0021] 1 0 BB08 0.50 [000..000)-> BB14 ( cond ) T0 i internal label target idxlen newobj BB13 [0025] 1 0 BB11 0.50 [000..000)-> BB14 ( cond ) T0 i internal idxlen BB15 [0027] 1 0 BB13 1 [000..043)-> BB18 ( cond ) T0 i label target BB19 [0034] 1 0 BB15 1 [042..043)-> BB22 (always) T0 i label target BB18 [0033] 1 0 BB15 0 [042..043) (throw ) T0 i rare label target gcsafe BB14 [0026] 2 0 BB11,BB13 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB10 [0020] 1 0 BB08 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB07 [0002] 1 0 BB06 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB22 [0043] 1 BB19 1 [04E..05B) keep i label target cfb BB25 [0046] 1 BB22 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB26 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB29 [0041] 1 0 BB26 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB06..BB07 [012..04E), Fault at BB26..BB29 [04E..05B) Renumber BB06 to BB03 Renumber BB08 to BB04 Renumber BB11 to BB05 Renumber BB13 to BB06 Renumber BB15 to BB07 Renumber BB19 to BB08 Renumber BB18 to BB09 Renumber BB14 to BB10 Renumber BB10 to BB11 Renumber BB07 to BB12 Renumber BB22 to BB13 Renumber BB25 to BB14 Renumber BB26 to BB15 Renumber BB29 to BB16 *************** After renumbering the basic blocks -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB16 [0041] 1 0 BB15 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB03..BB12 [012..04E), Fault at BB15..BB16 [04E..05B) New BlockSet epoch 3, # of blocks (including unused BB00): 17, bitset array size: 1 (short) Enter blocks: BB01 BB15 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB04 : BB01 BB02 BB03 BB04 BB05 : BB01 BB02 BB03 BB04 BB05 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB09 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB10 BB11 : BB01 BB02 BB03 BB04 BB11 BB12 : BB01 BB02 BB03 BB12 BB13 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB13 BB14 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB13 BB14 BB15 : BB15 BB16 : BB15 BB16 After computing reachability: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB16 [0041] 1 0 BB15 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 BB15 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB15: BB15 BB16: BB16 BB15 BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB02 BB01 BB04: BB04 BB03 BB02 BB01 BB05: BB05 BB04 BB03 BB02 BB01 BB06: BB06 BB05 BB04 BB03 BB02 BB01 BB07: BB07 BB06 BB05 BB04 BB03 BB02 BB01 BB08: BB08 BB07 BB06 BB05 BB04 BB03 BB02 BB01 BB13: BB13 BB08 BB07 BB06 BB05 BB04 BB03 BB02 BB01 BB14: BB14 BB13 BB08 BB07 BB06 BB05 BB04 BB03 BB02 BB01 BB09: BB09 BB07 BB06 BB05 BB04 BB03 BB02 BB01 BB10: BB10 BB05 BB04 BB03 BB02 BB01 BB11: BB11 BB04 BB03 BB02 BB01 BB12: BB12 BB03 BB02 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB02 BB02 : BB03 BB03 : BB12 BB04 BB04 : BB11 BB05 BB05 : BB10 BB06 BB06 : BB07 BB07 : BB09 BB08 BB08 : BB13 BB13 : BB14 BB15 : BB16 *************** In Allocate Objects Trees before Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB16 [0041] 1 0 BB15 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000357] ------------ * STMT void (IL ???... ???) [000369] x----------- | /--* IND int [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000368] ------------ | | \--* ADD byref [000366] ------------ | | \--* LCL_VAR byref V01 arg1 [000370] -A---------- | /--* ASG int [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 [000371] -A---+------ \--* COMMA void [000363] x----------- | /--* IND byref [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000362] ------------ | | \--* ADD byref [000360] ------------ | | \--* LCL_VAR byref V01 arg1 [000364] -A---------- \--* ASG byref [000359] D------N---- \--* LCL_VAR byref V16 tmp10 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 [000128] ------------ * STMT void (IL 0x000... ???) [000140] --CXG+------ | /--* IND ref [000138] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG+------ | | \--* ADD byref [000137] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----+------ arg0 in rcx | | +--* IND long [000132] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000127] -ACXG+------ \--* ASG ref [000126] D----+-N---- \--* LCL_VAR ref V09 tmp3 ***** BB02, stmt 3 [000010] ------------ * STMT void (IL ???... ???) [000129] -----+------ | /--* LCL_VAR ref V09 tmp3 [000009] -A---+------ \--* ASG ref [000008] D----+-N---- \--* LCL_VAR ref V06 tmp0 ***** BB02, stmt 4 [000017] ------------ * STMT void (IL ???... ???) [000013] --CXG+------ | /--* CALLV ind ref ArrayPool`1.Rent [000011] -----+------ this in rcx | | +--* LCL_VAR ref V09 tmp3 [000145] -----+------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 [000016] -ACXG+------ \--* ASG ref [000015] D----+-N---- \--* LCL_VAR ref V02 loc0 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 5 [000033] ------------ * STMT void (IL ???... ???) [000027] --CXG+------ | /--* CALLV ind int Stream.Read [000019] -----+------ this in rcx | | +--* LCL_VAR ref V00 this [000020] -----+------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 [000150] -----+------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 [000021] -----+------ arg2 in r8 | | \--* CNS_INT int 0 [000032] -ACXG+------ \--* ASG int [000031] D----+-N---- \--* LCL_VAR int V03 loc1 ***** BB03, stmt 6 [000044] ------------ * STMT void (IL ???... ???) [000043] -----+------ \--* JTRUE void [000041] -----+------ | /--* CAST long <- int [000155] -----+------ | | \--* LCL_VAR int V17 tmp11 [000042] J----+-N---- \--* GT int [000035] -----+---U-- \--* CAST long <- ulong <- uint [000034] -----+------ \--* LCL_VAR int V03 loc1 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 7 [000052] ------------ * STMT void (IL 0x039...0x041) [000411] ------------ | /--* CNS_INT int 0 [000412] -A---------- | /--* ASG int [000410] D------N---- | | \--* LCL_VAR int V21 tmp15 [000413] -A---+------ \--* COMMA void [000408] ------------ | /--* CNS_INT byref 0 [000409] -A---------- \--* ASG byref [000407] D------N---- \--* LCL_VAR byref V20 tmp14 ***** BB04, stmt 8 [000168] ------------ * STMT void (IL ???... ???) [000167] -----+------ \--* JTRUE void [000165] -----+------ | /--* CNS_INT ref null [000166] J----+-N---- \--* EQ int [000046] -----+------ \--* LCL_VAR ref V02 loc0 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 9 [000175] ------------ * STMT void (IL ???... ???) [000172] -----+------ | /--* CNS_INT int 0 [000174] -A---+------ \--* ASG ubyte [000170] D----+-N---- \--* LCL_VAR int V10 tmp4 ***** BB05, stmt 10 [000201] ------------ * STMT void (IL ???... ???) [000200] ---X-+------ \--* JTRUE void [000197] ---X-+------ | /--* ARR_LENGTH int [000196] -----+------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-+-N-U-- \--* GT int [000195] -----+------ \--* CNS_INT int 0 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 11 [000251] ------------ * STMT void (IL ???... ???) [000250] ---X-+------ \--* JTRUE void [000246] ---X-+------ | /--* ARR_LENGTH int [000245] -----+------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-+-N-U-- \--* GT int [000244] -----+------ \--* LCL_VAR int V03 loc1 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 12 [000266] ------------ * STMT void (IL ???... ???) [000419] -----+------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] [000420] -----+------ | /--* ADD byref [000418] -----+------ | | \--* LCL_VAR ref V02 loc0 [000421] ---XG+-N---- | /--* COMMA byref [000417] ---X-+-N---- | | \--* NULLCHECK byte [000416] -----+------ | | \--* LCL_VAR ref V02 loc0 [000265] -A-XG+------ \--* ASG byref [000264] D----+-N---- \--* LCL_VAR byref V13 tmp7 ***** BB07, stmt 13 [000226] ------------ * STMT void (IL ???... ???) [000424] ------------ | /--* CNS_INT byref 0 [000425] -A---+------ \--* ASG byref [000423] D------N---- \--* LCL_VAR byref V22 tmp16 ***** BB07, stmt 14 [000232] ------------ * STMT void (IL ???... ???) [000263] -----+------ | /--* LCL_VAR byref V13 tmp7 [000230] -A---+------ \--* ASG byref [000229] D----+-N---- \--* LCL_VAR byref V22 tmp16 ***** BB07, stmt 15 [000237] ------------ * STMT void (IL ???... ???) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 [000428] -A---+------ \--* ASG byref [000426] D------N---- \--* LCL_VAR byref V20 tmp14 ***** BB07, stmt 16 [000242] ------------ * STMT void (IL ???... ???) [000048] -----+------ | /--* LCL_VAR int V03 loc1 [000241] -A---+------ \--* ASG int [000240] D----+-N---- \--* LCL_VAR int V21 tmp15 ***** BB07, stmt 17 [000064] ------------ * STMT void (IL 0x041... ???) [000433] -------N---- | /--* LCL_VAR int V21 tmp15 [000434] -A--G------- | /--* ASG int [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 [000435] -A--G+------ \--* COMMA void [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 [000431] -A--G------- \--* ASG byref [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 18 [000297] ------------ * STMT void (IL 0x042... ???) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 [000441] -A---------- | /--* ASG int [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 [000442] -A---+------ \--* COMMA void [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 [000438] -A---------- \--* ASG byref [000436] D------N---- \--* LCL_VAR byref V23 tmp17 ***** BB07, stmt 19 [000289] ------------ * STMT void (IL 0x042... ???) [000288] -ACXG+------ \--* JTRUE void [000286] -----+------ | /--* CNS_INT int 0 [000287] JACXG+-N---- \--* EQ int [000280] -ACXG+------ \--* CALL int Span`1.TryCopyTo [000277] L----+------ | /--* ADDR byref [000278] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 [000465] -A--------L- this SETUP +--* ASG byref [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 [000461] -------N---- | /--* LCL_VAR int V24 tmp18 [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 [000460] *------N---- | | \--* IND int [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000459] ------------ | | \--* ADD byref [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 [000463] -A---+----L- arg1 SETUP +--* COMMA void [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 [000453] *------N---- | | | \--* IND byref [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] [000452] ------------ | | | \--* ADD byref [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 [000456] -A---------- | \--* COMMA void [000446] L----------- | | /--* ADDR byref [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 [000449] -A---------- | \--* ASG byref [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 [000469] L----------- arg1 in rdx \--* ADDR byref [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 20 [000076] ------------ * STMT void (IL 0x04A... ???) [000073] -----+------ | /--* LCL_VAR int V03 loc1 [000075] -A---+------ \--* ASG int [000074] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 21 [000293] ------------ * STMT void (IL 0x042... ???) [000292] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 22 [000204] ------------ * STMT void (IL ???... ???) [000203] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 23 [000256] ------------ * STMT void (IL ???... ???) [000254] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentNullException [000253] -----+------ arg0 in rcx \--* CNS_INT int 2 ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 24 [000089] ------------ * STMT void (IL ???... ???) [000086] -----+------ | /--* ALLOCOBJ ref [000085] -----+------ | | \--* CNS_INT(h) long 0x17dd3b22ac8 method [000088] -A---+------ \--* ASG ref [000087] D----+-N---- \--* LCL_VAR ref V08 tmp2 ***** BB12, stmt 25 [000093] ------------ * STMT void (IL ???... ???) [000091] --CXG+------ \--* CALL void IOException..ctor [000160] --CXG+------ | /--* CALL ref SR.GetResourceString [000390] --CXG+------ | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- arg0 SETUP | | +--* ASG ref [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 [000159] -----+------ arg1 in rdx | | \--* CNS_INT ref null [000400] -ACXG-----L- arg1 SETUP +--* ASG ref [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 [000090] -----+------ this in rcx \--* LCL_VAR ref V08 tmp2 ***** BB12, stmt 26 [000097] ------------ * STMT void (IL 0x038... ???) [000096] --CXG+------ \--* CALL help void HELPER.CORINFO_HELP_THROW [000094] -----+------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 27 [000343] ------------ * STMT void (IL ???... ???) [000334] --CXG+------ | /--* IND ref [000342] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000335] --CXG+------ | | \--* ADD byref [000336] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000338] #----+------ arg0 in rcx | | +--* IND long [000339] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000341] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000332] -ACXG+------ \--* ASG ref [000333] D----+-N---- \--* LCL_VAR ref V15 tmp9 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 28 [000350] ------------ * STMT void (IL ???... ???) [000344] --CXG+------ \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000345] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000347] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000349] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB14, stmt 29 [000080] ------------ * STMT void (IL 0x05B...0x05C) [000079] -----+------ \--* RETURN int [000078] -----+------ \--* LCL_VAR int V05 loc3 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 30 [000318] ------------ * STMT void (IL 0x04E... ???) [000330] --CXG+------ | /--* IND ref [000328] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG+------ | | \--* ADD byref [000327] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----+------ arg0 in rcx | | +--* IND long [000322] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000317] -ACXG+------ \--* ASG ref [000316] D----+-N---- \--* LCL_VAR ref V15 tmp9 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 31 [000107] ------------ * STMT void (IL ???... ???) [000104] --CXG+------ \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000103] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB16, stmt 32 [000109] ------------ * STMT void (IL 0x05A... ???) [000108] -----+------ \--* RETFILT void ------------------------------------------------------------------------------------------------------------------- argSlots=1, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000085] -----+------ * CNS_INT(h) long 0x17dd3b22ac8 method Replaced with placeholder node: [000492] ----------L- * ARGPLACE long Shuffled argument table: rcx fgArgTabEntry[arg 0 85.CNS_INT, rcx, regs=1, align=1, lateArgInx=0, processed] *************** Exiting Allocate Objects Trees after Allocate Objects -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 1 [04E..05B) H0 F fault { keep i label target flet BB16 [0041] 1 0 BB15 1 [???..???) (finret) H0 } keep internal label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 [000357] ------------ * STMT void (IL ???... ???) [000369] x----------- | /--* IND int [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000368] ------------ | | \--* ADD byref [000366] ------------ | | \--* LCL_VAR byref V01 arg1 [000370] -A---------- | /--* ASG int [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 [000371] -A---+------ \--* COMMA void [000363] x----------- | /--* IND byref [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000362] ------------ | | \--* ADD byref [000360] ------------ | | \--* LCL_VAR byref V01 arg1 [000364] -A---------- \--* ASG byref [000359] D------N---- \--* LCL_VAR byref V16 tmp10 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 [000128] ------------ * STMT void (IL 0x000... ???) [000140] --CXG+------ | /--* IND ref [000138] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG+------ | | \--* ADD byref [000137] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----+------ arg0 in rcx | | +--* IND long [000132] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000127] -ACXG+------ \--* ASG ref [000126] D----+-N---- \--* LCL_VAR ref V09 tmp3 ***** BB02, stmt 3 [000010] ------------ * STMT void (IL ???... ???) [000129] -----+------ | /--* LCL_VAR ref V09 tmp3 [000009] -A---+------ \--* ASG ref [000008] D----+-N---- \--* LCL_VAR ref V06 tmp0 ***** BB02, stmt 4 [000017] ------------ * STMT void (IL ???... ???) [000013] --CXG+------ | /--* CALLV ind ref ArrayPool`1.Rent [000011] -----+------ this in rcx | | +--* LCL_VAR ref V09 tmp3 [000145] -----+------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 [000016] -ACXG+------ \--* ASG ref [000015] D----+-N---- \--* LCL_VAR ref V02 loc0 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 5 [000033] ------------ * STMT void (IL ???... ???) [000027] --CXG+------ | /--* CALLV ind int Stream.Read [000019] -----+------ this in rcx | | +--* LCL_VAR ref V00 this [000020] -----+------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 [000150] -----+------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 [000021] -----+------ arg2 in r8 | | \--* CNS_INT int 0 [000032] -ACXG+------ \--* ASG int [000031] D----+-N---- \--* LCL_VAR int V03 loc1 ***** BB03, stmt 6 [000044] ------------ * STMT void (IL ???... ???) [000043] -----+------ \--* JTRUE void [000041] -----+------ | /--* CAST long <- int [000155] -----+------ | | \--* LCL_VAR int V17 tmp11 [000042] J----+-N---- \--* GT int [000035] -----+---U-- \--* CAST long <- ulong <- uint [000034] -----+------ \--* LCL_VAR int V03 loc1 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 7 [000052] ------------ * STMT void (IL 0x039...0x041) [000411] ------------ | /--* CNS_INT int 0 [000412] -A---------- | /--* ASG int [000410] D------N---- | | \--* LCL_VAR int V21 tmp15 [000413] -A---+------ \--* COMMA void [000408] ------------ | /--* CNS_INT byref 0 [000409] -A---------- \--* ASG byref [000407] D------N---- \--* LCL_VAR byref V20 tmp14 ***** BB04, stmt 8 [000168] ------------ * STMT void (IL ???... ???) [000167] -----+------ \--* JTRUE void [000165] -----+------ | /--* CNS_INT ref null [000166] J----+-N---- \--* EQ int [000046] -----+------ \--* LCL_VAR ref V02 loc0 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 9 [000175] ------------ * STMT void (IL ???... ???) [000172] -----+------ | /--* CNS_INT int 0 [000174] -A---+------ \--* ASG ubyte [000170] D----+-N---- \--* LCL_VAR int V10 tmp4 ***** BB05, stmt 10 [000201] ------------ * STMT void (IL ???... ???) [000200] ---X-+------ \--* JTRUE void [000197] ---X-+------ | /--* ARR_LENGTH int [000196] -----+------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-+-N-U-- \--* GT int [000195] -----+------ \--* CNS_INT int 0 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 11 [000251] ------------ * STMT void (IL ???... ???) [000250] ---X-+------ \--* JTRUE void [000246] ---X-+------ | /--* ARR_LENGTH int [000245] -----+------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-+-N-U-- \--* GT int [000244] -----+------ \--* LCL_VAR int V03 loc1 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 12 [000266] ------------ * STMT void (IL ???... ???) [000419] -----+------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] [000420] -----+------ | /--* ADD byref [000418] -----+------ | | \--* LCL_VAR ref V02 loc0 [000421] ---XG+-N---- | /--* COMMA byref [000417] ---X-+-N---- | | \--* NULLCHECK byte [000416] -----+------ | | \--* LCL_VAR ref V02 loc0 [000265] -A-XG+------ \--* ASG byref [000264] D----+-N---- \--* LCL_VAR byref V13 tmp7 ***** BB07, stmt 13 [000226] ------------ * STMT void (IL ???... ???) [000424] ------------ | /--* CNS_INT byref 0 [000425] -A---+------ \--* ASG byref [000423] D------N---- \--* LCL_VAR byref V22 tmp16 ***** BB07, stmt 14 [000232] ------------ * STMT void (IL ???... ???) [000263] -----+------ | /--* LCL_VAR byref V13 tmp7 [000230] -A---+------ \--* ASG byref [000229] D----+-N---- \--* LCL_VAR byref V22 tmp16 ***** BB07, stmt 15 [000237] ------------ * STMT void (IL ???... ???) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 [000428] -A---+------ \--* ASG byref [000426] D------N---- \--* LCL_VAR byref V20 tmp14 ***** BB07, stmt 16 [000242] ------------ * STMT void (IL ???... ???) [000048] -----+------ | /--* LCL_VAR int V03 loc1 [000241] -A---+------ \--* ASG int [000240] D----+-N---- \--* LCL_VAR int V21 tmp15 ***** BB07, stmt 17 [000064] ------------ * STMT void (IL 0x041... ???) [000433] -------N---- | /--* LCL_VAR int V21 tmp15 [000434] -A--G------- | /--* ASG int [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 [000435] -A--G+------ \--* COMMA void [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 [000431] -A--G------- \--* ASG byref [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 18 [000297] ------------ * STMT void (IL 0x042... ???) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 [000441] -A---------- | /--* ASG int [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 [000442] -A---+------ \--* COMMA void [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 [000438] -A---------- \--* ASG byref [000436] D------N---- \--* LCL_VAR byref V23 tmp17 ***** BB07, stmt 19 [000289] ------------ * STMT void (IL 0x042... ???) [000288] -ACXG+------ \--* JTRUE void [000286] -----+------ | /--* CNS_INT int 0 [000287] JACXG+-N---- \--* EQ int [000280] -ACXG+------ \--* CALL int Span`1.TryCopyTo [000277] L----+------ | /--* ADDR byref [000278] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 [000465] -A--------L- this SETUP +--* ASG byref [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 [000461] -------N---- | /--* LCL_VAR int V24 tmp18 [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 [000460] *------N---- | | \--* IND int [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000459] ------------ | | \--* ADD byref [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 [000463] -A---+----L- arg1 SETUP +--* COMMA void [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 [000453] *------N---- | | | \--* IND byref [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] [000452] ------------ | | | \--* ADD byref [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 [000456] -A---------- | \--* COMMA void [000446] L----------- | | /--* ADDR byref [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 [000449] -A---------- | \--* ASG byref [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 [000469] L----------- arg1 in rdx \--* ADDR byref [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 20 [000076] ------------ * STMT void (IL 0x04A... ???) [000073] -----+------ | /--* LCL_VAR int V03 loc1 [000075] -A---+------ \--* ASG int [000074] D----+-N---- \--* LCL_VAR int V05 loc3 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 21 [000293] ------------ * STMT void (IL 0x042... ???) [000292] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 22 [000204] ------------ * STMT void (IL ???... ???) [000203] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 23 [000256] ------------ * STMT void (IL ???... ???) [000254] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentNullException [000253] -----+------ arg0 in rcx \--* CNS_INT int 2 ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 24 [000089] ------------ * STMT void (IL ???... ???) [000086] --C--+------ | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000085] -----+------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method [000088] -AC--+------ \--* ASG ref [000087] D----+-N---- \--* LCL_VAR ref V08 tmp2 ***** BB12, stmt 25 [000093] ------------ * STMT void (IL ???... ???) [000091] --CXG+------ \--* CALL void IOException..ctor [000160] --CXG+------ | /--* CALL ref SR.GetResourceString [000390] --CXG+------ | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- arg0 SETUP | | +--* ASG ref [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 [000159] -----+------ arg1 in rdx | | \--* CNS_INT ref null [000400] -ACXG-----L- arg1 SETUP +--* ASG ref [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 [000090] -----+------ this in rcx \--* LCL_VAR ref V08 tmp2 ***** BB12, stmt 26 [000097] ------------ * STMT void (IL 0x038... ???) [000096] --CXG+------ \--* CALL help void HELPER.CORINFO_HELP_THROW [000094] -----+------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 27 [000343] ------------ * STMT void (IL ???... ???) [000334] --CXG+------ | /--* IND ref [000342] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000335] --CXG+------ | | \--* ADD byref [000336] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000338] #----+------ arg0 in rcx | | +--* IND long [000339] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000341] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000332] -ACXG+------ \--* ASG ref [000333] D----+-N---- \--* LCL_VAR ref V15 tmp9 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 28 [000350] ------------ * STMT void (IL ???... ???) [000344] --CXG+------ \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000345] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000347] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000349] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB14, stmt 29 [000080] ------------ * STMT void (IL 0x05B...0x05C) [000079] -----+------ \--* RETURN int [000078] -----+------ \--* LCL_VAR int V05 loc3 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 30 [000318] ------------ * STMT void (IL 0x04E... ???) [000330] --CXG+------ | /--* IND ref [000328] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG+------ | | \--* ADD byref [000327] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----+------ arg0 in rcx | | +--* IND long [000322] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000317] -ACXG+------ \--* ASG ref [000316] D----+-N---- \--* LCL_VAR ref V15 tmp9 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 31 [000107] ------------ * STMT void (IL ???... ???) [000104] --CXG+------ \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000103] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB16, stmt 32 [000109] ------------ * STMT void (IL 0x05A... ???) [000108] -----+------ \--* RETFILT void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In optOptimizeLoops() *************** In fgDebugCheckBBlist *************** In optCloneLoops() *************** In lvaMarkLocalVars() lvaGrabTemp returning 31 (V31 tmp25) (a long lifetime temp) called for OutgoingArgSpace. lvaGrabTemp returning 32 (V32 tmp26) (a long lifetime temp) called for PSPSym. Local V32 should not be enregistered because: it is address exposed *** marking local variables in block BB01 (weight=1 ) [000357] ------------ * STMT void (IL ???... ???) [000369] x----------- | /--* IND int [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000368] ------------ | | \--* ADD byref [000366] ------------ | | \--* LCL_VAR byref V01 arg1 [000370] -A---------- | /--* ASG int [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 [000371] -A---+------ \--* COMMA void [000363] x----------- | /--* IND byref [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] [000362] ------------ | | \--* ADD byref [000360] ------------ | | \--* LCL_VAR byref V01 arg1 [000364] -A---------- \--* ASG byref [000359] D------N---- \--* LCL_VAR byref V16 tmp10 New refCnts for V16: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 5, refCntWtd = 2 New refCnts for V17: refCnt = 1, refCntWtd = 2 New refCnts for V01: refCnt = 6, refCntWtd = 4 *** marking local variables in block BB02 (weight=1 ) [000128] ------------ * STMT void (IL 0x000... ???) [000140] --CXG+------ | /--* IND ref [000138] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000139] --CXG+------ | | \--* ADD byref [000137] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000133] #----+------ arg0 in rcx | | +--* IND long [000132] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000134] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000127] -ACXG+------ \--* ASG ref [000126] D----+-N---- \--* LCL_VAR ref V09 tmp3 New refCnts for V09: refCnt = 1, refCntWtd = 1 [000010] ------------ * STMT void (IL ???... ???) [000129] -----+------ | /--* LCL_VAR ref V09 tmp3 [000009] -A---+------ \--* ASG ref [000008] D----+-N---- \--* LCL_VAR ref V06 tmp0 New refCnts for V06: refCnt = 1, refCntWtd = 2 New refCnts for V09: refCnt = 2, refCntWtd = 2 [000017] ------------ * STMT void (IL ???... ???) [000013] --CXG+------ | /--* CALLV ind ref ArrayPool`1.Rent [000011] -----+------ this in rcx | | +--* LCL_VAR ref V09 tmp3 [000145] -----+------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 [000016] -ACXG+------ \--* ASG ref [000015] D----+-N---- \--* LCL_VAR ref V02 loc0 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V09: refCnt = 3, refCntWtd = 3 New refCnts for V17: refCnt = 2, refCntWtd = 3 *** marking local variables in block BB03 (weight=1 ) [000033] ------------ * STMT void (IL ???... ???) [000027] --CXG+------ | /--* CALLV ind int Stream.Read [000019] -----+------ this in rcx | | +--* LCL_VAR ref V00 this [000020] -----+------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 [000150] -----+------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 [000021] -----+------ arg2 in r8 | | \--* CNS_INT int 0 [000032] -ACXG+------ \--* ASG int [000031] D----+-N---- \--* LCL_VAR int V03 loc1 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V17: refCnt = 3, refCntWtd = 4 [000044] ------------ * STMT void (IL ???... ???) [000043] -----+------ \--* JTRUE void [000041] -----+------ | /--* CAST long <- int [000155] -----+------ | | \--* LCL_VAR int V17 tmp11 [000042] J----+-N---- \--* GT int [000035] -----+---U-- \--* CAST long <- ulong <- uint [000034] -----+------ \--* LCL_VAR int V03 loc1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V17: refCnt = 4, refCntWtd = 5 *** marking local variables in block BB04 (weight=1 ) [000052] ------------ * STMT void (IL 0x039...0x041) [000411] ------------ | /--* CNS_INT int 0 [000412] -A---------- | /--* ASG int [000410] D------N---- | | \--* LCL_VAR int V21 tmp15 [000413] -A---+------ \--* COMMA void [000408] ------------ | /--* CNS_INT byref 0 [000409] -A---------- \--* ASG byref [000407] D------N---- \--* LCL_VAR byref V20 tmp14 New refCnts for V20: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 1, refCntWtd = 1 [000168] ------------ * STMT void (IL ???... ???) [000167] -----+------ \--* JTRUE void [000165] -----+------ | /--* CNS_INT ref null [000166] J----+-N---- \--* EQ int [000046] -----+------ \--* LCL_VAR ref V02 loc0 New refCnts for V02: refCnt = 3, refCntWtd = 3 *** marking local variables in block BB05 (weight=0.50) [000175] ------------ * STMT void (IL ???... ???) [000172] -----+------ | /--* CNS_INT int 0 [000174] -A---+------ \--* ASG ubyte [000170] D----+-N---- \--* LCL_VAR int V10 tmp4 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 [000201] ------------ * STMT void (IL ???... ???) [000200] ---X-+------ \--* JTRUE void [000197] ---X-+------ | /--* ARR_LENGTH int [000196] -----+------ | | \--* LCL_VAR ref V02 loc0 [000199] N--X-+-N-U-- \--* GT int [000195] -----+------ \--* CNS_INT int 0 New refCnts for V02: refCnt = 4, refCntWtd = 3.50 *** marking local variables in block BB06 (weight=0.50) [000251] ------------ * STMT void (IL ???... ???) [000250] ---X-+------ \--* JTRUE void [000246] ---X-+------ | /--* ARR_LENGTH int [000245] -----+------ | | \--* LCL_VAR ref V02 loc0 [000249] N--X-+-N-U-- \--* GT int [000244] -----+------ \--* LCL_VAR int V03 loc1 New refCnts for V03: refCnt = 3, refCntWtd = 2.50 New refCnts for V02: refCnt = 5, refCntWtd = 4 *** marking local variables in block BB07 (weight=1 ) [000266] ------------ * STMT void (IL ???... ???) [000419] -----+------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] [000420] -----+------ | /--* ADD byref [000418] -----+------ | | \--* LCL_VAR ref V02 loc0 [000421] ---XG+-N---- | /--* COMMA byref [000417] ---X-+-N---- | | \--* NULLCHECK byte [000416] -----+------ | | \--* LCL_VAR ref V02 loc0 [000265] -A-XG+------ \--* ASG byref [000264] D----+-N---- \--* LCL_VAR byref V13 tmp7 New refCnts for V13: refCnt = 1, refCntWtd = 2 New refCnts for V02: refCnt = 6, refCntWtd = 5 New refCnts for V02: refCnt = 7, refCntWtd = 6 [000226] ------------ * STMT void (IL ???... ???) [000424] ------------ | /--* CNS_INT byref 0 [000425] -A---+------ \--* ASG byref [000423] D------N---- \--* LCL_VAR byref V22 tmp16 New refCnts for V22: refCnt = 1, refCntWtd = 1 [000232] ------------ * STMT void (IL ???... ???) [000263] -----+------ | /--* LCL_VAR byref V13 tmp7 [000230] -A---+------ \--* ASG byref [000229] D----+-N---- \--* LCL_VAR byref V22 tmp16 New refCnts for V22: refCnt = 2, refCntWtd = 2 New refCnts for V13: refCnt = 2, refCntWtd = 4 [000237] ------------ * STMT void (IL ???... ???) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 [000428] -A---+------ \--* ASG byref [000426] D------N---- \--* LCL_VAR byref V20 tmp14 New refCnts for V20: refCnt = 2, refCntWtd = 2 New refCnts for V22: refCnt = 3, refCntWtd = 3 [000242] ------------ * STMT void (IL ???... ???) [000048] -----+------ | /--* LCL_VAR int V03 loc1 [000241] -A---+------ \--* ASG int [000240] D----+-N---- \--* LCL_VAR int V21 tmp15 New refCnts for V21: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 4, refCntWtd = 3.50 [000064] ------------ * STMT void (IL 0x041... ???) [000433] -------N---- | /--* LCL_VAR int V21 tmp15 [000434] -A--G------- | /--* ASG int [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 [000435] -A--G+------ \--* COMMA void [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 [000431] -A--G------- \--* ASG byref [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 New refCnts for V04: refCnt = 1, refCntWtd = 1 New refCnts for V18: refCnt = 1, refCntWtd = 1 New refCnts for V20: refCnt = 3, refCntWtd = 3 New refCnts for V04: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 1, refCntWtd = 1 New refCnts for V21: refCnt = 3, refCntWtd = 3 [000297] ------------ * STMT void (IL 0x042... ???) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 [000441] -A---------- | /--* ASG int [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 [000442] -A---+------ \--* COMMA void [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 [000438] -A---------- \--* ASG byref [000436] D------N---- \--* LCL_VAR byref V23 tmp17 New refCnts for V23: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 2, refCntWtd = 3 New refCnts for V24: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 5, refCntWtd = 6 [000289] ------------ * STMT void (IL 0x042... ???) [000288] -ACXG+------ \--* JTRUE void [000286] -----+------ | /--* CNS_INT int 0 [000287] JACXG+-N---- \--* EQ int [000280] -ACXG+------ \--* CALL int Span`1.TryCopyTo [000277] L----+------ | /--* ADDR byref [000278] ----G+-N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 [000465] -A--------L- this SETUP +--* ASG byref [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 [000461] -------N---- | /--* LCL_VAR int V24 tmp18 [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 [000460] *------N---- | | \--* IND int [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] [000459] ------------ | | \--* ADD byref [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 [000463] -A---+----L- arg1 SETUP +--* COMMA void [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 [000453] *------N---- | | | \--* IND byref [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] [000452] ------------ | | | \--* ADD byref [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 [000456] -A---------- | \--* COMMA void [000446] L----------- | | /--* ADDR byref [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 [000449] -A---------- | \--* ASG byref [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 [000469] L----------- arg1 in rdx \--* ADDR byref [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 New refCnts for V30: refCnt = 1, refCntWtd = 2 New refCnts for V18: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 2, refCntWtd = 2 New refCnts for V04: refCnt = 3, refCntWtd = 3 New refCnts for V29: refCnt = 1, refCntWtd = 2 New refCnts for V28: refCnt = 2, refCntWtd = 4 New refCnts for V29: refCnt = 2, refCntWtd = 4 New refCnts for V23: refCnt = 2, refCntWtd = 2 New refCnts for V29: refCnt = 3, refCntWtd = 6 New refCnts for V24: refCnt = 2, refCntWtd = 2 New refCnts for V30: refCnt = 2, refCntWtd = 4 New refCnts for V28: refCnt = 3, refCntWtd = 6 *** marking local variables in block BB08 (weight=1 ) [000076] ------------ * STMT void (IL 0x04A... ???) [000073] -----+------ | /--* LCL_VAR int V03 loc1 [000075] -A---+------ \--* ASG int [000074] D----+-N---- \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 5, refCntWtd = 4.50 *** marking local variables in block BB09 (weight=0 ) [000293] ------------ * STMT void (IL 0x042... ???) [000292] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort *** marking local variables in block BB10 (weight=0 ) [000204] ------------ * STMT void (IL ???... ???) [000203] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException *** marking local variables in block BB11 (weight=0 ) [000256] ------------ * STMT void (IL ???... ???) [000254] --CXG+------ \--* CALL void ThrowHelper.ThrowArgumentNullException [000253] -----+------ arg0 in rcx \--* CNS_INT int 2 *** marking local variables in block BB12 (weight=0 ) [000089] ------------ * STMT void (IL ???... ???) [000086] --C--+------ | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000085] -----+------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method [000088] -AC--+------ \--* ASG ref [000087] D----+-N---- \--* LCL_VAR ref V08 tmp2 New refCnts for V08: refCnt = 1, refCntWtd = 0 [000093] ------------ * STMT void (IL ???... ???) [000091] --CXG+------ \--* CALL void IOException..ctor [000160] --CXG+------ | /--* CALL ref SR.GetResourceString [000390] --CXG+------ | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE [000388] -----+------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 [000394] -ACXG-----L- arg0 SETUP | | +--* ASG ref [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 [000159] -----+------ arg1 in rdx | | \--* CNS_INT ref null [000400] -ACXG-----L- arg1 SETUP +--* ASG ref [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 [000090] -----+------ this in rcx \--* LCL_VAR ref V08 tmp2 New refCnts for V27: refCnt = 1, refCntWtd = 0 New refCnts for V26: refCnt = 1, refCntWtd = 0 New refCnts for V26: refCnt = 2, refCntWtd = 0 New refCnts for V27: refCnt = 2, refCntWtd = 0 New refCnts for V08: refCnt = 2, refCntWtd = 0 [000097] ------------ * STMT void (IL 0x038... ???) [000096] --CXG+------ \--* CALL help void HELPER.CORINFO_HELP_THROW [000094] -----+------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 New refCnts for V08: refCnt = 3, refCntWtd = 0 *** marking local variables in block BB13 (weight=1 ) [000343] ------------ * STMT void (IL ???... ???) [000334] --CXG+------ | /--* IND ref [000342] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000335] --CXG+------ | | \--* ADD byref [000336] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000338] #----+------ arg0 in rcx | | +--* IND long [000339] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000341] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000332] -ACXG+------ \--* ASG ref [000333] D----+-N---- \--* LCL_VAR ref V15 tmp9 New refCnts for V15: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB14 (weight=1 ) [000350] ------------ * STMT void (IL ???... ???) [000344] --CXG+------ \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000345] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000347] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000349] -----+------ arg2 in r8 \--* CNS_INT int 0 New refCnts for V15: refCnt = 2, refCntWtd = 2 New refCnts for V02: refCnt = 8, refCntWtd = 7 [000080] ------------ * STMT void (IL 0x05B...0x05C) [000079] -----+------ \--* RETURN int [000078] -----+------ \--* LCL_VAR int V05 loc3 New refCnts for V05: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB15 (weight=0 ) [000318] ------------ * STMT void (IL 0x04E... ???) [000330] --CXG+------ | /--* IND ref [000328] -----+------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] [000329] --CXG+------ | | \--* ADD byref [000327] H-CXG+------ | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE [000323] #----+------ arg0 in rcx | | +--* IND long [000322] -----+------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid [000324] -----+------ arg1 in rdx | | \--* CNS_INT int 327 [000317] -ACXG+------ \--* ASG ref [000316] D----+-N---- \--* LCL_VAR ref V15 tmp9 New refCnts for V15: refCnt = 3, refCntWtd = 2 *** marking local variables in block BB16 (weight=0 ) [000107] ------------ * STMT void (IL ???... ???) [000104] --CXG+------ \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return [000319] -----+------ this in rcx +--* LCL_VAR ref V15 tmp9 [000102] -----+------ arg1 in rdx +--* LCL_VAR ref V02 loc0 [000103] -----+------ arg2 in r8 \--* CNS_INT int 0 New refCnts for V15: refCnt = 4, refCntWtd = 2 New refCnts for V02: refCnt = 9, refCntWtd = 7 [000109] ------------ * STMT void (IL 0x05A... ???) [000108] -----+------ \--* RETFILT void New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V01: refCnt = 7, refCntWtd = 6 New refCnts for V01: refCnt = 8, refCntWtd = 8 *************** In optAddCopies() Trying to add a copy for V02 a local, avg_wtd = 0.39 Referenced in BB03, bbWeight is 1 , which is dominated by BB01 Referenced in BB04, bbWeight is 1 , which is dominated by BB01 Referenced in BB05, bbWeight is 0.50, which is dominated by BB01 Referenced in BB06, bbWeight is 0.50, which is dominated by BB01 Referenced in BB07, bbWeight is 1 , which is dominated by BB01 Referenced in BB14, bbWeight is 1 , which is dominated by BB01 Referenced in BB16, bbWeight is 0 , which is dominated by BB01 lvaGrabTemp returning 33 (V33 tmp27) (a long lifetime temp) called for optAddCopies. Finding the best place to insert the assignment V33=V02 New refCnts for V33: refCnt = 1, refCntWtd = 1 New refCnts for V33: refCnt = 2, refCntWtd = 2 Introducing a new copy for V02 [000496] ------------ /--* LCL_VAR ref V33 tmp27 [000497] -A---------- /--* ASG ref [000015] D----+-N---- | \--* LCL_VAR ref V02 loc0 [000016] -ACXG+------ * COMMA void [000013] --CXG+------ | /--* CALLV ind ref ArrayPool`1.Rent [000011] -----+------ this in rcx | | +--* LCL_VAR ref V09 tmp3 [000145] -----+------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 [000495] -ACXG------- \--* ASG ref [000494] D------N---- \--* LCL_VAR ref V33 tmp27 refCnt table for 'Read': V01 arg1 [ byref]: refCnt = 8, refCntWtd = 8 pref [rdx] V02 loc0 [ ref]: refCnt = 9, refCntWtd = 7 V17 tmp11 [ int]: refCnt = 5, refCntWtd = 6 V29 tmp23 [ byref]: refCnt = 3, refCntWtd = 6 V00 this [ ref]: refCnt = 3, refCntWtd = 3 pref [rcx] V03 loc1 [ int]: refCnt = 5, refCntWtd = 4.50 V13 tmp7 [ byref]: refCnt = 2, refCntWtd = 4 V30 tmp24 [ byref]: refCnt = 2, refCntWtd = 4 V09 tmp3 [ ref]: refCnt = 3, refCntWtd = 3 V20 tmp14 [ byref]: refCnt = 3, refCntWtd = 3 V22 tmp16 [ byref]: refCnt = 3, refCntWtd = 3 V21 tmp15 [ int]: refCnt = 3, refCntWtd = 3 V16 tmp10 [ byref]: refCnt = 2, refCntWtd = 3 V15 tmp9 [ ref]: refCnt = 4, refCntWtd = 2 V23 tmp17 [ byref]: refCnt = 2, refCntWtd = 2 V33 tmp27 [ ref]: refCnt = 2, refCntWtd = 2 V05 loc3 [ int]: refCnt = 2, refCntWtd = 2 V24 tmp18 [ int]: refCnt = 2, refCntWtd = 2 V06 tmp0 [ ref]: refCnt = 1, refCntWtd = 2 V10 tmp4 [ ubyte]: refCnt = 1, refCntWtd = 0.50 V08 tmp2 [ ref]: refCnt = 3, refCntWtd = 0 V26 tmp20 [ ref]: refCnt = 2, refCntWtd = 0 V27 tmp21 [ ref]: refCnt = 2, refCntWtd = 0 V28 tmp22 [struct]: refCnt = 3, refCntWtd = 6 V04 loc2 [struct]: refCnt = 3, refCntWtd = 3 V18 tmp12 [ byref]: refCnt = 2, refCntWtd = 2 V19 tmp13 [ int]: refCnt = 2, refCntWtd = 2 V31 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 V32 PSPSym [ long]: refCnt = 1, refCntWtd = 1 *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** In fgFindOperOrder() *************** In fgSetBlockOrder() The biggest BB has 32 tree nodes -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 23, 29) [000128] ------------ * STMT void (IL 0x000... ???) N013 ( 23, 29) [000140] --CXG------- | /--* IND ref N011 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000139] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000137] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000133] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000132] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000134] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 23, 29) [000127] -ACXG---R--- \--* ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 ***** BB02, stmt 3 ( 5, 4) [000010] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000129] ------------ | /--* LCL_VAR ref V09 tmp3 N003 ( 5, 4) [000009] -A------R--- \--* ASG ref N002 ( 3, 2) [000008] D------N---- \--* LCL_VAR ref V06 tmp0 ***** BB02, stmt 4 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 5 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 ***** BB03, stmt 6 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 7 ( 2, 6) [000052] ------------ * STMT void (IL 0x039...0x041) N004 ( 1, 1) [000411] ------------ | /--* CNS_INT int 0 N006 ( 1, 3) [000412] -A------R--- | /--* ASG int N005 ( 1, 1) [000410] D------N---- | | \--* LCL_VAR int V21 tmp15 N007 ( 2, 6) [000413] -A---------- \--* COMMA void N001 ( 1, 1) [000408] ------------ | /--* CNS_INT byref 0 N003 ( 1, 3) [000409] -A------R--- \--* ASG byref N002 ( 1, 1) [000407] D------N---- \--* LCL_VAR byref V20 tmp14 ***** BB04, stmt 8 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null N003 ( 3, 3) [000166] J------N---- \--* EQ int N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 9 ( 5, 4) [000175] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000172] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000174] -A------R--- \--* ASG ubyte N002 ( 3, 2) [000170] D------N---- \--* LCL_VAR int V10 tmp4 ***** BB05, stmt 10 ( 7, 7) [000201] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000200] ---X-------- \--* JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int N002 ( 3, 3) [000197] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 11 ( 7, 7) [000251] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000250] ---X-------- \--* JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int N002 ( 3, 3) [000246] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 12 ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] N005 ( 3, 3) [000420] ------------ | /--* ADD byref N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref N002 ( 2, 2) [000417] ---X---N---- | | \--* NULLCHECK byte N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 ***** BB07, stmt 13 ( 1, 3) [000226] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000424] ------------ | /--* CNS_INT byref 0 N003 ( 1, 3) [000425] -A------R--- \--* ASG byref N002 ( 1, 1) [000423] D------N---- \--* LCL_VAR byref V22 tmp16 ***** BB07, stmt 14 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 N003 ( 1, 3) [000230] -A------R--- \--* ASG byref N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 ***** BB07, stmt 15 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 N003 ( 1, 3) [000428] -A------R--- \--* ASG byref N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 ***** BB07, stmt 16 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 N003 ( 1, 3) [000241] -A------R--- \--* ASG int N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 ***** BB07, stmt 17 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V21 tmp15 N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 18 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 ***** BB07, stmt 19 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo N002 ( 3, 3) [000277] L----------- | /--* ADDR byref N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 20 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 N003 ( 5, 4) [000075] -A------R--- \--* ASG int N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 21 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 22 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 23 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 24 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 ***** BB12, stmt 25 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 ***** BB12, stmt 26 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 27 ( 27, 32) [000343] ------------ * STMT void (IL ???... ???) N013 ( 23, 29) [000334] --CXG------- | /--* IND ref N011 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000335] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000336] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000338] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000339] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000341] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 27, 32) [000332] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 28 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB14, stmt 29 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 30 ( 27, 32) [000318] ------------ * STMT void (IL 0x04E... ???) N013 ( 23, 29) [000330] --CXG------- | /--* IND ref N011 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000329] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000327] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000323] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000322] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000324] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 27, 32) [000317] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 31 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB16, stmt 32 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void ------------------------------------------------------------------------------------------------------------------- *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 17. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table index eTry, eHnd 0 :: - Try at BB03..BB12 [012..04E), Fault at BB15..BB16 [04E..05B) [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] *************** In SsaBuilder::ComputeDominators(BasicBlock** postOrder, int count, ...) *************** In SsaBuilder::InsertPhiFunctions() *************** In fgLocalVarLiveness() *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V01 } + ByrefExposed + GcHeap DEF(2)={ V17 V16} BB02 USE(1)={ V17 } + ByrefExposed + GcHeap DEF(4)={V02 V09 V33 V06} + ByrefExposed* + GcHeap* BB03 USE(3)={V02 V17 V00 } + ByrefExposed + GcHeap DEF(1)={ V03} + ByrefExposed* + GcHeap* BB04 USE(1)={V02 } DEF(2)={ V20 V21} BB05 USE(1)={V02 } DEF(1)={ V10} BB06 USE(2)={V02 V03} DEF(0)={ } BB07 USE(4)={V02 V17 V03 V16 } + ByrefExposed + GcHeap DEF(8)={ V29 V13 V30 V20 V22 V21 V23 V24} + ByrefExposed* + GcHeap* BB08 USE(1)={V03 } DEF(1)={ V05} BB09 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB10 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB11 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB12 USE(0)={ } + ByrefExposed + GcHeap DEF(3)={V08 V26 V27} + ByrefExposed* + GcHeap* BB13 USE(0)={ } + ByrefExposed + GcHeap DEF(1)={V15} + ByrefExposed* + GcHeap* BB14 USE(3)={V02 V15 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB15 USE(0)={ } + ByrefExposed + GcHeap DEF(1)={V15} + ByrefExposed* + GcHeap* BB16 USE(2)={V02 V15} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V01 V00 } + ByrefExposed + GcHeap OUT(3)={ V17 V00 V16} + ByrefExposed + GcHeap BB02 IN (3)={ V17 V00 V16} + ByrefExposed + GcHeap OUT(4)={V02 V17 V00 V16} + ByrefExposed + GcHeap BB03 IN (4)={V02 V17 V00 V16} + ByrefExposed + GcHeap OUT(4)={V02 V17 V03 V16} + ByrefExposed + GcHeap BB04 IN (4)={V02 V17 V03 V16} + ByrefExposed + GcHeap OUT(4)={V02 V17 V03 V16} + ByrefExposed + GcHeap BB05 IN (4)={V02 V17 V03 V16} + ByrefExposed + GcHeap OUT(4)={V02 V17 V03 V16} + ByrefExposed + GcHeap BB06 IN (4)={V02 V17 V03 V16} + ByrefExposed + GcHeap OUT(4)={V02 V17 V03 V16} + ByrefExposed + GcHeap BB07 IN (4)={V02 V17 V03 V16} + ByrefExposed + GcHeap OUT(2)={V02 V03 } + ByrefExposed + GcHeap BB08 IN (2)={V02 V03 } + ByrefExposed + GcHeap OUT(2)={V02 V05} + ByrefExposed + GcHeap BB09 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB10 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB11 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB12 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB13 IN (2)={V02 V05} + ByrefExposed + GcHeap OUT(3)={V02 V15 V05} + ByrefExposed + GcHeap BB14 IN (3)={V02 V15 V05} + ByrefExposed + GcHeap OUT(0)={ } BB15 IN (1)={V02 } + ByrefExposed + GcHeap OUT(2)={V02 V15} + ByrefExposed + GcHeap BB16 IN (2)={V02 V15} + ByrefExposed + GcHeap OUT(0)={ } Local V02 should not be enregistered because: live in/out of a handler top level assign removing stmt with no side effects Removing statement [000010] in BB02 as useless: ( 5, 4) [000010] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000129] ------------ | /--* LCL_VAR ref V09 tmp3 N003 ( 5, 4) [000009] -A------R--- \--* ASG ref N002 ( 3, 2) [000008] D------N---- \--* LCL_VAR ref V06 tmp0 New refCnts for V06: refCnt = 0, refCntWtd = 0 New refCnts for V09: refCnt = 2, refCntWtd = 2 Removing tree [000412] in BB04 as useless N004 ( 1, 1) [000411] ------------ /--* CNS_INT int 0 N006 ( 1, 3) [000412] -A------R--- * ASG int N005 ( 1, 1) [000410] D------N---- \--* LCL_VAR int V21 tmp15 New refCnts for V21: refCnt = 2, refCntWtd = 2 Removing tree [000409] in BB04 as useless N001 ( 1, 1) [000408] ------------ /--* CNS_INT byref 0 N003 ( 1, 3) [000409] -A------R--- * ASG byref N002 ( 1, 1) [000407] D------N---- \--* LCL_VAR byref V20 tmp14 New refCnts for V20: refCnt = 2, refCntWtd = 2 fgComputeLife modified tree: N002 ( 0, 0) [000412] ------------ /--* NOP void N003 ( 0, 0) [000413] ------------ * COMMA void N001 ( 0, 0) [000409] ------------ \--* NOP void top level assign removing stmt with no side effects Removing statement [000175] in BB05 as useless: ( 5, 4) [000175] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000172] ------------ | /--* CNS_INT int 0 N003 ( 5, 4) [000174] -A------R--- \--* ASG ubyte N002 ( 3, 2) [000170] D------N---- \--* LCL_VAR int V10 tmp4 New refCnts for V10: refCnt = 0, refCntWtd = 0 top level assign removing stmt with no side effects Removing statement [000226] in BB07 as useless: ( 1, 3) [000226] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000424] ------------ | /--* CNS_INT byref 0 N003 ( 1, 3) [000425] -A------R--- \--* ASG byref N002 ( 1, 1) [000423] D------N---- \--* LCL_VAR byref V22 tmp16 New refCnts for V22: refCnt = 2, refCntWtd = 2 In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal) Inserting phi functions: Inserting phi definition for ByrefExposed at start of BB15. Inserting phi definition for GcHeap at start of BB15. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 23, 29) [000128] ------------ * STMT void (IL 0x000... ???) N013 ( 23, 29) [000140] --CXG------- | /--* IND ref N011 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000139] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000137] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000133] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000132] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000134] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 23, 29) [000127] -ACXG---R--- \--* ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void N003 ( 0, 0) [000413] ------------ \--* COMMA void N001 ( 0, 0) [000409] ------------ \--* NOP void ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null N003 ( 3, 3) [000166] J------N---- \--* EQ int N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 7, 7) [000201] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000200] ---X-------- \--* JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int N002 ( 3, 3) [000197] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 7, 7) [000251] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000250] ---X-------- \--* JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int N002 ( 3, 3) [000246] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] N005 ( 3, 3) [000420] ------------ | /--* ADD byref N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref N002 ( 2, 2) [000417] ---X---N---- | | \--* NULLCHECK byte N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) N003 ( 1, 3) [000230] -A------R--- \--* ASG byref N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) N003 ( 1, 3) [000428] -A------R--- \--* ASG byref N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 N003 ( 1, 3) [000241] -A------R--- \--* ASG int N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V21 tmp15 u:2 (last use) N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo N002 ( 3, 3) [000277] L----------- | /--* ADDR byref N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) N003 ( 5, 4) [000075] -A------R--- \--* ASG int N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 27, 32) [000343] ------------ * STMT void (IL ???... ???) N013 ( 23, 29) [000334] --CXG------- | /--* IND ref N011 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000335] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000336] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000338] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000339] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000341] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 27, 32) [000332] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 27, 32) [000318] ------------ * STMT void (IL 0x04E... ???) N013 ( 23, 29) [000330] --CXG------- | /--* IND ref N011 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000329] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000327] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000323] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000322] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000324] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 27, 32) [000317] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void ------------------------------------------------------------------------------------------------------------------- *************** In optEarlyProp() After optEarlyProp: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 23, 29) [000128] ------------ * STMT void (IL 0x000... ???) N013 ( 23, 29) [000140] --CXG------- | /--* IND ref N011 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000139] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000137] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000133] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000132] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000134] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 23, 29) [000127] -ACXG---R--- \--* ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void N003 ( 0, 0) [000413] ------------ \--* COMMA void N001 ( 0, 0) [000409] ------------ \--* NOP void ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null N003 ( 3, 3) [000166] J------N---- \--* EQ int N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 7, 7) [000201] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000200] ---X-------- \--* JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int N002 ( 3, 3) [000197] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 7, 7) [000251] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000250] ---X-------- \--* JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int N002 ( 3, 3) [000246] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] N005 ( 3, 3) [000420] ------------ | /--* ADD byref N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref N002 ( 2, 2) [000417] ---X---N---- | | \--* NULLCHECK byte N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) N003 ( 1, 3) [000230] -A------R--- \--* ASG byref N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) N003 ( 1, 3) [000428] -A------R--- \--* ASG byref N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 N003 ( 1, 3) [000241] -A------R--- \--* ASG int N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V21 tmp15 u:2 (last use) N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo N002 ( 3, 3) [000277] L----------- | /--* ADDR byref N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) N003 ( 5, 4) [000075] -A------R--- \--* ASG int N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 27, 32) [000343] ------------ * STMT void (IL ???... ???) N013 ( 23, 29) [000334] --CXG------- | /--* IND ref N011 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000335] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000336] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000338] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000339] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000341] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 27, 32) [000332] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 27, 32) [000318] ------------ * STMT void (IL 0x04E... ???) N013 ( 23, 29) [000330] --CXG------- | /--* IND ref N011 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000329] --CXG--N---- | | \--* ADD byref N010 ( 20, 23) [000327] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000323] #----------- arg0 in rcx | | +--* IND long N005 ( 3, 10) [000322] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000324] ------------ arg1 in rdx | | \--* CNS_INT int 327 N015 ( 27, 32) [000317] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void ------------------------------------------------------------------------------------------------------------------- *************** In fgValueNumber() Memory Initial Value in BB01 is: $81 The SSA definition for ByrefExposed (#2) at start of BB01 is $81 {InitVal($42)} The SSA definition for GcHeap (#2) at start of BB01 is $81 {InitVal($42)} ***** BB01, stmt 1 (before) N010 ( 4, 4) [000369] x----------- /--* IND int N008 ( 1, 1) [000367] ------------ | | /--* CNS_INT long 8 Fseq[_length] N009 ( 2, 2) [000368] -------N---- | \--* ADD byref N007 ( 1, 1) [000366] ------------ | \--* LCL_VAR byref V01 arg1 u:2 (last use) N012 ( 4, 4) [000370] -A------R--- /--* ASG int N011 ( 1, 1) [000365] D------N---- | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- * COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 N001 [000360] LCL_VAR V01 arg1 u:2 => $c0 {InitVal($41)} N002 [000361] CNS_INT 0 Fseq[_pointer] => $100 {LngCns: 0} N003 [000362] ADD => $140 {ADD($c0, $100)} N004 [000363] IND => N005 [000359] LCL_VAR V16 tmp10 d:2 => N006 [000364] ASG => N007 [000366] LCL_VAR V01 arg1 u:2 (last use) => $c0 {InitVal($41)} N008 [000367] CNS_INT 8 Fseq[_length] => $101 {LngCns: 8} N009 [000368] ADD => $141 {ADD($c0, $101)} N010 [000369] IND => N011 [000365] LCL_VAR V17 tmp11 d:2 => N012 [000370] ASG => N013 [000371] COMMA => ***** BB01, stmt 1 (after) N010 ( 4, 4) [000369] x----------- /--* IND int N008 ( 1, 1) [000367] ------------ | | /--* CNS_INT long 8 Fseq[_length] $101 N009 ( 2, 2) [000368] -------N---- | \--* ADD byref $141 N007 ( 1, 1) [000366] ------------ | \--* LCL_VAR byref V01 arg1 u:2 (last use) $c0 N012 ( 4, 4) [000370] -A------R--- /--* ASG int N011 ( 1, 1) [000365] D------N---- | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- * COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 $c0 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB02 is $81 {InitVal($42)} The SSA definition for GcHeap (#2) at start of BB02 is $81 {InitVal($42)} ***** BB02, stmt 2 (before) N013 ( 23, 29) [000140] --CXG------- /--* IND ref N011 ( 1, 4) [000138] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000139] --CXG--N---- | \--* ADD byref N010 ( 20, 23) [000137] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000133] #----------- arg0 in rcx | +--* IND long N005 ( 3, 10) [000132] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000134] ------------ arg1 in rdx | \--* CNS_INT int 327 N015 ( 23, 29) [000127] -ACXG---R--- * ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 N001 [000372] ARGPLACE => $280 {280} N002 [000374] ARGPLACE => $242 {242} N003 [000135] LIST => $2c0 {LIST($242, $0)} N004 [000136] LIST => $2c1 {LIST($280, $2c0)} N005 [000132] CNS_INT(h) 0x17dd3b1e7b0 cid/mid => $300 {Hnd const: 0x0000017DD3B1E7B0} VNForMapSelect($2, $300):ref returns $340 {$VN.ReadOnlyHeap[$300]} VNForMapSelect($2, $300):ref returns $340 {$VN.ReadOnlyHeap[$300]} N006 [000133] IND => $340 {$VN.ReadOnlyHeap[$300]} N007 [000134] CNS_INT 327 => $45 {IntCns 327} N008 [000375] LIST => $2c2 {LIST($45, $0)} N009 [000373] LIST => $2c3 {LIST($340, $2c2)} VN of ARGPLACE tree [000372] updated to $340 {$VN.ReadOnlyHeap[$300]} VN of ARGPLACE tree [000374] updated to $45 {IntCns 327} N003 [000135] LIST => $2c2 {LIST($45, $0)} N004 [000136] LIST => $2c3 {LIST($340, $2c2)} $341 = singleton exc set {HelperMultipleExc()} $341 = singleton exc set {HelperMultipleExc()} N010 [000137] CALL help => $143 {ValWithExc($142, $341)} N011 [000138] CNS_INT 888 Fseq[k__BackingField] => $46 {IntCns 888} N012 [000139] ADD => $145 {ValWithExc($144, $341)} VNApplySelectors: VNForHandle(Fseq[k__BackingField]) is $301, fieldType is ref VNForMapSelect($81, $301):ref returns $342 {$81[$301]} VNForMapSelect($342, $142):ref returns $343 {$342[$142]} N013 [000140] IND => N014 [000126] LCL_VAR V09 tmp3 d:2 => N015 [000127] ASG => ***** BB02, stmt 2 (after) N013 ( 23, 29) [000140] --CXG------- /--* IND ref N011 ( 1, 4) [000138] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000139] --CXG--N---- | \--* ADD byref $145 N010 ( 20, 23) [000137] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000133] #----------- arg0 in rcx | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | \--* CNS_INT int 327 $45 N015 ( 23, 29) [000127] -ACXG---R--- * ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 --------- ***** BB02, stmt 3 (before) N011 ( 3, 2) [000496] ------------ /--* LCL_VAR ref V33 tmp27 u:2 (last use) N013 ( 3, 3) [000497] -A------R--- /--* ASG ref N012 ( 1, 1) [000015] D------N---- | \--* LCL_VAR ref V02 loc0 d:2 N014 ( 29, 18) [000016] -ACXG------- * COMMA void N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 N001 [000376] ARGPLACE => $3c2 {3c2} N002 [000378] ARGPLACE => $243 {243} N003 [000014] LIST => $2c4 {LIST($243, $0)} N004 [000011] LCL_VAR V09 tmp3 u:2 (last use) => N005 [000145] LCL_VAR V17 tmp11 u:2 => N006 [000379] LIST => N007 [000377] LIST => VN of ARGPLACE tree [000378] updated to N003 [000014] LIST => fgCurMemoryVN[GcHeap] assigned by CALL at [000013] to VN: $3c4. N008 [000013] CALLV ind => $3c3 {3c3} N009 [000494] LCL_VAR V33 tmp27 d:2 => $3c3 {3c3} N010 [000495] ASG => $3c3 {3c3} N011 [000496] LCL_VAR V33 tmp27 u:2 (last use) => $3c3 {3c3} N012 [000015] LCL_VAR V02 loc0 d:2 => $3c3 {3c3} N013 [000497] ASG => $3c3 {3c3} N014 [000016] COMMA => $3c3 {3c3} ***** BB02, stmt 3 (after) N011 ( 3, 2) [000496] ------------ /--* LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 N013 ( 3, 3) [000497] -A------R--- /--* ASG ref $3c3 N012 ( 1, 1) [000015] D------N---- | \--* LCL_VAR ref V02 loc0 d:2 $3c3 N014 ( 29, 18) [000016] -ACXG------- * COMMA void $3c3 N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent $3c3 N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref $3c3 N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 $3c3 finish(BB02). Succ(BB03). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#3) at start of BB03 is $400 {400} The SSA definition for GcHeap (#4) at start of BB03 is $3c4 {3c4} ***** BB03, stmt 4 (before) N016 ( 24, 16) [000027] --CXG------- /--* CALLV ind int Stream.Read N008 ( 1, 1) [000019] ------------ this in rcx | +--* LCL_VAR ref V00 this u:2 (last use) N009 ( 1, 1) [000020] ------------ arg1 in rdx | +--* LCL_VAR ref V02 loc0 u:2 N010 ( 1, 1) [000150] ------------ arg3 in r9 | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | \--* CNS_INT int 0 N018 ( 24, 16) [000032] -ACXG---R--- * ASG int N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 N001 [000380] ARGPLACE => $3c7 {3c7} N002 [000382] ARGPLACE => $3c8 {3c8} N003 [000386] ARGPLACE => $244 {244} N004 [000384] ARGPLACE => $245 {245} N005 [000028] LIST => $2cb {LIST($245, $0)} N006 [000029] LIST => $2cc {LIST($244, $2cb)} N007 [000030] LIST => $2cd {LIST($3c8, $2cc)} N008 [000019] LCL_VAR V00 this u:2 (last use) => $80 {InitVal($40)} N009 [000020] LCL_VAR V02 loc0 u:2 => $3c3 {3c3} N010 [000150] LCL_VAR V17 tmp11 u:2 => N011 [000021] CNS_INT 0 => $40 {IntCns 0} N012 [000387] LIST => $2ce {LIST($40, $0)} N013 [000385] LIST => N014 [000383] LIST => N015 [000381] LIST => VN of ARGPLACE tree [000382] updated to $80 {InitVal($40)} VN of ARGPLACE tree [000386] updated to $3c3 {3c3} VN of ARGPLACE tree [000384] updated to $40 {IntCns 0} N005 [000028] LIST => $2ce {LIST($40, $0)} N006 [000029] LIST => $2d5 {LIST($3c3, $2ce)} N007 [000030] LIST => $2d6 {LIST($80, $2d5)} fgCurMemoryVN[GcHeap] assigned by CALL at [000027] to VN: $3c9. N016 [000027] CALLV ind => $246 {246} N017 [000031] LCL_VAR V03 loc1 d:2 => $246 {246} N018 [000032] ASG => $246 {246} ***** BB03, stmt 4 (after) N016 ( 24, 16) [000027] --CXG------- /--* CALLV ind int Stream.Read $246 N008 ( 1, 1) [000019] ------------ this in rcx | +--* LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ arg1 in rdx | +--* LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ arg3 in r9 | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | \--* CNS_INT int 0 $40 N018 ( 24, 16) [000032] -ACXG---R--- * ASG int $246 N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 $246 --------- ***** BB03, stmt 5 (before) N006 ( 7, 9) [000043] ------------ * JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 N001 [000034] LCL_VAR V03 loc1 u:2 => $246 {246} VNForCastOper(ulong, unsignedSrc) is $47 N002 [000035] CAST => $440 {Cast($246, $47)} N003 [000155] LCL_VAR V17 tmp11 u:2 => VNForCastOper(long) is $48 N004 [000041] CAST => N005 [000042] GT => ***** BB03, stmt 5 (after) N006 ( 7, 9) [000043] ------------ * JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint $440 N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 $246 finish(BB03). Succ(BB04). Not yet completed. All preds complete, adding to allDone. Succ(BB12). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB12 is $401 {401} The SSA definition for GcHeap (#12) at start of BB12 is $3c9 {3c9} ***** BB12, stmt 21 (before) N005 ( 17, 16) [000086] --C--------- /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N003 ( 3, 10) [000085] ------------ arg0 in rcx | \--* CNS_INT(h) long 0x17dd3b22ac8 method N007 ( 21, 19) [000088] -AC-----R--- * ASG ref N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 N001 [000492] ARGPLACE => $281 {281} N002 [000491] LIST => $2d7 {LIST($281, $0)} N003 [000085] CNS_INT(h) 0x17dd3b22ac8 method => $302 {Hnd const: 0x0000017DD3B22AC8} N004 [000493] LIST => $2d8 {LIST($302, $0)} VN of ARGPLACE tree [000492] updated to $302 {Hnd const: 0x0000017DD3B22AC8} N002 [000491] LIST => $2d8 {LIST($302, $0)} N005 [000086] CALL help => $346 {JitNew($302, $3ca)} N006 [000087] LCL_VAR V08 tmp2 d:2 => $346 {JitNew($302, $3ca)} N007 [000088] ASG => $346 {JitNew($302, $3ca)} ***** BB12, stmt 21 (after) N005 ( 17, 16) [000086] --C--------- /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 N003 ( 3, 10) [000085] ------------ arg0 in rcx | \--* CNS_INT(h) long 0x17dd3b22ac8 method $302 N007 ( 21, 19) [000088] -AC-----R--- * ASG ref $346 N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 $346 --------- ***** BB12, stmt 22 (before) N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 N001 [000403] ARGPLACE => $3cc {3cc} N002 [000391] ARGPLACE => $248 {248} N003 [000389] LIST => $2d9 {LIST($248, $0)} N004 [000388] CNS_INT 0xE904 => $49 {IntCns 0xE904} N005 [000392] LIST => $2da {LIST($49, $0)} VN of ARGPLACE tree [000391] updated to $49 {IntCns 0xE904} N003 [000389] LIST => $2da {LIST($49, $0)} $341 = singleton exc set {HelperMultipleExc()} $341 = singleton exc set {HelperMultipleExc()} fgCurMemoryVN[GcHeap] assigned by HELPER - modifies heap at [000390] to VN: $3ce. N006 [000390] CALL help => $347 {ValWithExc($3cd, $341)} N007 [000393] LCL_VAR V26 tmp20 d:2 => $3cd {3cd} N008 [000394] ASG => $347 {ValWithExc($3cd, $341)} N009 [000397] ARGPLACE => $3d0 {3d0} N010 [000161] LIST => $2db {LIST($3d0, $0)} N011 [000162] LIST => $2dd {ValWithExc($2dc, $341)} N012 [000395] LCL_VAR V26 tmp20 u:2 (last use) => $3cd {3cd} N013 [000159] CNS_INT null => $VN.Null N014 [000398] LIST => $2de {LIST($0, $0)} N015 [000396] LIST => $2df {LIST($3cd, $2de)} VN of ARGPLACE tree [000397] updated to $VN.Null N010 [000161] LIST => $2de {LIST($0, $0)} N011 [000162] LIST => $2e0 {ValWithExc($2df, $341)} fgCurMemoryVN[GcHeap] assigned by CALL at [000160] to VN: $3d2. N016 [000160] CALL => $3d1 {3d1} N017 [000399] LCL_VAR V27 tmp21 d:2 => $3d1 {3d1} N018 [000400] ASG => $3d1 {3d1} N019 [000092] LIST => $2e1 {LIST($3d1, $0)} N020 [000401] LCL_VAR V27 tmp21 u:2 (last use) => $3d1 {3d1} N021 [000090] LCL_VAR V08 tmp2 u:2 => $346 {JitNew($302, $3ca)} N022 [000404] LIST => $2e2 {LIST($346, $0)} N023 [000402] LIST => $2e3 {LIST($3d1, $2e2)} fgCurMemoryVN[GcHeap] assigned by CALL at [000091] to VN: $3d4. N024 [000091] CALL => $VN.Void ***** BB12, stmt 22 (after) N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString $3d1 N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 $49 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref $347 N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 $3cd N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null $VN.Null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref $3d1 N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 $3d1 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 $346 --------- ***** BB12, stmt 23 (before) N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) N001 [000405] ARGPLACE => $3d5 {3d5} N002 [000095] LIST => $2e4 {LIST($3d5, $0)} N003 [000094] LCL_VAR V08 tmp2 u:2 (last use) => $346 {JitNew($302, $3ca)} N004 [000406] LIST => $2e2 {LIST($346, $0)} VN of ARGPLACE tree [000405] updated to $346 {JitNew($302, $3ca)} N002 [000095] LIST => $2e2 {LIST($346, $0)} $341 = singleton exc set {HelperMultipleExc()} $341 = singleton exc set {HelperMultipleExc()} N005 [000096] CALL help => $348 {ValWithExc($3, $341)} ***** BB12, stmt 23 (after) N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) $346 finish(BB12). Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB04 is $401 {401} The SSA definition for GcHeap (#12) at start of BB04 is $3c9 {3c9} ***** BB04, stmt 6 (before) N002 ( 0, 0) [000412] ------------ /--* NOP void N003 ( 0, 0) [000413] ------------ * COMMA void N001 ( 0, 0) [000409] ------------ \--* NOP void N001 [000409] NOP => $4c0 {4c0} N002 [000412] NOP => $4c1 {4c1} N003 [000413] COMMA => $4c1 {4c1} ***** BB04, stmt 6 (after) N002 ( 0, 0) [000412] ------------ /--* NOP void $4c1 N003 ( 0, 0) [000413] ------------ * COMMA void $4c1 N001 ( 0, 0) [000409] ------------ \--* NOP void $4c0 --------- ***** BB04, stmt 7 (before) N004 ( 5, 5) [000167] ------------ * JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null N003 ( 3, 3) [000166] J------N---- \--* EQ int N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 N001 [000046] LCL_VAR V02 loc0 u:2 => $3c3 {3c3} N002 [000165] CNS_INT null => $VN.Null N003 [000166] EQ => $482 {EQ($3c3, $0)} ***** BB04, stmt 7 (after) N004 ( 5, 5) [000167] ------------ * JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null $VN.Null N003 ( 3, 3) [000166] J------N---- \--* EQ int $482 N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 finish(BB04). Succ(BB05). Not yet completed. All preds complete, adding to allDone. Succ(BB11). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB11 is $401 {401} The SSA definition for GcHeap (#12) at start of BB11 is $3c9 {3c9} ***** BB11, stmt 20 (before) N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 N001 [000414] ARGPLACE => $249 {249} N002 [000255] LIST => $2e5 {LIST($249, $0)} N003 [000253] CNS_INT 2 => $4a {IntCns 2} N004 [000415] LIST => $2e6 {LIST($4a, $0)} VN of ARGPLACE tree [000414] updated to $4a {IntCns 2} N002 [000255] LIST => $2e6 {LIST($4a, $0)} fgCurMemoryVN[GcHeap] assigned by CALL at [000254] to VN: $3d6. N005 [000254] CALL => $VN.Void ***** BB11, stmt 20 (after) N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 $4a finish(BB11). Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB05 is $401 {401} The SSA definition for GcHeap (#12) at start of BB05 is $3c9 {3c9} ***** BB05, stmt 8 (before) N005 ( 7, 7) [000200] ---X-------- * JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int N002 ( 3, 3) [000197] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 N001 [000196] LCL_VAR V02 loc0 u:2 => $3c3 {3c3} N002 [000197] ARR_LENGTH => $500 {ARR_LENGTH($3c3)} N003 [000195] CNS_INT 0 => $40 {IntCns 0} N004 [000199] LT => $483 {LT_UN($500, $40)} ***** BB05, stmt 8 (after) N005 ( 7, 7) [000200] ---X-------- * JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int $483 N002 ( 3, 3) [000197] ---X-------- \--* ARR_LENGTH int $500 N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 finish(BB05). Succ(BB06). Not yet completed. All preds complete, adding to allDone. Succ(BB10). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB06 is $401 {401} The SSA definition for GcHeap (#12) at start of BB06 is $3c9 {3c9} ***** BB06, stmt 9 (before) N005 ( 7, 7) [000250] ---X-------- * JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int N002 ( 3, 3) [000246] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 N001 [000245] LCL_VAR V02 loc0 u:2 => $3c3 {3c3} N002 [000246] ARR_LENGTH => $500 {ARR_LENGTH($3c3)} N003 [000244] LCL_VAR V03 loc1 u:2 => $246 {246} N004 [000249] LT => $484 {LT_UN($500, $246)} ***** BB06, stmt 9 (after) N005 ( 7, 7) [000250] ---X-------- * JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int $484 N002 ( 3, 3) [000246] ---X-------- \--* ARR_LENGTH int $500 N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 finish(BB06). Succ(BB07). Not yet completed. All preds complete, adding to allDone. Succ(BB10). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB10 is $401 {401} The SSA definition for GcHeap (#12) at start of BB10 is $3c9 {3c9} ***** BB10, stmt 19 (before) N001 ( 14, 5) [000203] --CXG------- * CALL void ThrowHelper.ThrowArgumentOutOfRangeException fgCurMemoryVN[GcHeap] assigned by CALL at [000203] to VN: $3d7. N001 [000203] CALL => $VN.Void ***** BB10, stmt 19 (after) N001 ( 14, 5) [000203] --CXG------- * CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void finish(BB10). Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#11) at start of BB07 is $401 {401} The SSA definition for GcHeap (#12) at start of BB07 is $3c9 {3c9} ***** BB07, stmt 10 (before) N004 ( 1, 1) [000419] ------------ /--* CNS_INT long 16 field offset Fseq[m_arrayData] N005 ( 3, 3) [000420] ------------ /--* ADD byref N003 ( 1, 1) [000418] ------------ | \--* LCL_VAR ref V02 loc0 u:2 N006 ( 5, 5) [000421] ---XG--N---- /--* COMMA byref N002 ( 2, 2) [000417] ---X---N---- | \--* NULLCHECK byte N001 ( 1, 1) [000416] ------------ | \--* LCL_VAR ref V02 loc0 u:2 N008 ( 5, 5) [000265] -A-XG---R--- * ASG byref N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 N001 [000416] LCL_VAR V02 loc0 u:2 => $3c3 {3c3} $349 = singleton exc set {NullPtrExc($3c3)} $349 = singleton exc set {NullPtrExc($3c3)} N002 [000417] NULLCHECK => $34a {ValWithExc($3, $349)} N003 [000418] LCL_VAR V02 loc0 u:2 => $3c3 {3c3} N004 [000419] CNS_INT 16 field offset Fseq[m_arrayData] => $102 {LngCns: 16} N005 [000420] ADD => $146 {ADD($102, $3c3)} N006 [000421] COMMA => $147 {ValWithExc($146, $349)} N007 [000264] LCL_VAR V13 tmp7 d:2 => $146 {ADD($102, $3c3)} N008 [000265] ASG => $147 {ValWithExc($146, $349)} ***** BB07, stmt 10 (after) N004 ( 1, 1) [000419] ------------ /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N005 ( 3, 3) [000420] ------------ /--* ADD byref $146 N003 ( 1, 1) [000418] ------------ | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N006 ( 5, 5) [000421] ---XG--N---- /--* COMMA byref $147 N002 ( 2, 2) [000417] ---X---N---- | \--* NULLCHECK byte $34a N001 ( 1, 1) [000416] ------------ | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N008 ( 5, 5) [000265] -A-XG---R--- * ASG byref $147 N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 --------- ***** BB07, stmt 11 (before) N001 ( 1, 1) [000263] ------------ /--* LCL_VAR byref V13 tmp7 u:2 (last use) N003 ( 1, 3) [000230] -A------R--- * ASG byref N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 N001 [000263] LCL_VAR V13 tmp7 u:2 (last use) => $146 {ADD($102, $3c3)} N002 [000229] LCL_VAR V22 tmp16 d:2 => $146 {ADD($102, $3c3)} N003 [000230] ASG => $146 {ADD($102, $3c3)} ***** BB07, stmt 11 (after) N001 ( 1, 1) [000263] ------------ /--* LCL_VAR byref V13 tmp7 u:2 (last use) $146 N003 ( 1, 3) [000230] -A------R--- * ASG byref $146 N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 $146 --------- ***** BB07, stmt 12 (before) N001 ( 1, 1) [000427] -------N---- /--* LCL_VAR byref V22 tmp16 u:2 (last use) N003 ( 1, 3) [000428] -A------R--- * ASG byref N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 N001 [000427] LCL_VAR V22 tmp16 u:2 (last use) => $146 {ADD($102, $3c3)} N002 [000426] LCL_VAR V20 tmp14 d:2 => $146 {ADD($102, $3c3)} N003 [000428] ASG => $146 {ADD($102, $3c3)} ***** BB07, stmt 12 (after) N001 ( 1, 1) [000427] -------N---- /--* LCL_VAR byref V22 tmp16 u:2 (last use) $146 N003 ( 1, 3) [000428] -A------R--- * ASG byref $146 N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 $146 --------- ***** BB07, stmt 13 (before) N001 ( 1, 1) [000048] ------------ /--* LCL_VAR int V03 loc1 u:2 N003 ( 1, 3) [000241] -A------R--- * ASG int N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 N001 [000048] LCL_VAR V03 loc1 u:2 => $246 {246} N002 [000240] LCL_VAR V21 tmp15 d:2 => $246 {246} N003 [000241] ASG => $246 {246} ***** BB07, stmt 13 (after) N001 ( 1, 1) [000048] ------------ /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 1, 3) [000241] -A------R--- * ASG int $246 N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 $246 --------- ***** BB07, stmt 14 (before) N004 ( 1, 1) [000433] -------N---- /--* LCL_VAR int V21 tmp15 u:2 (last use) N006 ( 5, 4) [000434] -A--G---R--- /--* ASG int N005 ( 3, 2) [000432] D---G--N---- | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- * COMMA void N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 N001 [000430] LCL_VAR V20 tmp14 u:2 (last use) => $146 {ADD($102, $3c3)} fgCurMemoryVN[ByrefExposed] assigned by local assign at [000431] to VN: $407. N003 [000431] ASG => $146 {ADD($102, $3c3)} N004 [000433] LCL_VAR V21 tmp15 u:2 (last use) => $246 {246} fgCurMemoryVN[ByrefExposed] assigned by local assign at [000434] to VN: $408. N006 [000434] ASG => $246 {246} N007 [000435] COMMA => $246 {246} ***** BB07, stmt 14 (after) N004 ( 1, 1) [000433] -------N---- /--* LCL_VAR int V21 tmp15 u:2 (last use) $246 N006 ( 5, 4) [000434] -A--G---R--- /--* ASG int $246 N005 ( 3, 2) [000432] D---G--N---- | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- * COMMA void $246 N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) $146 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref $146 N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 --------- ***** BB07, stmt 15 (before) N004 ( 1, 1) [000440] -------N---- /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- /--* ASG int N005 ( 3, 2) [000439] D------N---- | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- * COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 N001 [000437] LCL_VAR V16 tmp10 u:2 (last use) => N002 [000436] LCL_VAR V23 tmp17 d:2 => N003 [000438] ASG => N004 [000440] LCL_VAR V17 tmp11 u:2 (last use) => N005 [000439] LCL_VAR V24 tmp18 d:2 => N006 [000441] ASG => N007 [000442] COMMA => ***** BB07, stmt 15 (after) N004 ( 1, 1) [000440] -------N---- /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- /--* ASG int N005 ( 3, 2) [000439] D------N---- | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- * COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 --------- ***** BB07, stmt 16 (before) N032 ( 47, 35) [000288] -ACXG------- * JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo N002 ( 3, 3) [000277] L----------- | /--* ADDR byref N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 N001 [000278] LCL_VAR V04 loc2 byref V04._pointer (offs=0x00) -> V18 tmp12 int V04._length (offs=0x08) -> V19 tmp13 => $540 {ByrefExposedLoad($4c, $148, $408)} N002 [000277] ADDR => $1c6 {1c6} N003 [000464] LCL_VAR V30 tmp24 d:2 => $1c6 {1c6} N004 [000465] ASG => $1c6 {1c6} N005 [000447] LCL_VAR V28 tmp22 => $541 {ByrefExposedLoad($4c, $149, $408)} N006 [000446] ADDR => $1c8 {1c8} N007 [000448] LCL_VAR V29 tmp23 d:2 => $1c8 {1c8} N008 [000449] ASG => $1c8 {1c8} N009 [000450] LCL_VAR V29 tmp23 u:2 => $1c8 {1c8} N010 [000451] CNS_INT 0 Fseq[_pointer] => $100 {LngCns: 0} N011 [000452] ADD => $14a {ADD($100, $1c8)} N013 [000454] LCL_VAR V23 tmp17 u:2 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000455] to VN: $3d8. N014 [000455] ASG => $VN.Void N015 [000456] COMMA => $VN.Void N016 [000457] LCL_VAR V29 tmp23 u:2 (last use) => $1c8 {1c8} N017 [000458] CNS_INT 8 Fseq[_length] => $101 {LngCns: 8} N018 [000459] ADD => $14b {ADD($101, $1c8)} N020 [000461] LCL_VAR V24 tmp18 u:2 (last use) => fgCurMemoryVN[GcHeap] assigned by assign-of-IND at [000462] to VN: $3d9. N021 [000462] ASG => $VN.Void N022 [000463] COMMA => $VN.Void N023 [000283] LIST => $2e7 {LIST($3, $0)} N024 [000466] LCL_VAR V30 tmp24 u:2 (last use) => $1c6 {1c6} N025 [000468] LCL_VAR V28 tmp22 => $542 {ByrefExposedLoad($4c, $149, $40a)} N026 [000469] ADDR => $1ca {1ca} N027 [000470] LIST => $2e8 {LIST($1ca, $0)} N028 [000467] LIST => $2e9 {LIST($1c6, $2e8)} fgCurMemoryVN[GcHeap] assigned by CALL at [000280] to VN: $3da. N029 [000280] CALL => $24c {24c} N030 [000286] CNS_INT 0 => $40 {IntCns 0} N031 [000287] EQ => $485 {EQ($24c, $40)} ***** BB07, stmt 16 (after) N032 ( 47, 35) [000288] -ACXG------- * JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 $40 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int $485 N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo $24c N002 ( 3, 3) [000277] L----------- | /--* ADDR byref $1c6 N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 $540 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref $1c6 N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 $1c6 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 $VN.Void N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref $14b N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 $VN.Void N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref $14a N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 $1c8 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void $VN.Void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref $1c8 N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 $541 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref $1c8 N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 $1c8 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref $1ca N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 $542 finish(BB07). Succ(BB08). Not yet completed. All preds complete, adding to allDone. Succ(BB09). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#13) at start of BB09 is $40b {40b} The SSA definition for GcHeap (#14) at start of BB09 is $3da {3da} ***** BB09, stmt 18 (before) N001 ( 14, 5) [000292] --CXG------- * CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort fgCurMemoryVN[GcHeap] assigned by CALL at [000292] to VN: $3db. N001 [000292] CALL => $VN.Void ***** BB09, stmt 18 (after) N001 ( 14, 5) [000292] --CXG------- * CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void finish(BB09). Succ(BB15). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#13) at start of BB08 is $40b {40b} The SSA definition for GcHeap (#14) at start of BB08 is $3da {3da} ***** BB08, stmt 17 (before) N001 ( 1, 1) [000073] ------------ /--* LCL_VAR int V03 loc1 u:2 (last use) N003 ( 5, 4) [000075] -A------R--- * ASG int N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 N001 [000073] LCL_VAR V03 loc1 u:2 (last use) => $246 {246} N002 [000074] LCL_VAR V05 loc3 d:2 => $246 {246} N003 [000075] ASG => $246 {246} ***** BB08, stmt 17 (after) N001 ( 1, 1) [000073] ------------ /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N003 ( 5, 4) [000075] -A------R--- * ASG int $246 N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 $246 finish(BB08). Succ(BB13). Not yet completed. All preds complete, adding to allDone. Succ(BB15). Not yet completed. All preds complete, adding to allDone. Building phi application: $4e = SSA# 25. Building phi application: $4f = SSA# 23. Building phi application: $34b = phi($4f, $4e). Building phi application: $47 = SSA# 21. Building phi application: $34c = phi($47, $34b). Building phi application: $50 = SSA# 19. Building phi application: $34d = phi($50, $34c). Building phi application: $51 = SSA# 13. Building phi application: $34e = phi($51, $34d). Building phi application: $52 = SSA# 11. Building phi application: $34f = phi($52, $34e). Building phi application: $53 = SSA# 3. Building phi application: $350 = phi($53, $34f). The SSA definition for ByrefExposed (#5) at start of BB15 is $351 {PhiMemoryDef($303, $350)} Building phi application: $54 = SSA# 26. Building phi application: $55 = SSA# 24. Building phi application: $352 = phi($55, $54). Building phi application: $56 = SSA# 22. Building phi application: $353 = phi($56, $352). Building phi application: $57 = SSA# 20. Building phi application: $354 = phi($57, $353). Building phi application: $43 = SSA# 14. Building phi application: $355 = phi($43, $354). Building phi application: $58 = SSA# 12. Building phi application: $356 = phi($58, $355). Building phi application: $4b = SSA# 4. Building phi application: $357 = phi($4b, $356). The SSA definition for GcHeap (#6) at start of BB15 is $358 {PhiMemoryDef($303, $357)} ***** BB15, stmt 27 (before) N013 ( 23, 29) [000330] --CXG------- /--* IND ref N011 ( 1, 4) [000328] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000329] --CXG--N---- | \--* ADD byref N010 ( 20, 23) [000327] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000323] #----------- arg0 in rcx | +--* IND long N005 ( 3, 10) [000322] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000324] ------------ arg1 in rdx | \--* CNS_INT int 327 N015 ( 27, 32) [000317] -ACXG---R--- * ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 N001 [000481] ARGPLACE => $282 {282} N002 [000483] ARGPLACE => $24e {24e} N003 [000325] LIST => $2ea {LIST($24e, $0)} N004 [000326] LIST => $2eb {LIST($282, $2ea)} N005 [000322] CNS_INT(h) 0x17dd3b1e7b0 cid/mid => $300 {Hnd const: 0x0000017DD3B1E7B0} VNForMapSelect($2, $300):ref returns $340 {$VN.ReadOnlyHeap[$300]} VNForMapSelect($2, $300):ref returns $340 {$VN.ReadOnlyHeap[$300]} N006 [000323] IND => $340 {$VN.ReadOnlyHeap[$300]} N007 [000324] CNS_INT 327 => $45 {IntCns 327} N008 [000484] LIST => $2c2 {LIST($45, $0)} N009 [000482] LIST => $2c3 {LIST($340, $2c2)} VN of ARGPLACE tree [000481] updated to $340 {$VN.ReadOnlyHeap[$300]} VN of ARGPLACE tree [000483] updated to $45 {IntCns 327} N003 [000325] LIST => $2c2 {LIST($45, $0)} N004 [000326] LIST => $2c3 {LIST($340, $2c2)} $341 = singleton exc set {HelperMultipleExc()} $341 = singleton exc set {HelperMultipleExc()} N010 [000327] CALL help => $143 {ValWithExc($142, $341)} N011 [000328] CNS_INT 888 Fseq[k__BackingField] => $46 {IntCns 888} N012 [000329] ADD => $145 {ValWithExc($144, $341)} VNApplySelectors: VNForHandle(Fseq[k__BackingField]) is $301, fieldType is ref VNForMapSelect($358, $301):ref returns $35b {$358[$301]} VNForMapSelect($35b, $142):ref returns $35c {$35b[$142]} N013 [000330] IND => N014 [000316] LCL_VAR V15 tmp9 d:2 => N015 [000317] ASG => ***** BB15, stmt 27 (after) N013 ( 23, 29) [000330] --CXG------- /--* IND ref N011 ( 1, 4) [000328] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000329] --CXG--N---- | \--* ADD byref $145 N010 ( 20, 23) [000327] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000323] #----------- arg0 in rcx | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | \--* CNS_INT int 327 $45 N015 ( 27, 32) [000317] -ACXG---R--- * ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 finish(BB15). Succ(BB16). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#7) at start of BB16 is $351 {PhiMemoryDef($303, $350)} The SSA definition for GcHeap (#8) at start of BB16 is $358 {PhiMemoryDef($303, $357)} ***** BB16, stmt 28 (before) N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 N001 [000485] ARGPLACE => $3de {3de} N002 [000487] ARGPLACE => $3df {3df} N003 [000489] ARGPLACE => $24f {24f} N004 [000105] LIST => $2ec {LIST($24f, $0)} N005 [000106] LIST => $2ed {LIST($3df, $2ec)} N006 [000319] LCL_VAR V15 tmp9 u:2 (last use) => N007 [000102] LCL_VAR V02 loc0 u:2 (last use) => $3c3 {3c3} N008 [000103] CNS_INT 0 => $40 {IntCns 0} N009 [000490] LIST => $2ce {LIST($40, $0)} N010 [000488] LIST => $2d5 {LIST($3c3, $2ce)} N011 [000486] LIST => VN of ARGPLACE tree [000487] updated to VN of ARGPLACE tree [000489] updated to $3c3 {3c3} N004 [000105] LIST => $2f0 {LIST($3c3, $0)} N005 [000106] LIST => fgCurMemoryVN[GcHeap] assigned by CALL at [000104] to VN: $3e0. N012 [000104] CALL nullcheck => $VN.Void ***** BB16, stmt 28 (after) N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 $40 --------- ***** BB16, stmt 29 (before) N001 ( 0, 0) [000108] ------------ * RETFILT void N001 [000108] RETFILT => $4c2 {4c2} ***** BB16, stmt 29 (after) N001 ( 0, 0) [000108] ------------ * RETFILT void $4c2 finish(BB16). The SSA definition for ByrefExposed (#13) at start of BB13 is $40b {40b} The SSA definition for GcHeap (#14) at start of BB13 is $3da {3da} ***** BB13, stmt 24 (before) N013 ( 23, 29) [000334] --CXG------- /--* IND ref N011 ( 1, 4) [000342] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] N012 ( 21, 27) [000335] --CXG--N---- | \--* ADD byref N010 ( 20, 23) [000336] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE N006 ( 5, 12) [000338] #----------- arg0 in rcx | +--* IND long N005 ( 3, 10) [000339] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid N007 ( 1, 4) [000341] ------------ arg1 in rdx | \--* CNS_INT int 327 N015 ( 27, 32) [000332] -ACXG---R--- * ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 N001 [000471] ARGPLACE => $283 {283} N002 [000473] ARGPLACE => $250 {250} N003 [000340] LIST => $2f3 {LIST($250, $0)} N004 [000337] LIST => $2f4 {LIST($283, $2f3)} N005 [000339] CNS_INT(h) 0x17dd3b1e7b0 cid/mid => $300 {Hnd const: 0x0000017DD3B1E7B0} VNForMapSelect($2, $300):ref returns $340 {$VN.ReadOnlyHeap[$300]} VNForMapSelect($2, $300):ref returns $340 {$VN.ReadOnlyHeap[$300]} N006 [000338] IND => $340 {$VN.ReadOnlyHeap[$300]} N007 [000341] CNS_INT 327 => $45 {IntCns 327} N008 [000474] LIST => $2c2 {LIST($45, $0)} N009 [000472] LIST => $2c3 {LIST($340, $2c2)} VN of ARGPLACE tree [000471] updated to $340 {$VN.ReadOnlyHeap[$300]} VN of ARGPLACE tree [000473] updated to $45 {IntCns 327} N003 [000340] LIST => $2c2 {LIST($45, $0)} N004 [000337] LIST => $2c3 {LIST($340, $2c2)} $341 = singleton exc set {HelperMultipleExc()} $341 = singleton exc set {HelperMultipleExc()} N010 [000336] CALL help => $143 {ValWithExc($142, $341)} N011 [000342] CNS_INT 888 Fseq[k__BackingField] => $46 {IntCns 888} N012 [000335] ADD => $145 {ValWithExc($144, $341)} VNApplySelectors: VNForHandle(Fseq[k__BackingField]) is $301, fieldType is ref VNForMapSelect($3da, $301):ref returns $35f {$3da[$301]} VNForMapSelect($35f, $142):ref returns $360 {$35f[$142]} N013 [000334] IND => N014 [000333] LCL_VAR V15 tmp9 d:3 => N015 [000332] ASG => ***** BB13, stmt 24 (after) N013 ( 23, 29) [000334] --CXG------- /--* IND ref N011 ( 1, 4) [000342] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000335] --CXG--N---- | \--* ADD byref $145 N010 ( 20, 23) [000336] H-CXG------- | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000338] #----------- arg0 in rcx | +--* IND long $340 N005 ( 3, 10) [000339] ------------ | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000341] ------------ arg1 in rdx | \--* CNS_INT int 327 $45 N015 ( 27, 32) [000332] -ACXG---R--- * ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 finish(BB13). Succ(BB14). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#15) at start of BB14 is $40b {40b} The SSA definition for GcHeap (#16) at start of BB14 is $3da {3da} ***** BB14, stmt 25 (before) N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 N001 [000475] ARGPLACE => $3e3 {3e3} N002 [000477] ARGPLACE => $3e4 {3e4} N003 [000479] ARGPLACE => $251 {251} N004 [000348] LIST => $2f5 {LIST($251, $0)} N005 [000346] LIST => $2f6 {LIST($3e4, $2f5)} N006 [000345] LCL_VAR V15 tmp9 u:3 (last use) => N007 [000347] LCL_VAR V02 loc0 u:2 (last use) => $3c3 {3c3} N008 [000349] CNS_INT 0 => $40 {IntCns 0} N009 [000480] LIST => $2ce {LIST($40, $0)} N010 [000478] LIST => $2d5 {LIST($3c3, $2ce)} N011 [000476] LIST => VN of ARGPLACE tree [000477] updated to VN of ARGPLACE tree [000479] updated to $3c3 {3c3} N004 [000348] LIST => $2f0 {LIST($3c3, $0)} N005 [000346] LIST => fgCurMemoryVN[GcHeap] assigned by CALL at [000344] to VN: $3e5. N012 [000344] CALL nullcheck => $VN.Void ***** BB14, stmt 25 (after) N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 $40 --------- ***** BB14, stmt 26 (before) N002 ( 4, 3) [000079] ------------ * RETURN int N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) N001 [000078] LCL_VAR V05 loc3 u:2 (last use) => $246 {246} N002 [000079] RETURN => $252 {252} ***** BB14, stmt 26 (after) N002 ( 4, 3) [000079] ------------ * RETURN int $252 N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) $246 finish(BB14). *************** In optVnCopyProp() *************** In SsaBuilder::ComputeDominators(Compiler*, ...) Copy Assertion for BB01 Live vars: {V00 V01} => {V00 V01 V16} Live vars: {V00 V01 V16} => {V00 V16} Live vars: {V00 V16} => {V00 V16 V17} Copy Assertion for BB02 Live vars: {V00 V16 V17} => {V00 V09 V16 V17} Live vars: {V00 V09 V16 V17} => {V00 V16 V17} Live vars: {V00 V16 V17} => {V00 V16 V17 V33} Live vars: {V00 V16 V17 V33} => {V00 V16 V17} Live vars: {V00 V16 V17} => {V00 V02 V16 V17} Copy Assertion for BB15 Live vars: {V02} => {V02 V15} Copy Assertion for BB16 Live vars: {V02 V15} => {V02} Live vars: {V02} => {} Copy Assertion for BB03 Live vars: {V00 V02 V16 V17} => {V02 V16 V17} Live vars: {V02 V16 V17} => {V02 V03 V16 V17} Copy Assertion for BB04 Copy Assertion for BB05 Copy Assertion for BB06 Copy Assertion for BB07 Live vars: {V02 V03 V16 V17} => {V02 V03 V13 V16 V17} Live vars: {V02 V03 V13 V16 V17} => {V02 V03 V16 V17} Live vars: {V02 V03 V16 V17} => {V02 V03 V16 V17 V22} Live vars: {V02 V03 V16 V17 V22} => {V02 V03 V16 V17} Live vars: {V02 V03 V16 V17} => {V02 V03 V16 V17 V20} Live vars: {V02 V03 V16 V17 V20} => {V02 V03 V16 V17 V20 V21} Live vars: {V02 V03 V16 V17 V20 V21} => {V02 V03 V16 V17 V21} Live vars: {V02 V03 V16 V17 V21} => {V02 V03 V16 V17} VN based copy assertion for [000433] V21 @00000246 by [000031] V03 @00000246. N004 ( 1, 1) [000433] -------N---- * LCL_VAR int V21 tmp15 u:2 (last use) $246 New refCnts for V21: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 6, refCntWtd = 5.50 copy propagated to: N004 ( 1, 1) [000433] -------N---- * LCL_VAR int V03 loc1 u:2 (last use) $246 Live vars: {V02 V03 V16 V17} => {V02 V03 V17} Live vars: {V02 V03 V17} => {V02 V03 V17 V23} Live vars: {V02 V03 V17 V23} => {V02 V03 V23} Live vars: {V02 V03 V23} => {V02 V03 V23 V24} Live vars: {V02 V03 V23 V24} => {V02 V03 V23 V24 V30} Live vars: {V02 V03 V23 V24 V30} => {V02 V03 V23 V24 V29 V30} Live vars: {V02 V03 V23 V24 V29 V30} => {V02 V03 V24 V29 V30} Live vars: {V02 V03 V24 V29 V30} => {V02 V03 V24 V30} Live vars: {V02 V03 V24 V30} => {V02 V03 V30} Live vars: {V02 V03 V30} => {V02 V03} Copy Assertion for BB08 Live vars: {V02 V03} => {V02} Live vars: {V02} => {V02 V05} Copy Assertion for BB13 Live vars: {V02 V05} => {V02 V05 V15} Copy Assertion for BB14 Live vars: {V02 V05 V15} => {V02 V05} Live vars: {V02 V05} => {V05} Live vars: {V05} => {} Copy Assertion for BB09 Copy Assertion for BB10 Copy Assertion for BB11 Copy Assertion for BB12 Live vars: {V02} => {V02 V08} Live vars: {V02 V08} => {V02 V08 V26} Live vars: {V02 V08 V26} => {V02 V08} Live vars: {V02 V08} => {V02 V08 V27} Live vars: {V02 V08 V27} => {V02 V08} Live vars: {V02 V08} => {V02} *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) $c0 N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 $c0 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 23, 29) [000128] ------------ * STMT void (IL 0x000... ???) N013 ( 23, 29) [000140] --CXG------- | /--* IND ref N011 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000139] --CXG--N---- | | \--* ADD byref $145 N010 ( 20, 23) [000137] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000133] #----------- arg0 in rcx | | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | | \--* CNS_INT int 327 $45 N015 ( 23, 29) [000127] -ACXG---R--- \--* ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref $3c3 N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 $3c3 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void $3c3 N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent $3c3 N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref $3c3 N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 $3c3 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read $246 N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 $40 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int $246 N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 $246 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint $440 N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 $246 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void $4c1 N003 ( 0, 0) [000413] ------------ \--* COMMA void $4c1 N001 ( 0, 0) [000409] ------------ \--* NOP void $4c0 ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null $VN.Null N003 ( 3, 3) [000166] J------N---- \--* EQ int $482 N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 7, 7) [000201] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000200] ---X-------- \--* JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int $483 N002 ( 3, 3) [000197] ---X-------- \--* ARR_LENGTH int $500 N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 7, 7) [000251] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000250] ---X-------- \--* JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int $484 N002 ( 3, 3) [000246] ---X-------- \--* ARR_LENGTH int $500 N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N005 ( 3, 3) [000420] ------------ | /--* ADD byref $146 N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref $147 N002 ( 2, 2) [000417] ---X---N---- | | \--* NULLCHECK byte $34a N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref $147 N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) $146 N003 ( 1, 3) [000230] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 $146 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) $146 N003 ( 1, 3) [000428] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 $146 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 1, 3) [000241] -A------R--- \--* ASG int $246 N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 $246 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int $246 N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void $246 N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) $146 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref $146 N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 $40 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int $485 N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo $24c N002 ( 3, 3) [000277] L----------- | /--* ADDR byref $1c6 N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 $540 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref $1c6 N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 $1c6 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 $VN.Void N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref $14b N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 $VN.Void N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref $14a N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 $1c8 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void $VN.Void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref $1c8 N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 $541 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref $1c8 N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 $1c8 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref $1ca N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 $542 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N003 ( 5, 4) [000075] -A------R--- \--* ASG int $246 N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 $246 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException $VN.Void N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 $4a ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method $302 N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref $346 N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 $346 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor $VN.Void N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString $3d1 N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 $49 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref $347 N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 $3cd N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null $VN.Null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref $3d1 N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 $3d1 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 $346 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW $348 N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) $346 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 27, 32) [000343] ------------ * STMT void (IL ???... ???) N013 ( 23, 29) [000334] --CXG------- | /--* IND ref N011 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000335] --CXG--N---- | | \--* ADD byref $145 N010 ( 20, 23) [000336] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000338] #----------- arg0 in rcx | | +--* IND long $340 N005 ( 3, 10) [000339] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000341] ------------ arg1 in rdx | | \--* CNS_INT int 327 $45 N015 ( 27, 32) [000332] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int $252 N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) $246 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 27, 32) [000318] ------------ * STMT void (IL 0x04E... ???) N013 ( 23, 29) [000330] --CXG------- | /--* IND ref N011 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000329] --CXG--N---- | | \--* ADD byref $145 N010 ( 20, 23) [000327] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000323] #----------- arg0 in rcx | | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | | \--* CNS_INT int 327 $45 N015 ( 27, 32) [000317] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() CSE candidate #01, vn=$500 cseMask=0000000000000001 in BB06, [cost= 3, size= 3]: N002 ( 3, 3) CSE #01 (use)[000246] ---X-------- * ARR_LENGTH int $500 N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 CSE candidate #02, vn=$340 cseMask=0000000000000002 in BB13, [cost= 5, size=12]: N006 ( 5, 12) CSE #02 (use)[000338] #----------- * IND long $340 N005 ( 3, 10) [000339] ------------ \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 CSE candidate #03, vn=$143 cseMask=0000000000000004 in BB13, [cost=20, size=23]: N010 ( 20, 23) CSE #03 (use)[000336] H-CXG------- * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (use)[000338] #----------- arg0 in rcx +--* IND long $340 N005 ( 3, 10) [000339] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000341] ------------ arg1 in rdx \--* CNS_INT int 327 $45 Blocks that generate CSE def/uses BB02 cseGen = 0000000000000006 BB05 cseGen = 0000000000000001 BB06 cseGen = 0000000000000001 BB13 cseGen = 0000000000000006 BB15 cseGen = 0000000000000006 After performing DataFlow for ValnumCSE's BB01 cseIn = 0000000000000000 cseOut = 0000000000000000 BB02 cseIn = 0000000000000000 cseOut = 0000000000000006 BB03 cseIn = 0000000000000006 cseOut = 0000000000000006 BB04 cseIn = 0000000000000006 cseOut = 0000000000000006 BB05 cseIn = 0000000000000006 cseOut = 0000000000000007 BB06 cseIn = 0000000000000007 cseOut = 0000000000000007 BB07 cseIn = 0000000000000007 cseOut = 0000000000000007 BB08 cseIn = 0000000000000007 cseOut = 0000000000000007 BB09 cseIn = 0000000000000007 cseOut = 0000000000000007 BB10 cseIn = 0000000000000007 cseOut = 0000000000000007 BB11 cseIn = 0000000000000006 cseOut = 0000000000000006 BB12 cseIn = 0000000000000006 cseOut = 0000000000000006 BB13 cseIn = 0000000000000007 cseOut = 0000000000000007 BB14 cseIn = 0000000000000007 cseOut = 0000000000000007 BB15 cseIn = 0000000000000000 cseOut = 0000000000000006 BB16 cseIn = 0000000000000006 cseOut = 0000000000000006 Labeling the CSEs with Use/Def information BB02 [000133] Def of CSE #02 [weight=1 ] BB02 [000137] Def of CSE #03 [weight=1 ] BB05 [000197] Def of CSE #01 [weight=0.50] BB06 [000246] Use of CSE #01 [weight=0.50] BB13 [000338] Use of CSE #02 [weight=1 ] BB13 [000336] Use of CSE #03 [weight=1 ] BB15 [000323] Def of CSE #02 [weight=0 ] BB15 [000327] Def of CSE #03 [weight=0 ] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) $c0 N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 $c0 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 23, 29) [000128] ------------ * STMT void (IL 0x000... ???) N013 ( 23, 29) [000140] --CXG------- | /--* IND ref N011 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000139] --CXG--N---- | | \--* ADD byref $145 N010 ( 20, 23) CSE #03 (def)[000137] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (def)[000133] #----------- arg0 in rcx | | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | | \--* CNS_INT int 327 $45 N015 ( 23, 29) [000127] -ACXG---R--- \--* ASG ref N014 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref $3c3 N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 $3c3 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void $3c3 N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent $3c3 N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref $3c3 N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 $3c3 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read $246 N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 $40 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int $246 N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 $246 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint $440 N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 $246 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void $4c1 N003 ( 0, 0) [000413] ------------ \--* COMMA void $4c1 N001 ( 0, 0) [000409] ------------ \--* NOP void $4c0 ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null $VN.Null N003 ( 3, 3) [000166] J------N---- \--* EQ int $482 N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 7, 7) [000201] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000200] ---X-------- \--* JTRUE void N003 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N004 ( 5, 5) [000199] N--X---N-U-- \--* LT int $483 N002 ( 3, 3) CSE #01 (def)[000197] ---X-------- \--* ARR_LENGTH int $500 N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 7, 7) [000251] ------------ * STMT void (IL ???... ???) N005 ( 7, 7) [000250] ---X-------- \--* JTRUE void N003 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N004 ( 5, 5) [000249] N--X---N-U-- \--* LT int $484 N002 ( 3, 3) CSE #01 (use)[000246] ---X-------- \--* ARR_LENGTH int $500 N001 ( 1, 1) [000245] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N005 ( 3, 3) [000420] ------------ | /--* ADD byref $146 N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref $147 N002 ( 2, 2) [000417] ---X---N---- | | \--* NULLCHECK byte $34a N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref $147 N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) $146 N003 ( 1, 3) [000230] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 $146 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) $146 N003 ( 1, 3) [000428] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 $146 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 1, 3) [000241] -A------R--- \--* ASG int $246 N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 $246 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int $246 N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void $246 N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) $146 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref $146 N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 $40 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int $485 N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo $24c N002 ( 3, 3) [000277] L----------- | /--* ADDR byref $1c6 N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 $540 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref $1c6 N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 $1c6 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 $VN.Void N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref $14b N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 $VN.Void N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref $14a N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 $1c8 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void $VN.Void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref $1c8 N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 $541 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref $1c8 N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 $1c8 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref $1ca N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 $542 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N003 ( 5, 4) [000075] -A------R--- \--* ASG int $246 N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 $246 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException $VN.Void N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 $4a ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method $302 N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref $346 N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 $346 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor $VN.Void N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString $3d1 N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 $49 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref $347 N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 $3cd N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null $VN.Null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref $3d1 N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 $3d1 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 $346 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW $348 N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) $346 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 27, 32) [000343] ------------ * STMT void (IL ???... ???) N013 ( 23, 29) [000334] --CXG------- | /--* IND ref N011 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000335] --CXG--N---- | | \--* ADD byref $145 N010 ( 20, 23) CSE #03 (use)[000336] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (use)[000338] #----------- arg0 in rcx | | +--* IND long $340 N005 ( 3, 10) [000339] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000341] ------------ arg1 in rdx | | \--* CNS_INT int 327 $45 N015 ( 27, 32) [000332] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int $252 N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) $246 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 27, 32) [000318] ------------ * STMT void (IL 0x04E... ???) N013 ( 23, 29) [000330] --CXG------- | /--* IND ref N011 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N012 ( 21, 27) [000329] --CXG--N---- | | \--* ADD byref $145 N010 ( 20, 23) CSE #03 (def)[000327] H-CXG------- | | \--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (def)[000323] #----------- arg0 in rcx | | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | | \--* CNS_INT int 327 $45 N015 ( 27, 32) [000317] -ACXG---R--- \--* ASG ref N014 ( 3, 2) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 500 Moderate CSE Promotion cutoff is 150 Framesize estimate is 0x003C We have a small frame Sorted CSE candidates: CSE #03,cseMask=0000000000000004,useCnt=1: [def=100, use=100] :: N010 ( 20, 23) CSE #03 (def)[000137] H-CXG------- * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 CSE #02,cseMask=0000000000000002,useCnt=1: [def=100, use=100] :: N006 ( 5, 12) CSE #02 (def)[000133] #----------- * IND long $340 CSE #01,cseMask=0000000000000001,useCnt=1: [def= 50, use= 50] :: N002 ( 3, 3) CSE #01 (def)[000197] ---X-------- * ARR_LENGTH int $500 Considering CSE #03 [def=100, use=100, cost=20] CSE Expression: N010 ( 20, 23) CSE #03 (def)[000137] H-CXG------- * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (def)[000133] #----------- arg0 in rcx +--* IND long $340 N005 ( 3, 10) [000132] ------------ | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx \--* CNS_INT int 327 $45 Moderate CSE Promotion (CSE never live at call) (300 >= 150) cseRefCnt=300, aggressiveRefCnt=500, moderateRefCnt=150 defCnt=100, useCnt=100, cost=20, size=23 def_cost=2, use_cost=1, extra_no_cost=44, extra_yes_cost=0 CSE cost savings check (2044 >= 300) passes Promoting CSE: lvaGrabTemp returning 34 (V34 rat0) (a long lifetime temp) called for ValNumCSE. CSE #03 def at [000137] replaced in BB02 with def of V34 New refCnts for V34: refCnt = 1, refCntWtd = 1 New refCnts for V34: refCnt = 2, refCntWtd = 2 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 fgArgTabEntry[arg 0 133.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 134.CNS_INT, rdx, regs=1, align=1, lateArgInx=1, processed] New refCnts for V09: refCnt = 3, refCntWtd = 3 New refCnts for V34: refCnt = 3, refCntWtd = 3 New refCnts for V34: refCnt = 4, refCntWtd = 4 optValnumCSE morphed tree: N017 ( 24, 30) [000140] -ACXG------- /--* IND ref N015 ( 1, 4) [000138] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000139] -ACXG--N---- | \--* ADD byref $145 N013 ( 1, 1) [000500] ------------ | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000501] -ACXG------- | \--* COMMA byref $143 N010 ( 20, 23) [000137] H-CXG------- | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (def)[000133] #----------- arg0 in rcx | | | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000499] -ACXG---R--- | \--* ASG byref $VN.Void N011 ( 1, 1) [000498] D------N---- | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000127] -ACXG---R--- * ASG ref N018 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 CSE #03 use at [000336] replaced in BB13 with temp use. Unmark CSE use #02 at [000338]: 1 -> 0 New refCnts for V34: refCnt = 5, refCntWtd = 5 New refCnts for V15: refCnt = 5, refCntWtd = 3 New refCnts for V34: refCnt = 6, refCntWtd = 6 optValnumCSE morphed tree: N004 ( 4, 7) [000334] ---XG------- /--* IND ref N002 ( 1, 4) [000342] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N003 ( 2, 5) [000335] ----G--N---- | \--* ADD byref $145 N001 ( 1, 1) [000502] ------------ | \--* LCL_VAR byref V34 cse0 $143 N006 ( 4, 7) [000332] -A-XG---R--- * ASG ref N005 ( 1, 1) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 CSE #03 def at [000327] replaced in BB15 with def of V34 New refCnts for V34: refCnt = 7, refCntWtd = 6 New refCnts for V34: refCnt = 8, refCntWtd = 6 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 fgArgTabEntry[arg 0 323.IND, rcx, regs=1, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 1 324.CNS_INT, rdx, regs=1, align=1, lateArgInx=1, processed] New refCnts for V15: refCnt = 6, refCntWtd = 3 New refCnts for V34: refCnt = 9, refCntWtd = 6 New refCnts for V34: refCnt = 10, refCntWtd = 6 optValnumCSE morphed tree: N017 ( 24, 30) [000330] -ACXG------- /--* IND ref N015 ( 1, 4) [000328] ------------ | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000329] -ACXG--N---- | \--* ADD byref $145 N013 ( 1, 1) [000505] ------------ | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000506] -ACXG------- | \--* COMMA byref $143 N010 ( 20, 23) [000327] H-CXG------- | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) CSE #02 (def)[000323] #----------- arg0 in rcx | | | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000504] -ACXG---R--- | \--* ASG byref $VN.Void N011 ( 1, 1) [000503] D------N---- | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000317] -ACXG---R--- * ASG ref N018 ( 1, 1) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 Skipped CSE #02 because use count is 0 Considering CSE #01 [def=50, use=50, cost= 3] CSE Expression: N002 ( 3, 3) CSE #01 (def)[000197] ---X-------- * ARR_LENGTH int $500 N001 ( 1, 1) [000196] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 Moderate CSE Promotion (CSE never live at call) (150 >= 150) cseRefCnt=150, aggressiveRefCnt=500, moderateRefCnt=150 defCnt=50, useCnt=50, cost=3, size=3 def_cost=2, use_cost=1, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (154 >= 150) passes Promoting CSE: lvaGrabTemp returning 35 (V35 rat0) (a long lifetime temp) called for ValNumCSE. CSE #01 def at [000197] replaced in BB05 with def of V35 New refCnts for V35: refCnt = 1, refCntWtd = 0.50 New refCnts for V35: refCnt = 2, refCntWtd = 1 New refCnts for V35: refCnt = 3, refCntWtd = 1.50 New refCnts for V02: refCnt = 10, refCntWtd = 7.50 New refCnts for V35: refCnt = 4, refCntWtd = 2 optValnumCSE morphed tree: N009 ( 16, 13) [000200] -A-X-------- * JTRUE void N007 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N008 ( 14, 11) [000199] NA-X---N-U-- \--* LT int $483 N005 ( 3, 2) [000509] ------------ | /--* LCL_VAR int V35 cse1 $500 N006 ( 12, 9) [000510] -A-X-------- \--* COMMA int $500 N002 ( 5, 4) [000197] ---X-------- | /--* ARR_LENGTH int $500 N001 ( 3, 2) [000196] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N004 ( 9, 7) [000508] -A-X----R--- \--* ASG int $VN.Void N003 ( 3, 2) [000507] D------N---- \--* LCL_VAR int V35 cse1 $500 CSE #01 use at [000246] replaced in BB06 with temp use. New refCnts for V02: refCnt = 9, refCntWtd = 7 New refCnts for V35: refCnt = 5, refCntWtd = 2.50 New refCnts for V35: refCnt = 6, refCntWtd = 3 New refCnts for V03: refCnt = 7, refCntWtd = 6 optValnumCSE morphed tree: N004 ( 5, 5) [000250] ------------ * JTRUE void N002 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 3, 3) [000249] N------N-U-- \--* LT int $484 N001 ( 1, 1) [000511] ------------ \--* LCL_VAR int V35 cse1 $500 *************** In optAssertionPropMain() Blocks/Trees at start of phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) $c0 N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 $c0 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 24, 30) [000128] ------------ * STMT void (IL 0x000... ???) N017 ( 24, 30) [000140] -ACXG------- | /--* IND ref N015 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000139] -ACXG--N---- | | \--* ADD byref $145 N013 ( 1, 1) [000500] ------------ | | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000501] -ACXG------- | | \--* COMMA byref $143 N010 ( 20, 23) [000137] H-CXG------- | | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000133] #----------- arg0 in rcx | | | | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000499] -ACXG---R--- | | \--* ASG byref $VN.Void N011 ( 1, 1) [000498] D------N---- | | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000127] -ACXG---R--- \--* ASG ref N018 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref $3c3 N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 $3c3 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void $3c3 N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent $3c3 N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref $3c3 N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 $3c3 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read $246 N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 $40 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int $246 N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 $246 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint $440 N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 $246 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void $4c1 N003 ( 0, 0) [000413] ------------ \--* COMMA void $4c1 N001 ( 0, 0) [000409] ------------ \--* NOP void $4c0 ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null $VN.Null N003 ( 3, 3) [000166] J------N---- \--* EQ int $482 N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 16, 13) [000201] ------------ * STMT void (IL ???... ???) N009 ( 16, 13) [000200] -A-X-------- \--* JTRUE void N007 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N008 ( 14, 11) [000199] NA-X---N-U-- \--* LT int $483 N005 ( 3, 2) [000509] ------------ | /--* LCL_VAR int V35 cse1 $500 N006 ( 12, 9) [000510] -A-X-------- \--* COMMA int $500 N002 ( 5, 4) [000197] ---X-------- | /--* ARR_LENGTH int $500 N001 ( 3, 2) [000196] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N004 ( 9, 7) [000508] -A-X----R--- \--* ASG int $VN.Void N003 ( 3, 2) [000507] D------N---- \--* LCL_VAR int V35 cse1 $500 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 5, 5) [000251] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000250] ------------ \--* JTRUE void N002 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 3, 3) [000249] N------N-U-- \--* LT int $484 N001 ( 1, 1) [000511] ------------ \--* LCL_VAR int V35 cse1 $500 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N005 ( 3, 3) [000420] ------------ | /--* ADD byref $146 N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref $147 N002 ( 2, 2) [000417] ---X---N---- | | \--* NULLCHECK byte $34a N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref $147 N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) $146 N003 ( 1, 3) [000230] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 $146 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) $146 N003 ( 1, 3) [000428] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 $146 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 1, 3) [000241] -A------R--- \--* ASG int $246 N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 $246 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int $246 N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void $246 N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) $146 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref $146 N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 $40 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int $485 N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo $24c N002 ( 3, 3) [000277] L----------- | /--* ADDR byref $1c6 N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 $540 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref $1c6 N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 $1c6 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 $VN.Void N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref $14b N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 $VN.Void N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref $14a N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 $1c8 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void $VN.Void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref $1c8 N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 $541 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref $1c8 N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 $1c8 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref $1ca N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 $542 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N003 ( 5, 4) [000075] -A------R--- \--* ASG int $246 N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 $246 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException $VN.Void N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 $4a ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method $302 N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref $346 N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 $346 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor $VN.Void N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString $3d1 N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 $49 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref $347 N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 $3cd N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null $VN.Null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref $3d1 N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 $3d1 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 $346 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW $348 N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) $346 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 4, 7) [000343] ------------ * STMT void (IL ???... ???) N004 ( 4, 7) [000334] ---XG------- | /--* IND ref N002 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N003 ( 2, 5) [000335] ----G--N---- | | \--* ADD byref $145 N001 ( 1, 1) [000502] ------------ | | \--* LCL_VAR byref V34 cse0 $143 N006 ( 4, 7) [000332] -A-XG---R--- \--* ASG ref N005 ( 1, 1) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int $252 N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) $246 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 24, 30) [000318] ------------ * STMT void (IL 0x04E... ???) N017 ( 24, 30) [000330] -ACXG------- | /--* IND ref N015 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000329] -ACXG--N---- | | \--* ADD byref $145 N013 ( 1, 1) [000505] ------------ | | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000506] -ACXG------- | | \--* COMMA byref $143 N010 ( 20, 23) [000327] H-CXG------- | | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000323] #----------- arg0 in rcx | | | | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000504] -ACXG---R--- | | \--* ASG byref $VN.Void N011 ( 1, 1) [000503] D------N---- | | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000317] -ACXG---R--- \--* ASG ref N018 ( 1, 1) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- GenTreeNode creates assertion: N008 ( 22, 12) [000013] --CXG------- * CALLV ind ref ArrayPool`1.Rent $3c3 In BB02 New Global Constant Assertion: (960, 0) ($3c0,$0) V09.02 != null index=#01, mask=0000000000000001 GenTreeNode creates assertion: N016 ( 24, 16) [000027] --CXG------- * CALLV ind int Stream.Read $246 In BB03 New Global Constant Assertion: (128, 0) ($80,$0) V00.02 != null index=#02, mask=0000000000000002 GenTreeNode creates assertion: N004 ( 5, 5) [000167] ------------ * JTRUE void In BB04 New Global Constant Assertion: (963, 0) ($3c3,$0) V02.02 == null index=#03, mask=0000000000000004 GenTreeNode creates assertion: N004 ( 5, 5) [000167] ------------ * JTRUE void In BB04 New Global Constant Assertion: (963, 0) ($3c3,$0) V02.02 != null index=#04, mask=0000000000000008 GenTreeNode creates assertion: N002 ( 5, 4) [000197] ---X-------- * ARR_LENGTH int $500 In BB05 New Global Constant Assertion: (963, 0) ($3c3,$0) V02.02 != null index=#05, mask=0000000000000010 GenTreeNode creates assertion: N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void In BB14 New Global Constant Assertion: (993, 0) ($3e1,$0) V15.03 != null index=#06, mask=0000000000000020 GenTreeNode creates assertion: N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void In BB16 New Global Constant Assertion: (988, 0) ($3dc,$0) V15.02 != null index=#07, mask=0000000000000040 BB01 valueGen = 0000000000000000 BB02 valueGen = 0000000000000001 BB03 valueGen = 0000000000000002 => BB12 valueGen = 0000000000000002, BB04 valueGen = 0000000000000008 => BB11 valueGen = 0000000000000004, BB05 valueGen = 0000000000000010 => BB10 valueGen = 0000000000000010, BB06 valueGen = 0000000000000000 => BB10 valueGen = 0000000000000000, BB07 valueGen = 0000000000000010 => BB09 valueGen = 0000000000000010, BB08 valueGen = 0000000000000000 BB09 valueGen = 0000000000000000 BB10 valueGen = 0000000000000000 BB11 valueGen = 0000000000000000 BB12 valueGen = 0000000000000000 BB13 valueGen = 0000000000000000 BB14 valueGen = 0000000000000020 BB15 valueGen = 0000000000000000 BB16 valueGen = 0000000000000040AssertionPropCallback::StartMerge: BB01 in -> 0000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 0000000000000000 AssertionPropCallback::Changed : BB01 before out -> 000000000000007F; after out -> 0000000000000000; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB02 in -> 000000000000007F AssertionPropCallback::Merge : BB02 in -> 000000000000007F, predBlock BB01 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB02 in -> 0000000000000000 AssertionPropCallback::Changed : BB02 before out -> 000000000000007F; after out -> 0000000000000001; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB03 in -> 000000000000007F AssertionPropCallback::Merge : BB03 in -> 000000000000007F, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB03 in -> 0000000000000001 AssertionPropCallback::Changed : BB03 before out -> 000000000000007F; after out -> 0000000000000003; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Changed : BB15 before out -> 000000000000007F; after out -> 0000000000000000; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB04 in -> 000000000000007F AssertionPropCallback::Merge : BB04 in -> 000000000000007F, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB04 in -> 0000000000000003 AssertionPropCallback::Changed : BB04 before out -> 000000000000007F; after out -> 000000000000000B; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000007; AssertionPropCallback::StartMerge: BB12 in -> 000000000000007F AssertionPropCallback::Merge : BB12 in -> 000000000000007F, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::EndMerge : BB12 in -> 0000000000000003 AssertionPropCallback::Changed : BB12 before out -> 000000000000007F; after out -> 0000000000000003; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000003; AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB16 in -> 000000000000007F AssertionPropCallback::Merge : BB16 in -> 000000000000007F, predBlock BB15 out -> 0000000000000000 AssertionPropCallback::EndMerge : BB16 in -> 0000000000000000 AssertionPropCallback::Changed : BB16 before out -> 000000000000007F; after out -> 0000000000000040; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000000; AssertionPropCallback::StartMerge: BB05 in -> 000000000000007F AssertionPropCallback::Merge : BB05 in -> 000000000000007F, predBlock BB04 out -> 000000000000000B AssertionPropCallback::EndMerge : BB05 in -> 000000000000000B AssertionPropCallback::Changed : BB05 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB11 in -> 000000000000007F AssertionPropCallback::Merge : BB11 in -> 000000000000007F, predBlock BB04 out -> 000000000000000B AssertionPropCallback::EndMerge : BB11 in -> 0000000000000007 AssertionPropCallback::Changed : BB11 before out -> 000000000000007F; after out -> 0000000000000007; jumpDest before out -> 000000000000007F; jumpDest after out -> 0000000000000007; AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB06 in -> 000000000000007F AssertionPropCallback::Merge : BB06 in -> 000000000000007F, predBlock BB05 out -> 000000000000001B AssertionPropCallback::EndMerge : BB06 in -> 000000000000001B AssertionPropCallback::Changed : BB06 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB10 in -> 000000000000007F AssertionPropCallback::Merge : BB10 in -> 000000000000007F, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB10 in -> 000000000000001B, predBlock BB06 out -> 000000000000001B AssertionPropCallback::EndMerge : BB10 in -> 000000000000001B AssertionPropCallback::Changed : BB10 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB07 in -> 000000000000007F AssertionPropCallback::Merge : BB07 in -> 000000000000007F, predBlock BB06 out -> 000000000000001B AssertionPropCallback::EndMerge : BB07 in -> 000000000000001B AssertionPropCallback::Changed : BB07 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB10 in -> 000000000000001B AssertionPropCallback::Merge : BB10 in -> 000000000000001B, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB10 in -> 000000000000001B, predBlock BB06 out -> 000000000000001B AssertionPropCallback::EndMerge : BB10 in -> 000000000000001B AssertionPropCallback::Unchanged : BB10 out -> 000000000000001B; jumpDest out -> 000000000000001B AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000007F AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB08 in -> 000000000000007F AssertionPropCallback::Merge : BB08 in -> 000000000000007F, predBlock BB07 out -> 000000000000001B AssertionPropCallback::EndMerge : BB08 in -> 000000000000001B AssertionPropCallback::Changed : BB08 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB09 in -> 000000000000007F AssertionPropCallback::Merge : BB09 in -> 000000000000007F, predBlock BB07 out -> 000000000000001B AssertionPropCallback::EndMerge : BB09 in -> 000000000000001B AssertionPropCallback::Changed : BB09 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB13 in -> 000000000000007F AssertionPropCallback::Merge : BB13 in -> 000000000000007F, predBlock BB08 out -> 000000000000001B AssertionPropCallback::EndMerge : BB13 in -> 000000000000001B AssertionPropCallback::Changed : BB13 before out -> 000000000000007F; after out -> 000000000000001B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB15 in -> 0000000000000000 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB12 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB11 out -> 0000000000000007 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB10 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB09 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB08 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB07 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB06 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB05 out -> 000000000000001B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB04 out -> 000000000000000B AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB03 out -> 0000000000000003 AssertionPropCallback::Merge : BB15 in -> 0000000000000000, predBlock BB02 out -> 0000000000000001 AssertionPropCallback::EndMerge : BB15 in -> 0000000000000000 AssertionPropCallback::Unchanged : BB15 out -> 0000000000000000; jumpDest out -> 0000000000000000 AssertionPropCallback::StartMerge: BB14 in -> 000000000000007F AssertionPropCallback::Merge : BB14 in -> 000000000000007F, predBlock BB13 out -> 000000000000001B AssertionPropCallback::EndMerge : BB14 in -> 000000000000001B AssertionPropCallback::Changed : BB14 before out -> 000000000000007F; after out -> 000000000000003B; jumpDest before out -> 000000000000007F; jumpDest after out -> 000000000000001B; BB01 valueIn = 0000000000000000 valueOut = 0000000000000000 BB02 valueIn = 0000000000000000 valueOut = 0000000000000001 BB03 valueIn = 0000000000000001 valueOut = 0000000000000003 => BB12 valueOut= 0000000000000003 BB04 valueIn = 0000000000000003 valueOut = 000000000000000B => BB11 valueOut= 0000000000000007 BB05 valueIn = 000000000000000B valueOut = 000000000000001B => BB10 valueOut= 000000000000001B BB06 valueIn = 000000000000001B valueOut = 000000000000001B => BB10 valueOut= 000000000000001B BB07 valueIn = 000000000000001B valueOut = 000000000000001B => BB09 valueOut= 000000000000001B BB08 valueIn = 000000000000001B valueOut = 000000000000001B BB09 valueIn = 000000000000001B valueOut = 000000000000001B BB10 valueIn = 000000000000001B valueOut = 000000000000001B BB11 valueIn = 0000000000000007 valueOut = 0000000000000007 BB12 valueIn = 0000000000000003 valueOut = 0000000000000003 BB13 valueIn = 000000000000001B valueOut = 000000000000001B BB14 valueIn = 000000000000001B valueOut = 000000000000003B BB15 valueIn = 0000000000000000 valueOut = 0000000000000000 BB16 valueIn = 0000000000000000 valueOut = 0000000000000040 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000360], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000361], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000362], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000363], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000359], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000364], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000366], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000367], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000368], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000369], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000365], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000370], tree -> 0 Propagating 0000000000000000 assertions for BB01, stmt [000357], tree [000371], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000372], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000374], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000135], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000136], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000132], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000133], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000134], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000375], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000373], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000137], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000498], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000499], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000500], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000501], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000138], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000139], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000140], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000126], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000128], tree [000127], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000376], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000378], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000014], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000011], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000145], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000379], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000377], tree -> 0 Propagating 0000000000000000 assertions for BB02, stmt [000017], tree [000013], tree -> 1 Propagating 0000000000000001 assertions for BB02, stmt [000017], tree [000494], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt [000017], tree [000495], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt [000017], tree [000496], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt [000017], tree [000015], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt [000017], tree [000497], tree -> 0 Propagating 0000000000000001 assertions for BB02, stmt [000017], tree [000016], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000380], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000382], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000386], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000384], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000028], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000029], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000030], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000019], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000020], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000150], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000021], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000387], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000385], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000383], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000381], tree -> 0 Propagating 0000000000000001 assertions for BB03, stmt [000033], tree [000027], tree -> 2 Propagating 0000000000000003 assertions for BB03, stmt [000033], tree [000031], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt [000033], tree [000032], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt [000044], tree [000034], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt [000044], tree [000035], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt [000044], tree [000155], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt [000044], tree [000041], tree -> 0 Propagating 0000000000000003 assertions for BB03, stmt [000044], tree [000042], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt [000052], tree [000409], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt [000052], tree [000412], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt [000052], tree [000413], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt [000168], tree [000046], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt [000168], tree [000165], tree -> 0 Propagating 0000000000000003 assertions for BB04, stmt [000168], tree [000166], tree -> 0 Propagating 000000000000000B assertions for BB05, stmt [000201], tree [000196], tree -> 0 Propagating 000000000000000B assertions for BB05, stmt [000201], tree [000197], tree -> 5 Propagating 000000000000001B assertions for BB05, stmt [000201], tree [000507], tree -> 0 Propagating 000000000000001B assertions for BB05, stmt [000201], tree [000508], tree -> 0 Propagating 000000000000001B assertions for BB05, stmt [000201], tree [000509], tree -> 0 Propagating 000000000000001B assertions for BB05, stmt [000201], tree [000510], tree -> 0 Propagating 000000000000001B assertions for BB05, stmt [000201], tree [000195], tree -> 0 Propagating 000000000000001B assertions for BB05, stmt [000201], tree [000199], tree -> 0 Propagating 000000000000001B assertions for BB06, stmt [000251], tree [000511], tree -> 0 Propagating 000000000000001B assertions for BB06, stmt [000251], tree [000244], tree -> 0 Propagating 000000000000001B assertions for BB06, stmt [000251], tree [000249], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000416], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000417], tree -> 5 Non-null prop for index #04 in BB07: N002 ( 2, 2) [000417] ---X---N---- * NULLCHECK byte $34a Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000418], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000419], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000420], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000421], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000264], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000266], tree [000265], tree -> 0 Re-morphing this stmt: ( 5, 5) [000266] ------------ * STMT void (IL ???... ???) N004 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N005 ( 3, 3) [000420] ------------ | /--* ADD byref $146 N003 ( 1, 1) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N006 ( 5, 5) [000421] ---XG--N---- | /--* COMMA byref $147 N002 ( 2, 2) [000417] -----O-N---- | | \--* NULLCHECK byte $34a N001 ( 1, 1) [000416] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N008 ( 5, 5) [000265] -A-XG---R--- \--* ASG byref $147 N007 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 New refCnts for V02: refCnt = 8, refCntWtd = 6 New refCnts for V13: refCnt = 3, refCntWtd = 6 New refCnts for V02: refCnt = 9, refCntWtd = 7 optAssertionPropMain morphed tree: N002 ( 1, 1) [000419] ------------ /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N003 ( 5, 4) [000420] -------N---- /--* ADD byref $146 N001 ( 3, 2) [000418] ------------ | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N005 ( 5, 4) [000265] -A--G---R--- * ASG byref $147 N004 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 Propagating 000000000000001B assertions for BB07, stmt [000232], tree [000263], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000232], tree [000229], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000232], tree [000230], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000237], tree [000427], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000237], tree [000426], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000237], tree [000428], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000242], tree [000048], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000242], tree [000240], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000242], tree [000241], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000430], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000429], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000431], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000433], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000432], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000434], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000064], tree [000435], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000437], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000436], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000438], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000440], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000439], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000441], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000297], tree [000442], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000278], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000277], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000464], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000465], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000447], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000446], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000448], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000449], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000450], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000451], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000452], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000453], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000454], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000455], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000456], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000457], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000458], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000459], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000460], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000461], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000462], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000463], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000283], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000466], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000468], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000469], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000470], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000467], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000280], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000286], tree -> 0 Propagating 000000000000001B assertions for BB07, stmt [000289], tree [000287], tree -> 0 Propagating 000000000000001B assertions for BB08, stmt [000076], tree [000073], tree -> 0 Propagating 000000000000001B assertions for BB08, stmt [000076], tree [000074], tree -> 0 Propagating 000000000000001B assertions for BB08, stmt [000076], tree [000075], tree -> 0 Propagating 000000000000001B assertions for BB09, stmt [000293], tree [000292], tree -> 0 Propagating 000000000000001B assertions for BB10, stmt [000204], tree [000203], tree -> 0 Propagating 0000000000000007 assertions for BB11, stmt [000256], tree [000414], tree -> 0 Propagating 0000000000000007 assertions for BB11, stmt [000256], tree [000255], tree -> 0 Propagating 0000000000000007 assertions for BB11, stmt [000256], tree [000253], tree -> 0 Propagating 0000000000000007 assertions for BB11, stmt [000256], tree [000415], tree -> 0 Propagating 0000000000000007 assertions for BB11, stmt [000256], tree [000254], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000492], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000491], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000085], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000493], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000086], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000087], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000089], tree [000088], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000403], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000391], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000389], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000388], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000392], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000390], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000393], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000394], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000397], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000161], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000162], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000395], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000159], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000398], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000396], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000160], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000399], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000400], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000092], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000401], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000090], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000404], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000402], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000093], tree [000091], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000097], tree [000405], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000097], tree [000095], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000097], tree [000094], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000097], tree [000406], tree -> 0 Propagating 0000000000000003 assertions for BB12, stmt [000097], tree [000096], tree -> 0 Propagating 000000000000001B assertions for BB13, stmt [000343], tree [000502], tree -> 0 Propagating 000000000000001B assertions for BB13, stmt [000343], tree [000342], tree -> 0 Propagating 000000000000001B assertions for BB13, stmt [000343], tree [000335], tree -> 0 Propagating 000000000000001B assertions for BB13, stmt [000343], tree [000334], tree -> 0 Propagating 000000000000001B assertions for BB13, stmt [000343], tree [000333], tree -> 0 Propagating 000000000000001B assertions for BB13, stmt [000343], tree [000332], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000475], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000477], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000479], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000348], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000346], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000345], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000347], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000349], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000480], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000478], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000476], tree -> 0 Propagating 000000000000001B assertions for BB14, stmt [000350], tree [000344], tree -> 6 Propagating 000000000000003B assertions for BB14, stmt [000080], tree [000078], tree -> 0 Propagating 000000000000003B assertions for BB14, stmt [000080], tree [000079], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000485], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000487], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000489], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000105], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000106], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000319], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000102], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000103], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000490], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000488], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000486], tree -> 0 Propagating 0000000000000000 assertions for BB16, stmt [000107], tree [000104], tree -> 7 Propagating 0000000000000040 assertions for BB16, stmt [000109], tree [000108], tree -> 0 *************** In fgDebugCheckBBlist *************** In OptimizeRangeChecks() Blocks/trees before phase -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) $c0 N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 $c0 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 24, 30) [000128] ------------ * STMT void (IL 0x000... ???) N017 ( 24, 30) [000140] -ACXG------- | /--* IND ref N015 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000139] -ACXG--N---- | | \--* ADD byref $145 N013 ( 1, 1) [000500] ------------ | | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000501] -ACXG------- | | \--* COMMA byref $143 N010 ( 20, 23) [000137] H-CXG------- | | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000133] #----------- arg0 in rcx | | | | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000499] -ACXG---R--- | | \--* ASG byref $VN.Void N011 ( 1, 1) [000498] D------N---- | | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000127] -ACXG---R--- \--* ASG ref N018 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref $3c3 N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 $3c3 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void $3c3 N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent $3c3 N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref $3c3 N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 $3c3 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read $246 N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 $40 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int $246 N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 $246 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint $440 N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 $246 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void $4c1 N003 ( 0, 0) [000413] ------------ \--* COMMA void $4c1 N001 ( 0, 0) [000409] ------------ \--* NOP void $4c0 ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null $VN.Null N003 ( 3, 3) [000166] J------N---- \--* EQ int $482 N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 16, 13) [000201] ------------ * STMT void (IL ???... ???) N009 ( 16, 13) [000200] -A-X-------- \--* JTRUE void N007 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N008 ( 14, 11) [000199] NA-X---N-U-- \--* LT int $483 N005 ( 3, 2) [000509] ------------ | /--* LCL_VAR int V35 cse1 $500 N006 ( 12, 9) [000510] -A-X-------- \--* COMMA int $500 N002 ( 5, 4) [000197] ---X-------- | /--* ARR_LENGTH int $500 N001 ( 3, 2) [000196] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N004 ( 9, 7) [000508] -A-X----R--- \--* ASG int $VN.Void N003 ( 3, 2) [000507] D------N---- \--* LCL_VAR int V35 cse1 $500 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 5, 5) [000251] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000250] ------------ \--* JTRUE void N002 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 3, 3) [000249] N------N-U-- \--* LT int $484 N001 ( 1, 1) [000511] ------------ \--* LCL_VAR int V35 cse1 $500 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 4) [000266] ------------ * STMT void (IL ???... ???) N002 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N003 ( 5, 4) [000420] -------N---- | /--* ADD byref $146 N001 ( 3, 2) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N005 ( 5, 4) [000265] -A--G---R--- \--* ASG byref $147 N004 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) $146 N003 ( 1, 3) [000230] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 $146 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) $146 N003 ( 1, 3) [000428] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 $146 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 1, 3) [000241] -A------R--- \--* ASG int $246 N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 $246 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int $246 N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void $246 N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) $146 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref $146 N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 $40 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int $485 N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo $24c N002 ( 3, 3) [000277] L----------- | /--* ADDR byref $1c6 N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 $540 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref $1c6 N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 $1c6 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 $VN.Void N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref $14b N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 $VN.Void N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref $14a N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 $1c8 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void $VN.Void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref $1c8 N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 $541 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref $1c8 N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 $1c8 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref $1ca N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 $542 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N003 ( 5, 4) [000075] -A------R--- \--* ASG int $246 N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 $246 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException $VN.Void N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 $4a ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method $302 N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref $346 N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 $346 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor $VN.Void N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString $3d1 N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 $49 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref $347 N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 $3cd N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null $VN.Null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref $3d1 N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 $3d1 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 $346 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW $348 N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) $346 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 4, 7) [000343] ------------ * STMT void (IL ???... ???) N004 ( 4, 7) [000334] ---XG------- | /--* IND ref N002 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N003 ( 2, 5) [000335] ----G--N---- | | \--* ADD byref $145 N001 ( 1, 1) [000502] ------------ | | \--* LCL_VAR byref V34 cse0 $143 N006 ( 4, 7) [000332] -A-XG---R--- \--* ASG ref N005 ( 1, 1) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int $252 N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) $246 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 24, 30) [000318] ------------ * STMT void (IL 0x04E... ???) N017 ( 24, 30) [000330] -ACXG------- | /--* IND ref N015 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000329] -ACXG--N---- | | \--* ADD byref $145 N013 ( 1, 1) [000505] ------------ | | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000506] -ACXG------- | | \--* COMMA byref $143 N010 ( 20, 23) [000327] H-CXG------- | | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000323] #----------- arg0 in rcx | | | | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000504] -ACXG---R--- | | \--* ASG byref $VN.Void N011 ( 1, 1) [000503] D------N---- | | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000317] -ACXG---R--- \--* ASG ref N018 ( 1, 1) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method with EH (implementation limitation) *************** In IR Rationalize Trees before IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target BB02 [0000] 1 BB01 1 [000..012) i gcsafe BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} ***** BB01, stmt 1 ( 8, 7) [000357] ------------ * STMT void (IL ???... ???) N010 ( 4, 4) [000369] x----------- | /--* IND int N008 ( 1, 1) [000367] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N009 ( 2, 2) [000368] -------N---- | | \--* ADD byref $141 N007 ( 1, 1) [000366] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 (last use) $c0 N012 ( 4, 4) [000370] -A------R--- | /--* ASG int N011 ( 1, 1) [000365] D------N---- | | \--* LCL_VAR int V17 tmp11 d:2 N013 ( 8, 7) [000371] -A---------- \--* COMMA void N004 ( 4, 3) [000363] x----------- | /--* IND byref N002 ( 1, 1) [000361] ------------ | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N003 ( 3, 3) [000362] -------N---- | | \--* ADD byref $140 N001 ( 1, 1) [000360] ------------ | | \--* LCL_VAR byref V01 arg1 u:2 $c0 N006 ( 4, 3) [000364] -A------R--- \--* ASG byref N005 ( 1, 1) [000359] D------N---- \--* LCL_VAR byref V16 tmp10 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ***** BB02, stmt 2 ( 24, 30) [000128] ------------ * STMT void (IL 0x000... ???) N017 ( 24, 30) [000140] -ACXG------- | /--* IND ref N015 ( 1, 4) [000138] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000139] -ACXG--N---- | | \--* ADD byref $145 N013 ( 1, 1) [000500] ------------ | | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000501] -ACXG------- | | \--* COMMA byref $143 N010 ( 20, 23) [000137] H-CXG------- | | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000133] #----------- arg0 in rcx | | | | +--* IND long $340 N005 ( 3, 10) [000132] ------------ | | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000134] ------------ arg1 in rdx | | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000499] -ACXG---R--- | | \--* ASG byref $VN.Void N011 ( 1, 1) [000498] D------N---- | | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000127] -ACXG---R--- \--* ASG ref N018 ( 1, 1) [000126] D------N---- \--* LCL_VAR ref V09 tmp3 d:2 ***** BB02, stmt 3 ( 29, 18) [000017] ------------ * STMT void (IL ???... ???) N011 ( 3, 2) [000496] ------------ | /--* LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 N013 ( 3, 3) [000497] -A------R--- | /--* ASG ref $3c3 N012 ( 1, 1) [000015] D------N---- | | \--* LCL_VAR ref V02 loc0 d:2 $3c3 N014 ( 29, 18) [000016] -ACXG------- \--* COMMA void $3c3 N008 ( 22, 12) [000013] --CXG------- | /--* CALLV ind ref ArrayPool`1.Rent $3c3 N004 ( 1, 1) [000011] ------------ this in rcx | | +--* LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ arg1 in rdx | | \--* LCL_VAR int V17 tmp11 u:2 N010 ( 26, 15) [000495] -ACXG---R--- \--* ASG ref $3c3 N009 ( 3, 2) [000494] D------N---- \--* LCL_VAR ref V33 tmp27 d:2 $3c3 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ***** BB03, stmt 4 ( 24, 16) [000033] ------------ * STMT void (IL ???... ???) N016 ( 24, 16) [000027] --CXG------- | /--* CALLV ind int Stream.Read $246 N008 ( 1, 1) [000019] ------------ this in rcx | | +--* LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ arg1 in rdx | | +--* LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ arg3 in r9 | | +--* LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ arg2 in r8 | | \--* CNS_INT int 0 $40 N018 ( 24, 16) [000032] -ACXG---R--- \--* ASG int $246 N017 ( 1, 1) [000031] D------N---- \--* LCL_VAR int V03 loc1 d:2 $246 ***** BB03, stmt 5 ( 7, 9) [000044] ------------ * STMT void (IL ???... ???) N006 ( 7, 9) [000043] ------------ \--* JTRUE void N004 ( 2, 3) [000041] ------------ | /--* CAST long <- int N003 ( 1, 1) [000155] ------------ | | \--* LCL_VAR int V17 tmp11 u:2 N005 ( 5, 7) [000042] J------N---- \--* GT int N002 ( 2, 3) [000035] ---------U-- \--* CAST long <- ulong <- uint $440 N001 ( 1, 1) [000034] ------------ \--* LCL_VAR int V03 loc1 u:2 $246 ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ***** BB04, stmt 6 ( 0, 0) [000052] ------------ * STMT void (IL 0x039...0x041) N002 ( 0, 0) [000412] ------------ | /--* NOP void $4c1 N003 ( 0, 0) [000413] ------------ \--* COMMA void $4c1 N001 ( 0, 0) [000409] ------------ \--* NOP void $4c0 ***** BB04, stmt 7 ( 5, 5) [000168] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000167] ------------ \--* JTRUE void N002 ( 1, 1) [000165] ------------ | /--* CNS_INT ref null $VN.Null N003 ( 3, 3) [000166] J------N---- \--* EQ int $482 N001 ( 1, 1) [000046] ------------ \--* LCL_VAR ref V02 loc0 u:2 $3c3 ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ***** BB05, stmt 8 ( 16, 13) [000201] ------------ * STMT void (IL ???... ???) N009 ( 16, 13) [000200] -A-X-------- \--* JTRUE void N007 ( 1, 1) [000195] ------------ | /--* CNS_INT int 0 $40 N008 ( 14, 11) [000199] NA-X---N-U-- \--* LT int $483 N005 ( 3, 2) [000509] ------------ | /--* LCL_VAR int V35 cse1 $500 N006 ( 12, 9) [000510] -A-X-------- \--* COMMA int $500 N002 ( 5, 4) [000197] ---X-------- | /--* ARR_LENGTH int $500 N001 ( 3, 2) [000196] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N004 ( 9, 7) [000508] -A-X----R--- \--* ASG int $VN.Void N003 ( 3, 2) [000507] D------N---- \--* LCL_VAR int V35 cse1 $500 ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ***** BB06, stmt 9 ( 5, 5) [000251] ------------ * STMT void (IL ???... ???) N004 ( 5, 5) [000250] ------------ \--* JTRUE void N002 ( 1, 1) [000244] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 3, 3) [000249] N------N-U-- \--* LT int $484 N001 ( 1, 1) [000511] ------------ \--* LCL_VAR int V35 cse1 $500 ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ***** BB07, stmt 10 ( 5, 4) [000266] ------------ * STMT void (IL ???... ???) N002 ( 1, 1) [000419] ------------ | /--* CNS_INT long 16 field offset Fseq[m_arrayData] $102 N003 ( 5, 4) [000420] -------N---- | /--* ADD byref $146 N001 ( 3, 2) [000418] ------------ | | \--* LCL_VAR ref V02 loc0 u:2 $3c3 N005 ( 5, 4) [000265] -A--G---R--- \--* ASG byref $147 N004 ( 1, 1) [000264] D------N---- \--* LCL_VAR byref V13 tmp7 d:2 $146 ***** BB07, stmt 11 ( 1, 3) [000232] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000263] ------------ | /--* LCL_VAR byref V13 tmp7 u:2 (last use) $146 N003 ( 1, 3) [000230] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000229] D------N---- \--* LCL_VAR byref V22 tmp16 d:2 $146 ***** BB07, stmt 12 ( 1, 3) [000237] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000427] -------N---- | /--* LCL_VAR byref V22 tmp16 u:2 (last use) $146 N003 ( 1, 3) [000428] -A------R--- \--* ASG byref $146 N002 ( 1, 1) [000426] D------N---- \--* LCL_VAR byref V20 tmp14 d:2 $146 ***** BB07, stmt 13 ( 1, 3) [000242] ------------ * STMT void (IL ???... ???) N001 ( 1, 1) [000048] ------------ | /--* LCL_VAR int V03 loc1 u:2 $246 N003 ( 1, 3) [000241] -A------R--- \--* ASG int $246 N002 ( 1, 1) [000240] D------N---- \--* LCL_VAR int V21 tmp15 d:2 $246 ***** BB07, stmt 14 ( 10, 8) [000064] ------------ * STMT void (IL 0x041... ???) N004 ( 1, 1) [000433] -------N---- | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N006 ( 5, 4) [000434] -A--G---R--- | /--* ASG int $246 N005 ( 3, 2) [000432] D---G--N---- | | \--* LCL_VAR int (AX) V19 tmp13 N007 ( 10, 8) [000435] -A--G------- \--* COMMA void $246 N001 ( 1, 1) [000430] -------N---- | /--* LCL_VAR byref V20 tmp14 u:2 (last use) $146 N003 ( 5, 4) [000431] -A--G---R--- \--* ASG byref $146 N002 ( 3, 2) [000429] D---G--N---- \--* LCL_VAR byref (AX) V18 tmp12 ***** BB07, stmt 15 ( 10, 8) [000297] ------------ * STMT void (IL 0x042... ???) N004 ( 1, 1) [000440] -------N---- | /--* LCL_VAR int V17 tmp11 u:2 (last use) N006 ( 5, 4) [000441] -A------R--- | /--* ASG int N005 ( 3, 2) [000439] D------N---- | | \--* LCL_VAR int V24 tmp18 d:2 N007 ( 10, 8) [000442] -A---------- \--* COMMA void N001 ( 1, 1) [000437] -------N---- | /--* LCL_VAR byref V16 tmp10 u:2 (last use) N003 ( 5, 4) [000438] -A------R--- \--* ASG byref N002 ( 3, 2) [000436] D------N---- \--* LCL_VAR byref V23 tmp17 d:2 ***** BB07, stmt 16 ( 47, 35) [000289] ------------ * STMT void (IL 0x042... ???) N032 ( 47, 35) [000288] -ACXG------- \--* JTRUE void N030 ( 1, 1) [000286] ------------ | /--* CNS_INT int 0 $40 N031 ( 45, 33) [000287] JACXG--N---- \--* EQ int $485 N029 ( 43, 31) [000280] -ACXG------- \--* CALL int Span`1.TryCopyTo $24c N002 ( 3, 3) [000277] L----------- | /--* ADDR byref $1c6 N001 ( 3, 2) [000278] ----G--N---- | | \--* LCL_VAR struct(AX)(P) V04 loc2 | | \--* byref V04._pointer (offs=0x00) -> V18 tmp12 | | \--* int V04._length (offs=0x08) -> V19 tmp13 $540 N004 ( 3, 3) [000465] -A------R-L- this SETUP +--* ASG byref $1c6 N003 ( 1, 1) [000464] D------N---- | \--* LCL_VAR byref V30 tmp24 d:2 $1c6 N020 ( 3, 2) [000461] -------N---- | /--* LCL_VAR int V24 tmp18 u:2 (last use) N021 ( 8, 7) [000462] -A---------- | /--* ASG int indir assign of V28:ud:0->0 $VN.Void N019 ( 4, 4) [000460] *------N---- | | \--* IND int N017 ( 1, 1) [000458] ------------ | | | /--* CNS_INT long 8 Fseq[_length] $101 N018 ( 2, 2) [000459] -------N---- | | \--* ADD byref $14b N016 ( 1, 1) [000457] ------------ | | \--* LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N022 ( 19, 16) [000463] -A--------L- arg1 SETUP +--* COMMA void $VN.Void N013 ( 3, 2) [000454] -------N---- | | /--* LCL_VAR byref V23 tmp17 u:2 (last use) N014 ( 8, 6) [000455] -A---------- | | /--* ASG byref indir assign of V28:ud:0->0 $VN.Void N012 ( 4, 3) [000453] *------N---- | | | \--* IND byref N010 ( 1, 1) [000451] ------------ | | | | /--* CNS_INT long 0 Fseq[_pointer] $100 N011 ( 3, 3) [000452] -------N---- | | | \--* ADD byref $14a N009 ( 1, 1) [000450] ------------ | | | \--* LCL_VAR byref V29 tmp23 u:2 $1c8 N015 ( 11, 9) [000456] -A---------- | \--* COMMA void $VN.Void N006 ( 3, 3) [000446] L----------- | | /--* ADDR byref $1c8 N005 ( 3, 2) [000447] -------N---- | | | \--* LCL_VAR struct(AX) V28 tmp22 $541 N008 ( 3, 3) [000449] -A------R--- | \--* ASG byref $1c8 N007 ( 1, 1) [000448] D------N---- | \--* LCL_VAR byref V29 tmp23 d:2 $1c8 N024 ( 1, 1) [000466] ------------ this in rcx +--* LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N026 ( 3, 3) [000469] L----------- arg1 in rdx \--* ADDR byref $1ca N025 ( 3, 2) [000468] -------N---- \--* LCL_VAR struct(AX) V28 tmp22 $542 ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ***** BB08, stmt 17 ( 5, 4) [000076] ------------ * STMT void (IL 0x04A... ???) N001 ( 1, 1) [000073] ------------ | /--* LCL_VAR int V03 loc1 u:2 (last use) $246 N003 ( 5, 4) [000075] -A------R--- \--* ASG int $246 N002 ( 3, 2) [000074] D------N---- \--* LCL_VAR int V05 loc3 d:2 $246 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ***** BB09, stmt 18 ( 14, 5) [000293] ------------ * STMT void (IL 0x042... ???) N001 ( 14, 5) [000292] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} ***** BB10, stmt 19 ( 14, 5) [000204] ------------ * STMT void (IL ???... ???) N001 ( 14, 5) [000203] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} ***** BB11, stmt 20 ( 15, 7) [000256] ------------ * STMT void (IL ???... ???) N005 ( 15, 7) [000254] --CXG------- \--* CALL void ThrowHelper.ThrowArgumentNullException $VN.Void N003 ( 1, 1) [000253] ------------ arg0 in rcx \--* CNS_INT int 2 $4a ------------ BB12 [02E..039) (throw), preds={BB03} succs={} ***** BB12, stmt 21 ( 21, 19) [000089] ------------ * STMT void (IL ???... ???) N005 ( 17, 16) [000086] --C--------- | /--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 N003 ( 3, 10) [000085] ------------ arg0 in rcx | | \--* CNS_INT(h) long 0x17dd3b22ac8 method $302 N007 ( 21, 19) [000088] -AC-----R--- \--* ASG ref $346 N006 ( 3, 2) [000087] D------N---- \--* LCL_VAR ref V08 tmp2 d:2 $346 ***** BB12, stmt 22 ( 67, 38) [000093] ------------ * STMT void (IL ???... ???) N024 ( 67, 38) [000091] --CXG------- \--* CALL void IOException..ctor $VN.Void N016 ( 40, 23) [000160] --CXG------- | /--* CALL ref SR.GetResourceString $3d1 N006 ( 15, 10) [000390] --CXG------- | | | /--* CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 N004 ( 1, 4) [000388] ------------ arg0 in rcx | | | | \--* CNS_INT int 0xE904 $49 N008 ( 19, 13) [000394] -ACXG---R-L- arg0 SETUP | | +--* ASG ref $347 N007 ( 3, 2) [000393] D------N---- | | | \--* LCL_VAR ref V26 tmp20 d:2 $3cd N012 ( 3, 2) [000395] ------------ arg0 in rcx | | +--* LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ arg1 in rdx | | \--* CNS_INT ref null $VN.Null N018 ( 44, 26) [000400] -ACXG---R-L- arg1 SETUP +--* ASG ref $3d1 N017 ( 3, 2) [000399] D------N---- | \--* LCL_VAR ref V27 tmp21 d:2 $3d1 N020 ( 3, 2) [000401] ------------ arg1 in rdx +--* LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ this in rcx \--* LCL_VAR ref V08 tmp2 u:2 $346 ***** BB12, stmt 23 ( 17, 8) [000097] ------------ * STMT void (IL 0x038... ???) N005 ( 17, 8) [000096] --CXG------- \--* CALL help void HELPER.CORINFO_HELP_THROW $348 N003 ( 3, 2) [000094] ------------ arg0 in rcx \--* LCL_VAR ref V08 tmp2 u:2 (last use) $346 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} ***** BB13, stmt 24 ( 4, 7) [000343] ------------ * STMT void (IL ???... ???) N004 ( 4, 7) [000334] ---XG------- | /--* IND ref N002 ( 1, 4) [000342] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N003 ( 2, 5) [000335] ----G--N---- | | \--* ADD byref $145 N001 ( 1, 1) [000502] ------------ | | \--* LCL_VAR byref V34 cse0 $143 N006 ( 4, 7) [000332] -A-XG---R--- \--* ASG ref N005 ( 1, 1) [000333] D------N---- \--* LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} ***** BB14, stmt 25 ( 19, 13) [000350] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000344] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000345] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB14, stmt 26 ( 4, 3) [000080] ------------ * STMT void (IL 0x05B...0x05C) N002 ( 4, 3) [000079] ------------ \--* RETURN int $252 N001 ( 3, 2) [000078] ------------ \--* LCL_VAR int V05 loc3 u:2 (last use) $246 ------------ BB15 [04E..05B), preds={} succs={BB16} ***** BB15, stmt 27 ( 24, 30) [000318] ------------ * STMT void (IL 0x04E... ???) N017 ( 24, 30) [000330] -ACXG------- | /--* IND ref N015 ( 1, 4) [000328] ------------ | | | /--* CNS_INT int 888 Fseq[k__BackingField] $46 N016 ( 22, 28) [000329] -ACXG--N---- | | \--* ADD byref $145 N013 ( 1, 1) [000505] ------------ | | | /--* LCL_VAR byref V34 cse0 $143 N014 ( 21, 24) [000506] -ACXG------- | | \--* COMMA byref $143 N010 ( 20, 23) [000327] H-CXG------- | | | /--* CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 N006 ( 5, 12) [000323] #----------- arg0 in rcx | | | | +--* IND long $340 N005 ( 3, 10) [000322] ------------ | | | | | \--* CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 N007 ( 1, 4) [000324] ------------ arg1 in rdx | | | | \--* CNS_INT int 327 $45 N012 ( 20, 23) [000504] -ACXG---R--- | | \--* ASG byref $VN.Void N011 ( 1, 1) [000503] D------N---- | | \--* LCL_VAR byref V34 cse0 $143 N019 ( 24, 30) [000317] -ACXG---R--- \--* ASG ref N018 ( 1, 1) [000316] D------N---- \--* LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} ***** BB16, stmt 28 ( 19, 13) [000107] ------------ * STMT void (IL ???... ???) N012 ( 19, 13) [000104] --CXG------- \--* CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N006 ( 3, 2) [000319] ------------ this in rcx +--* LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ arg1 in rdx +--* LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ arg2 in r8 \--* CNS_INT int 0 $40 ***** BB16, stmt 29 ( 0, 0) [000109] ------------ * STMT void (IL 0x05A... ???) N001 ( 0, 0) [000108] ------------ \--* RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 20, 23) [000499] DACXG------- * STORE_LCL_VAR byref V34 cse0 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N019 ( 24, 30) [000127] DACXG------- * STORE_LCL_VAR ref V09 tmp3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 26, 15) [000495] DACXG------- * STORE_LCL_VAR ref V33 tmp27 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N018 ( 24, 16) [000032] DACXG------- * STORE_LCL_VAR int V03 loc1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000241] DA---------- * STORE_LCL_VAR int V21 tmp15 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 21, 19) [000088] DAC--------- * STORE_LCL_VAR ref V08 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 19, 13) [000394] DACXG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N018 ( 44, 26) [000400] DACXG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 20, 23) [000504] DACXG------- * STORE_LCL_VAR byref V34 cse0 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N019 ( 24, 30) [000317] DACXG------- * STORE_LCL_VAR ref V15 tmp9 d:2 *************** Exiting IR Rationalize Trees after IR Rationalize -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 $c0 N002 ( 1, 1) [000361] ------------ t361 = CNS_INT long 0 Fseq[_pointer] $100 /--* t360 byref +--* t361 long N003 ( 3, 3) [000362] -------N---- t362 = * ADD byref $140 /--* t362 byref N004 ( 4, 3) [000363] x----------- t363 = * IND byref /--* t363 byref N006 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 N007 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 (last use) $c0 N008 ( 1, 1) [000367] ------------ t367 = CNS_INT long 8 Fseq[_length] $101 /--* t366 byref +--* t367 long N009 ( 2, 2) [000368] -------N---- t368 = * ADD byref $141 /--* t368 byref N010 ( 4, 4) [000369] x----------- t369 = * IND int /--* t369 int N012 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 N005 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t133 long arg0 in rcx +--* t134 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t137 byref N012 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 $143 N015 ( 1, 4) [000138] ------------ t138 = CNS_INT int 888 Fseq[k__BackingField] $46 /--* t500 byref +--* t138 int N016 ( 22, 28) [000139] ---XG--N---- t139 = * ADD byref $145 /--* t139 byref N017 ( 24, 30) [000140] ---XG------- t140 = * IND ref /--* t140 ref N019 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t11 ref this in rcx +--* t145 int arg1 in rdx N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 /--* t13 ref N010 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 N011 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 /--* t496 ref N013 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t19 ref this in rcx +--* t20 ref arg1 in rdx +--* t150 int arg3 in r9 +--* t21 int arg2 in r8 N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 /--* t27 int N018 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 $246 /--* t34 int N002 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint $440 N003 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 /--* t155 int N004 ( 2, 3) [000041] ------------ t41 = * CAST long <- int /--* t35 long +--* t41 long N005 ( 5, 7) [000042] J------N---- t42 = * GT int /--* t42 int N006 ( 7, 9) [000043] ------------ * JTRUE void ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000165] ------------ t165 = CNS_INT ref null $VN.Null /--* t46 ref +--* t165 ref N003 ( 3, 3) [000166] J------N---- t166 = * EQ int $482 /--* t166 int N004 ( 5, 5) [000167] ------------ * JTRUE void ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} N001 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t196 ref N002 ( 5, 4) [000197] ---X-------- t197 = * ARR_LENGTH int $500 /--* t197 int N004 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 N005 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 $500 N007 ( 1, 1) [000195] ------------ t195 = CNS_INT int 0 $40 /--* t509 int +--* t195 int N008 ( 14, 11) [000199] N--X---N-U-- t199 = * LT int $483 /--* t199 int N009 ( 16, 13) [000200] ---X-------- * JTRUE void ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} N001 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 $500 N002 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 $246 /--* t511 int +--* t244 int N003 ( 3, 3) [000249] N------N-U-- t249 = * LT int $484 /--* t249 int N004 ( 5, 5) [000250] ------------ * JTRUE void ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} N001 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000419] ------------ t419 = CNS_INT long 16 field offset Fseq[m_arrayData] $102 /--* t418 ref +--* t419 long N003 ( 5, 4) [000420] -------N---- t420 = * ADD byref $146 /--* t420 byref N005 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 N001 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 (last use) $146 /--* t263 byref N003 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 N001 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 (last use) $146 /--* t427 byref N003 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 N001 ( 1, 1) [000048] ------------ t48 = LCL_VAR int V03 loc1 u:2 $246 /--* t48 int N003 ( 1, 3) [000241] DA---------- * STORE_LCL_VAR int V21 tmp15 d:2 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 (last use) $146 /--* t430 byref N003 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 N004 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t433 int N006 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 (last use) /--* t437 byref N003 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 N004 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 (last use) /--* t440 int N006 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 N010 ( 1, 1) [000451] ------------ t451 = CNS_INT long 0 Fseq[_pointer] $100 /--* t450 byref +--* t451 long N011 ( 3, 3) [000452] -------N---- t452 = * ADD byref $14a N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t452 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N017 ( 1, 1) [000458] ------------ t458 = CNS_INT long 8 Fseq[_length] $101 /--* t457 byref +--* t458 long N018 ( 2, 2) [000459] -------N---- t459 = * ADD byref $14b N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t459 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t466 byref this in rcx +--* t468 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c N030 ( 1, 1) [000286] ------------ t286 = CNS_INT int 0 $40 /--* t280 int +--* t286 int N031 ( 45, 33) [000287] J--XG--N---- t287 = * EQ int $485 /--* t287 int N032 ( 47, 35) [000288] ---XG------- * JTRUE void ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a N001 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t73 int N003 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB12 [02E..039) (throw), preds={BB03} succs={} N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 /--* t86 ref N007 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t395 ref arg0 in rcx +--* t159 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t401 ref arg1 in rdx +--* t90 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} N001 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 $143 N002 ( 1, 4) [000342] ------------ t342 = CNS_INT int 888 Fseq[k__BackingField] $46 /--* t502 byref +--* t342 int N003 ( 2, 5) [000335] ----G--N---- t335 = * ADD byref $145 /--* t335 byref N004 ( 4, 7) [000334] ---XG------- t334 = * IND ref /--* t334 ref N006 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t345 ref this in rcx +--* t347 ref arg1 in rdx +--* t349 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 (last use) $246 /--* t78 int N002 ( 4, 3) [000079] ------------ * RETURN int $252 ------------ BB15 [04E..05B), preds={} succs={BB16} ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e N005 ( 3, 10) [000322] ------------ t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t323 long arg0 in rcx +--* t324 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t327 byref N012 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 $143 N015 ( 1, 4) [000328] ------------ t328 = CNS_INT int 888 Fseq[k__BackingField] $46 /--* t505 byref +--* t328 int N016 ( 22, 28) [000329] ---XG--N---- t329 = * ADD byref $145 /--* t329 byref N017 ( 24, 30) [000330] ---XG------- t330 = * IND ref /--* t330 ref N019 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t319 ref this in rcx +--* t102 ref arg1 in rdx +--* t103 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a N001 ( 0, 0) [000108] ------------ RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Bumping outgoingArgSpaceSize to 32 for call [000137] outgoingArgSpaceSize 32 sufficient for call [000013], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000027], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000280], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000292], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000203], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000254], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000086], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000390], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000160], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000091], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000096], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000344], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000327], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000104], which needs 32 *************** In fgDebugCheckBBlist *************** In Lowering Trees before Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 $c0 N002 ( 1, 1) [000361] ------------ t361 = CNS_INT long 0 Fseq[_pointer] $100 /--* t360 byref +--* t361 long N003 ( 3, 3) [000362] -------N---- t362 = * ADD byref $140 /--* t362 byref N004 ( 4, 3) [000363] x----------- t363 = * IND byref /--* t363 byref N006 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 N007 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 (last use) $c0 N008 ( 1, 1) [000367] ------------ t367 = CNS_INT long 8 Fseq[_length] $101 /--* t366 byref +--* t367 long N009 ( 2, 2) [000368] -------N---- t368 = * ADD byref $141 /--* t368 byref N010 ( 4, 4) [000369] x----------- t369 = * IND int /--* t369 int N012 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 N005 ( 3, 10) [000132] ------------ t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t133 long arg0 in rcx +--* t134 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t137 byref N012 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 $143 N015 ( 1, 4) [000138] ------------ t138 = CNS_INT int 888 Fseq[k__BackingField] $46 /--* t500 byref +--* t138 int N016 ( 22, 28) [000139] ---XG--N---- t139 = * ADD byref $145 /--* t139 byref N017 ( 24, 30) [000140] ---XG------- t140 = * IND ref /--* t140 ref N019 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t11 ref this in rcx +--* t145 int arg1 in rdx N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 /--* t13 ref N010 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 N011 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 /--* t496 ref N013 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t19 ref this in rcx +--* t20 ref arg1 in rdx +--* t150 int arg3 in r9 +--* t21 int arg2 in r8 N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 /--* t27 int N018 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 $246 /--* t34 int N002 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint $440 N003 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 /--* t155 int N004 ( 2, 3) [000041] ------------ t41 = * CAST long <- int /--* t35 long +--* t41 long N005 ( 5, 7) [000042] J------N---- t42 = * GT int /--* t42 int N006 ( 7, 9) [000043] ------------ * JTRUE void ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000165] ------------ t165 = CNS_INT ref null $VN.Null /--* t46 ref +--* t165 ref N003 ( 3, 3) [000166] J------N---- t166 = * EQ int $482 /--* t166 int N004 ( 5, 5) [000167] ------------ * JTRUE void ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} N001 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 $3c3 [000514] ------------ t514 = CNS_INT long 8 /--* t196 ref +--* t514 long [000515] ------------ t515 = * ADD ref /--* t515 ref N002 ( 5, 4) [000197] ---X-------- t197 = * IND int $500 /--* t197 int N004 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 N005 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 $500 N007 ( 1, 1) [000195] ------------ t195 = CNS_INT int 0 $40 /--* t509 int +--* t195 int N008 ( 14, 11) [000199] N--X---N-U-- t199 = * LT int $483 /--* t199 int N009 ( 16, 13) [000200] ---X-------- * JTRUE void ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} N001 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 $500 N002 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 $246 /--* t511 int +--* t244 int N003 ( 3, 3) [000249] N------N-U-- t249 = * LT int $484 /--* t249 int N004 ( 5, 5) [000250] ------------ * JTRUE void ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} N001 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000419] ------------ t419 = CNS_INT long 16 field offset Fseq[m_arrayData] $102 /--* t418 ref +--* t419 long N003 ( 5, 4) [000420] -------N---- t420 = * ADD byref $146 /--* t420 byref N005 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 N001 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 (last use) $146 /--* t263 byref N003 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 N001 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 (last use) $146 /--* t427 byref N003 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 N001 ( 1, 1) [000048] ------------ t48 = LCL_VAR int V03 loc1 u:2 $246 /--* t48 int N003 ( 1, 3) [000241] DA---------- * STORE_LCL_VAR int V21 tmp15 d:2 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 (last use) $146 /--* t430 byref N003 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 N004 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t433 int N006 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 (last use) /--* t437 byref N003 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 N004 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 (last use) /--* t440 int N006 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 N010 ( 1, 1) [000451] ------------ t451 = CNS_INT long 0 Fseq[_pointer] $100 /--* t450 byref +--* t451 long N011 ( 3, 3) [000452] -------N---- t452 = * ADD byref $14a N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t452 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 N017 ( 1, 1) [000458] ------------ t458 = CNS_INT long 8 Fseq[_length] $101 /--* t457 byref +--* t458 long N018 ( 2, 2) [000459] -------N---- t459 = * ADD byref $14b N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t459 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t466 byref this in rcx +--* t468 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c N030 ( 1, 1) [000286] ------------ t286 = CNS_INT int 0 $40 /--* t280 int +--* t286 int N031 ( 45, 33) [000287] J--XG--N---- t287 = * EQ int $485 /--* t287 int N032 ( 47, 35) [000288] ---XG------- * JTRUE void ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a N001 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t73 int N003 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB12 [02E..039) (throw), preds={BB03} succs={} N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 /--* t86 ref N007 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t395 ref arg0 in rcx +--* t159 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t401 ref arg1 in rdx +--* t90 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} N001 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 $143 N002 ( 1, 4) [000342] ------------ t342 = CNS_INT int 888 Fseq[k__BackingField] $46 /--* t502 byref +--* t342 int N003 ( 2, 5) [000335] ----G--N---- t335 = * ADD byref $145 /--* t335 byref N004 ( 4, 7) [000334] ---XG------- t334 = * IND ref /--* t334 ref N006 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t345 ref this in rcx +--* t347 ref arg1 in rdx +--* t349 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 (last use) $246 /--* t78 int N002 ( 4, 3) [000079] ------------ * RETURN int $252 ------------ BB15 [04E..05B), preds={} succs={BB16} ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e N005 ( 3, 10) [000322] ------------ t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t323 long arg0 in rcx +--* t324 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t327 byref N012 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 $143 N015 ( 1, 4) [000328] ------------ t328 = CNS_INT int 888 Fseq[k__BackingField] $46 /--* t505 byref +--* t328 int N016 ( 22, 28) [000329] ---XG--N---- t329 = * ADD byref $145 /--* t329 byref N017 ( 24, 30) [000330] ---XG------- t330 = * IND ref /--* t330 ref N019 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t319 ref this in rcx +--* t102 ref arg1 in rdx +--* t103 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a N001 ( 0, 0) [000108] ------------ RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- Addressing mode: Base N001 ( 1, 1) [000360] ------------ * LCL_VAR byref V01 arg1 u:2 $c0 + 0 New addressing mode node: [000516] ------------ * LEA(b+0) byref Addressing mode: Base N007 ( 1, 1) [000366] ------------ * LCL_VAR byref V01 arg1 u:2 (last use) $c0 + 8 New addressing mode node: [000517] ------------ * LEA(b+8) byref No addressing mode: N005 ( 3, 10) [000132] ------------ * CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 lowering call (before): N005 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t133 long arg0 in rcx +--* t134 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000372] ----------L- * ARGPLACE long $340 lowering arg : N002 ( 0, 0) [000374] ----------L- * ARGPLACE int $45 late: ====== lowering arg : N006 ( 5, 12) [000133] #----------- * IND long $340 new node is : [000518] ------------ * PUTARG_REG long REG rcx lowering arg : N007 ( 1, 4) [000134] ------------ * CNS_INT int 327 $45 new node is : [000519] ------------ * PUTARG_REG int REG rdx lowering call (after): N005 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 /--* t133 long [000518] ------------ t518 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t134 int [000519] ------------ t519 = * PUTARG_REG int REG rdx /--* t518 long arg0 in rcx +--* t519 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 Addressing mode: Base N013 ( 1, 1) [000500] ------------ * LCL_VAR byref V34 cse0 $143 + 888 New addressing mode node: [000520] ------------ * LEA(b+888) byref lowering call (before): N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 (last use) N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t11 ref this in rcx +--* t145 int arg1 in rdx N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 objp: ====== lowering arg : N001 ( 0, 0) [000376] ----------L- * ARGPLACE ref $3c2 args: ====== lowering arg : N002 ( 0, 0) [000378] ----------L- * ARGPLACE int late: ====== lowering arg : N004 ( 1, 1) [000011] ------------ * LCL_VAR ref V09 tmp3 u:2 (last use) new node is : [000521] ------------ * PUTARG_REG ref REG rcx lowering arg : N005 ( 1, 1) [000145] ------------ * LCL_VAR int V17 tmp11 u:2 new node is : [000522] ------------ * PUTARG_REG int REG rdx New refCnts for V09: refCnt = 4, refCntWtd = 4 results of lowering call: N001 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 /--* t523 ref N002 ( 2, 2) [000524] ------------ t524 = * LEA(b+0) byref /--* t524 byref N003 ( 5, 4) [000525] ------------ t525 = * IND long /--* t525 long N004 ( 6, 5) [000526] ------------ t526 = * LEA(b+64) long /--* t526 long N005 ( 9, 7) [000527] ------------ t527 = * IND long /--* t527 long N006 ( 10, 8) [000528] ------------ t528 = * LEA(b+32) long /--* t528 long N007 ( 13, 10) [000529] ------------ t529 = * IND long lowering call (after): N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 (last use) /--* t11 ref [000521] ------------ t521 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t145 int [000522] ------------ t522 = * PUTARG_REG int REG rdx N001 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 /--* t523 ref N002 ( 2, 2) [000524] -c---------- t524 = * LEA(b+0) byref /--* t524 byref N003 ( 5, 4) [000525] ------------ t525 = * IND long /--* t525 long N004 ( 6, 5) [000526] -c---------- t526 = * LEA(b+64) long /--* t526 long N005 ( 9, 7) [000527] ------------ t527 = * IND long /--* t527 long N006 ( 10, 8) [000528] -c---------- t528 = * LEA(b+32) long /--* t528 long N007 ( 13, 10) [000529] -c---------- t529 = * IND long REG NA /--* t521 ref this in rcx +--* t522 int arg1 in rdx +--* t529 long control expr N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 lowering call (before): N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 (last use) $80 N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t19 ref this in rcx +--* t20 ref arg1 in rdx +--* t150 int arg3 in r9 +--* t21 int arg2 in r8 N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 objp: ====== lowering arg : N001 ( 0, 0) [000380] ----------L- * ARGPLACE ref $3c7 args: ====== lowering arg : N002 ( 0, 0) [000382] ----------L- * ARGPLACE ref $80 lowering arg : N003 ( 0, 0) [000386] ----------L- * ARGPLACE int $3c3 lowering arg : N004 ( 0, 0) [000384] ----------L- * ARGPLACE int $40 late: ====== lowering arg : N008 ( 1, 1) [000019] ------------ * LCL_VAR ref V00 this u:2 (last use) $80 new node is : [000530] ------------ * PUTARG_REG ref REG rcx lowering arg : N009 ( 1, 1) [000020] ------------ * LCL_VAR ref V02 loc0 u:2 $3c3 new node is : [000531] ------------ * PUTARG_REG ref REG rdx lowering arg : N010 ( 1, 1) [000150] ------------ * LCL_VAR int V17 tmp11 u:2 new node is : [000532] ------------ * PUTARG_REG int REG r9 lowering arg : N011 ( 1, 1) [000021] ------------ * CNS_INT int 0 $40 new node is : [000533] ------------ * PUTARG_REG int REG r8 New refCnts for V00: refCnt = 4, refCntWtd = 4 results of lowering call: N001 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this /--* t534 ref N002 ( 2, 2) [000535] ------------ t535 = * LEA(b+0) byref /--* t535 byref N003 ( 5, 4) [000536] ------------ t536 = * IND long /--* t536 long N004 ( 6, 5) [000537] ------------ t537 = * LEA(b+96) long /--* t537 long N005 ( 9, 7) [000538] ------------ t538 = * IND long /--* t538 long N006 ( 10, 8) [000539] ------------ t539 = * LEA(b+16) long /--* t539 long N007 ( 13, 10) [000540] ------------ t540 = * IND long lowering call (after): N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 (last use) $80 /--* t19 ref [000530] ------------ t530 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t20 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdx N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 /--* t150 int [000532] ------------ t532 = * PUTARG_REG int REG r9 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t21 int [000533] ------------ t533 = * PUTARG_REG int REG r8 N001 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this /--* t534 ref N002 ( 2, 2) [000535] -c---------- t535 = * LEA(b+0) byref /--* t535 byref N003 ( 5, 4) [000536] ------------ t536 = * IND long /--* t536 long N004 ( 6, 5) [000537] -c---------- t537 = * LEA(b+96) long /--* t537 long N005 ( 9, 7) [000538] ------------ t538 = * IND long /--* t538 long N006 ( 10, 8) [000539] -c---------- t539 = * LEA(b+16) long /--* t539 long N007 ( 13, 10) [000540] -c---------- t540 = * IND long REG NA /--* t530 ref this in rcx +--* t531 ref arg1 in rdx +--* t532 int arg3 in r9 +--* t533 int arg2 in r8 +--* t540 long control expr N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 Addressing mode: Base N001 ( 3, 2) [000196] ------------ * LCL_VAR ref V02 loc0 u:2 $3c3 + 8 New addressing mode node: [000541] ------------ * LEA(b+8) byref Addressing mode: Base N009 ( 1, 1) [000450] ------------ * LCL_VAR byref V29 tmp23 u:2 $1c8 + 0 New addressing mode node: [000542] ------------ * LEA(b+0) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 /--* t450 byref [000542] ------------ t542 = * LEA(b+0) byref N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t542 byref +--* t454 byref [000512] -A---------- * STOREIND byref Addressing mode: Base N016 ( 1, 1) [000457] ------------ * LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 + 8 New addressing mode node: [000543] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 /--* t457 byref [000543] ------------ t543 = * LEA(b+8) byref N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t543 byref +--* t461 int [000513] -A--------L- * STOREIND int lowering call (before): N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 /--* t450 byref [000542] -c---------- t542 = * LEA(b+0) byref N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t542 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 /--* t457 byref [000543] -c---------- t543 = * LEA(b+8) byref N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t543 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t466 byref this in rcx +--* t468 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c objp: ====== lowering arg : N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 args: ====== lowering arg : [000513] -A--------L- * STOREIND int late: ====== lowering arg : N024 ( 1, 1) [000466] ------------ * LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 new node is : [000544] ------------ * PUTARG_REG byref REG rcx lowering arg : N025 ( 3, 2) [000468] -------N---- * LCL_VAR_ADDR byref V28 tmp22 new node is : [000545] ------------ * PUTARG_REG byref REG rdx lowering call (after): N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 /--* t450 byref [000542] -c---------- t542 = * LEA(b+0) byref N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t542 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 /--* t457 byref [000543] -c---------- t543 = * LEA(b+8) byref N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t543 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 /--* t466 byref [000544] ------------ t544 = * PUTARG_REG byref REG rcx N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t468 byref [000545] ------------ t545 = * PUTARG_REG byref REG rdx /--* t544 byref this in rcx +--* t545 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c lowering call (before): N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void lowering call (before): N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void lowering call (before): N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000414] ----------L- * ARGPLACE int $4a late: ====== lowering arg : N003 ( 1, 1) [000253] ------------ * CNS_INT int 2 $4a new node is : [000546] ------------ * PUTARG_REG int REG rcx lowering call (after): N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int [000546] ------------ t546 = * PUTARG_REG int REG rcx /--* t546 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void lowering call (before): N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000492] ----------L- * ARGPLACE long $302 late: ====== lowering arg : N003 ( 3, 10) [000085] ------------ * CNS_INT(h) long 0x17dd3b22ac8 method $302 new node is : [000547] ------------ * PUTARG_REG long REG rcx lowering call (after): N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long [000547] ------------ t547 = * PUTARG_REG long REG rcx /--* t547 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 lowering call (before): N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 objp: ====== args: ====== lowering arg : N002 ( 0, 0) [000391] ----------L- * ARGPLACE int $49 late: ====== lowering arg : N004 ( 1, 4) [000388] ------------ * CNS_INT int 0xE904 $49 new node is : [000548] ------------ * PUTARG_REG int REG rcx lowering call (after): N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 lowering call (before): N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t395 ref arg0 in rcx +--* t159 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 objp: ====== args: ====== lowering arg : N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 lowering arg : N009 ( 0, 0) [000397] ----------L- * ARGPLACE ref $VN.Null late: ====== lowering arg : N012 ( 3, 2) [000395] ------------ * LCL_VAR ref V26 tmp20 u:2 (last use) $3cd new node is : [000549] ------------ * PUTARG_REG ref REG rcx lowering arg : N013 ( 1, 1) [000159] ------------ * CNS_INT ref null $VN.Null new node is : [000550] ------------ * PUTARG_REG ref REG rdx lowering call (after): N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd /--* t395 ref [000549] ------------ t549 = * PUTARG_REG ref REG rcx N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t159 ref [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 lowering call (before): N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd /--* t395 ref [000549] ------------ t549 = * PUTARG_REG ref REG rcx N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t159 ref [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t401 ref arg1 in rdx +--* t90 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000403] ----------L- * ARGPLACE ref $3cc args: ====== lowering arg : N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 late: ====== lowering arg : N020 ( 3, 2) [000401] ------------ * LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 new node is : [000551] ------------ * PUTARG_REG ref REG rdx lowering arg : N021 ( 3, 2) [000090] ------------ * LCL_VAR ref V08 tmp2 u:2 $346 new node is : [000552] ------------ * PUTARG_REG ref REG rcx lowering call (after): N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd /--* t395 ref [000549] ------------ t549 = * PUTARG_REG ref REG rcx N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t159 ref [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 /--* t401 ref [000551] ------------ t551 = * PUTARG_REG ref REG rdx N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t90 ref [000552] ------------ t552 = * PUTARG_REG ref REG rcx /--* t551 ref arg1 in rdx +--* t552 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void lowering call (before): N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000405] ----------L- * ARGPLACE ref $346 late: ====== lowering arg : N003 ( 3, 2) [000094] ------------ * LCL_VAR ref V08 tmp2 u:2 (last use) $346 new node is : [000553] ------------ * PUTARG_REG ref REG rcx lowering call (after): N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref [000553] ------------ t553 = * PUTARG_REG ref REG rcx /--* t553 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 Addressing mode: Base N001 ( 1, 1) [000502] ------------ * LCL_VAR byref V34 cse0 $143 + 888 New addressing mode node: [000554] ------------ * LEA(b+888) byref lowering call (before): N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t345 ref this in rcx +--* t347 ref arg1 in rdx +--* t349 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000475] ----------L- * ARGPLACE ref $3e3 args: ====== lowering arg : N002 ( 0, 0) [000477] ----------L- * ARGPLACE ref lowering arg : N003 ( 0, 0) [000479] ----------L- * ARGPLACE int $3c3 late: ====== lowering arg : N006 ( 3, 2) [000345] ------------ * LCL_VAR ref V15 tmp9 u:3 (last use) new node is : [000555] ------------ * PUTARG_REG ref REG rcx lowering arg : N007 ( 1, 1) [000347] ------------ * LCL_VAR ref V02 loc0 u:2 (last use) $3c3 new node is : [000556] ------------ * PUTARG_REG ref REG rdx lowering arg : N008 ( 1, 1) [000349] ------------ * CNS_INT int 0 $40 new node is : [000557] ------------ * PUTARG_REG int REG r8 lowering call (after): N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) /--* t345 ref [000555] ------------ t555 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t347 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t349 int [000557] ------------ t557 = * PUTARG_REG int REG r8 /--* t555 ref this in rcx +--* t556 ref arg1 in rdx +--* t557 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void lowering GT_RETURN N002 ( 4, 3) [000079] ------------ * RETURN int $252 ============No addressing mode: N005 ( 3, 10) [000322] ------------ * CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 lowering call (before): N005 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t323 long arg0 in rcx +--* t324 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000481] ----------L- * ARGPLACE long $340 lowering arg : N002 ( 0, 0) [000483] ----------L- * ARGPLACE int $45 late: ====== lowering arg : N006 ( 5, 12) [000323] #----------- * IND long $340 new node is : [000558] ------------ * PUTARG_REG long REG rcx lowering arg : N007 ( 1, 4) [000324] ------------ * CNS_INT int 327 $45 new node is : [000559] ------------ * PUTARG_REG int REG rdx lowering call (after): N005 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 /--* t323 long [000558] ------------ t558 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t324 int [000559] ------------ t559 = * PUTARG_REG int REG rdx /--* t558 long arg0 in rcx +--* t559 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 Addressing mode: Base N013 ( 1, 1) [000505] ------------ * LCL_VAR byref V34 cse0 $143 + 888 New addressing mode node: [000560] ------------ * LEA(b+888) byref lowering call (before): N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t319 ref this in rcx +--* t102 ref arg1 in rdx +--* t103 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [000485] ----------L- * ARGPLACE ref $3de args: ====== lowering arg : N002 ( 0, 0) [000487] ----------L- * ARGPLACE ref lowering arg : N003 ( 0, 0) [000489] ----------L- * ARGPLACE int $3c3 late: ====== lowering arg : N006 ( 3, 2) [000319] ------------ * LCL_VAR ref V15 tmp9 u:2 (last use) new node is : [000561] ------------ * PUTARG_REG ref REG rcx lowering arg : N007 ( 1, 1) [000102] ------------ * LCL_VAR ref V02 loc0 u:2 (last use) $3c3 new node is : [000562] ------------ * PUTARG_REG ref REG rdx lowering arg : N008 ( 1, 1) [000103] ------------ * CNS_INT int 0 $40 new node is : [000563] ------------ * PUTARG_REG int REG r8 lowering call (after): N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) /--* t319 ref [000561] ------------ t561 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t102 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t103 int [000563] ------------ t563 = * PUTARG_REG int REG r8 /--* t561 ref this in rcx +--* t562 ref arg1 in rdx +--* t563 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void Lower has completed modifying nodes. -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 $c0 /--* t360 byref [000516] -c---------- t516 = * LEA(b+0) byref /--* t516 byref N004 ( 4, 3) [000363] x----------- t363 = * IND byref /--* t363 byref N006 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 N007 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 (last use) $c0 /--* t366 byref [000517] -c---------- t517 = * LEA(b+8) byref /--* t517 byref N010 ( 4, 4) [000369] x----------- t369 = * IND int /--* t369 int N012 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 N005 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 /--* t133 long [000518] ------------ t518 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t134 int [000519] ------------ t519 = * PUTARG_REG int REG rdx /--* t518 long arg0 in rcx +--* t519 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t137 byref N012 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 $143 /--* t500 byref [000520] -c---------- t520 = * LEA(b+888) byref /--* t520 byref N017 ( 24, 30) [000140] ---XG------- t140 = * IND ref /--* t140 ref N019 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 (last use) /--* t11 ref [000521] ------------ t521 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t145 int [000522] ------------ t522 = * PUTARG_REG int REG rdx N001 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 /--* t523 ref N002 ( 2, 2) [000524] -c---------- t524 = * LEA(b+0) byref /--* t524 byref N003 ( 5, 4) [000525] ------------ t525 = * IND long /--* t525 long N004 ( 6, 5) [000526] -c---------- t526 = * LEA(b+64) long /--* t526 long N005 ( 9, 7) [000527] ------------ t527 = * IND long /--* t527 long N006 ( 10, 8) [000528] -c---------- t528 = * LEA(b+32) long /--* t528 long N007 ( 13, 10) [000529] -c---------- t529 = * IND long REG NA /--* t521 ref this in rcx +--* t522 int arg1 in rdx +--* t529 long control expr N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 /--* t13 ref N010 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 N011 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 /--* t496 ref N013 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 (last use) $80 /--* t19 ref [000530] ------------ t530 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t20 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdx N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 /--* t150 int [000532] ------------ t532 = * PUTARG_REG int REG r9 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t21 int [000533] ------------ t533 = * PUTARG_REG int REG r8 N001 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this /--* t534 ref N002 ( 2, 2) [000535] -c---------- t535 = * LEA(b+0) byref /--* t535 byref N003 ( 5, 4) [000536] ------------ t536 = * IND long /--* t536 long N004 ( 6, 5) [000537] -c---------- t537 = * LEA(b+96) long /--* t537 long N005 ( 9, 7) [000538] ------------ t538 = * IND long /--* t538 long N006 ( 10, 8) [000539] -c---------- t539 = * LEA(b+16) long /--* t539 long N007 ( 13, 10) [000540] -c---------- t540 = * IND long REG NA /--* t530 ref this in rcx +--* t531 ref arg1 in rdx +--* t532 int arg3 in r9 +--* t533 int arg2 in r8 +--* t540 long control expr N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 /--* t27 int N018 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 $246 /--* t34 int N002 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint $440 N003 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 /--* t155 int N004 ( 2, 3) [000041] ------------ t41 = * CAST long <- int /--* t35 long +--* t41 long N005 ( 5, 7) [000042] J------N---- * GT void N006 ( 7, 9) [000043] ------------ * JTRUE void ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 N001 ( 1, 1) [000046] -c---------- t46 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000165] -c---------- t165 = CNS_INT ref null $VN.Null /--* t46 ref +--* t165 ref N003 ( 3, 3) [000166] J------N---- * EQ void $482 N004 ( 5, 5) [000167] ------------ * JTRUE void ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} N001 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t196 ref [000541] -c---------- t541 = * LEA(b+8) byref /--* t541 byref N002 ( 5, 4) [000197] ---X-------- t197 = * IND int $500 /--* t197 int N004 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 N005 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 $500 N007 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 0 $40 /--* t509 int +--* t195 int N008 ( 14, 11) [000199] N--X---N-U-- * LT void $483 N009 ( 16, 13) [000200] ---X-------- * JTRUE void ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} N001 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 $500 N002 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 $246 /--* t511 int +--* t244 int N003 ( 3, 3) [000249] N------N-U-- * LT void $484 N004 ( 5, 5) [000250] ------------ * JTRUE void ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} N001 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000419] -c---------- t419 = CNS_INT long 16 field offset Fseq[m_arrayData] $102 /--* t418 ref +--* t419 long N003 ( 5, 4) [000420] -------N---- t420 = * ADD byref $146 /--* t420 byref N005 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 N001 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 (last use) $146 /--* t263 byref N003 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 N001 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 (last use) $146 /--* t427 byref N003 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 N001 ( 1, 1) [000048] ------------ t48 = LCL_VAR int V03 loc1 u:2 $246 /--* t48 int N003 ( 1, 3) [000241] DA---------- * STORE_LCL_VAR int V21 tmp15 d:2 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 (last use) $146 /--* t430 byref N003 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 N004 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t433 int N006 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 (last use) /--* t437 byref N003 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 N004 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 (last use) /--* t440 int N006 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 /--* t450 byref [000542] -c---------- t542 = * LEA(b+0) byref N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t542 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 /--* t457 byref [000543] -c---------- t543 = * LEA(b+8) byref N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t543 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 /--* t466 byref [000544] ------------ t544 = * PUTARG_REG byref REG rcx N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t468 byref [000545] ------------ t545 = * PUTARG_REG byref REG rdx /--* t544 byref this in rcx +--* t545 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c N030 ( 1, 1) [000286] -c---------- t286 = CNS_INT int 0 $40 /--* t280 int +--* t286 int N031 ( 45, 33) [000287] J--XG--N---- * EQ void $485 N032 ( 47, 35) [000288] ---XG------- * JTRUE void ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a N001 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t73 int N003 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int [000546] ------------ t546 = * PUTARG_REG int REG rcx /--* t546 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB12 [02E..039) (throw), preds={BB03} succs={} N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long [000547] ------------ t547 = * PUTARG_REG long REG rcx /--* t547 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 /--* t86 ref N007 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd /--* t395 ref [000549] ------------ t549 = * PUTARG_REG ref REG rcx N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t159 ref [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 /--* t401 ref [000551] ------------ t551 = * PUTARG_REG ref REG rdx N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t90 ref [000552] ------------ t552 = * PUTARG_REG ref REG rcx /--* t551 ref arg1 in rdx +--* t552 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref [000553] ------------ t553 = * PUTARG_REG ref REG rcx /--* t553 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} N001 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 $143 /--* t502 byref [000554] -c---------- t554 = * LEA(b+888) byref /--* t554 byref N004 ( 4, 7) [000334] ---XG------- t334 = * IND ref /--* t334 ref N006 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) /--* t345 ref [000555] ------------ t555 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t347 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t349 int [000557] ------------ t557 = * PUTARG_REG int REG r8 /--* t555 ref this in rcx +--* t556 ref arg1 in rdx +--* t557 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 (last use) $246 /--* t78 int N002 ( 4, 3) [000079] ------------ * RETURN int $252 ------------ BB15 [04E..05B), preds={} succs={BB16} ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e N005 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 /--* t323 long [000558] ------------ t558 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t324 int [000559] ------------ t559 = * PUTARG_REG int REG rdx /--* t558 long arg0 in rcx +--* t559 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t327 byref N012 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 $143 /--* t505 byref [000560] -c---------- t560 = * LEA(b+888) byref /--* t560 byref N017 ( 24, 30) [000330] ---XG------- t330 = * IND ref /--* t330 ref N019 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) /--* t319 ref [000561] ------------ t561 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t102 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t103 int [000563] ------------ t563 = * PUTARG_REG int REG r8 /--* t561 ref this in rcx +--* t562 ref arg1 in rdx +--* t563 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a N001 ( 0, 0) [000108] ------------ RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 byref ld-addr-op ; V02 loc0 ref do-not-enreg[H] class-hnd ; V03 loc1 int ; V04 loc2 struct (16) do-not-enreg[XS] addr-exposed ld-addr-op ; V05 loc3 int ; V06 tmp0 ref class-hnd ; V07 tmp1 struct (16) ; V08 tmp2 ref class-hnd exact ; V09 tmp3 ref class-hnd ; V10 tmp4 ubyte ld-addr-op ; V11 tmp5 ref class-hnd exact ; V12 tmp6 struct ( 8) ; V13 tmp7 byref ; V14 tmp8 struct (16) ; V15 tmp9 ref class-hnd ; V16 tmp10 byref V25._pointer(offs=0x00) P-INDEP ; V17 tmp11 int V25._length(offs=0x08) P-INDEP ; V18 tmp12 byref do-not-enreg[X] addr-exposed V04._pointer(offs=0x00) P-DEP ; V19 tmp13 int do-not-enreg[X] addr-exposed V04._length(offs=0x08) P-DEP ; V20 tmp14 byref V07._pointer(offs=0x00) P-INDEP ; V21 tmp15 int V07._length(offs=0x08) P-INDEP ; V22 tmp16 byref V12._value(offs=0x00) P-INDEP ; V23 tmp17 byref V14._pointer(offs=0x00) P-INDEP ; V24 tmp18 int V14._length(offs=0x08) P-INDEP ; V25 tmp19 struct (16) ; V26 tmp20 ref ; V27 tmp21 ref ; V28 tmp22 struct (16) do-not-enreg[XSB] addr-exposed ; V29 tmp23 byref stack-byref ; V30 tmp24 byref ; V31 OutArgs lclBlk (32) ; V32 PSPSym long do-not-enreg[X] addr-exposed ; V33 tmp27 ref ; V34 cse0 byref ; V35 cse1 int In fgLocalVarLivenessInit, sorting locals refCnt table for 'Read': V01 arg1 [ byref]: refCnt = 8, refCntWtd = 8 pref [rdx] V02 loc0 [ ref]: refCnt = 9, refCntWtd = 7 V34 cse0 [ byref]: refCnt = 10, refCntWtd = 6 V03 loc1 [ int]: refCnt = 7, refCntWtd = 6 V17 tmp11 [ int]: refCnt = 5, refCntWtd = 6 V00 this [ ref]: refCnt = 4, refCntWtd = 4 pref [rcx] V13 tmp7 [ byref]: refCnt = 3, refCntWtd = 6 V29 tmp23 [ byref]: refCnt = 3, refCntWtd = 6 V09 tmp3 [ ref]: refCnt = 4, refCntWtd = 4 V30 tmp24 [ byref]: refCnt = 2, refCntWtd = 4 V15 tmp9 [ ref]: refCnt = 6, refCntWtd = 3 V35 cse1 [ int]: refCnt = 6, refCntWtd = 3 V16 tmp10 [ byref]: refCnt = 2, refCntWtd = 3 V20 tmp14 [ byref]: refCnt = 2, refCntWtd = 2 V22 tmp16 [ byref]: refCnt = 2, refCntWtd = 2 V23 tmp17 [ byref]: refCnt = 2, refCntWtd = 2 V33 tmp27 [ ref]: refCnt = 2, refCntWtd = 2 V05 loc3 [ int]: refCnt = 2, refCntWtd = 2 V24 tmp18 [ int]: refCnt = 2, refCntWtd = 2 V21 tmp15 [ int]: refCnt = 1, refCntWtd = 1 V08 tmp2 [ ref]: refCnt = 3, refCntWtd = 0 V26 tmp20 [ ref]: refCnt = 2, refCntWtd = 0 V27 tmp21 [ ref]: refCnt = 2, refCntWtd = 0 V28 tmp22 [struct]: refCnt = 3, refCntWtd = 6 V04 loc2 [struct]: refCnt = 3, refCntWtd = 3 V18 tmp12 [ byref]: refCnt = 2, refCntWtd = 2 V19 tmp13 [ int]: refCnt = 2, refCntWtd = 2 V31 OutArgs [lclBlk]: refCnt = 1, refCntWtd = 1 V32 PSPSym [ long]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V01 } + ByrefExposed + GcHeap DEF(2)={ V17 V16} BB02 USE(1)={ V17 } + ByrefExposed + GcHeap DEF(4)={V02 V34 V09 V33} + ByrefExposed* + GcHeap* BB03 USE(3)={V02 V17 V00} + ByrefExposed + GcHeap DEF(1)={ V03 } + ByrefExposed* + GcHeap* BB04 USE(1)={V02} DEF(0)={ } BB05 USE(1)={V02 } + ByrefExposed + GcHeap DEF(1)={ V35} BB06 USE(2)={V03 V35} DEF(0)={ } BB07 USE(4)={V02 V03 V17 V16 } + ByrefExposed + GcHeap DEF(8)={ V13 V29 V30 V20 V22 V23 V24 V21} + ByrefExposed* + GcHeap* BB08 USE(1)={V03 } DEF(1)={ V05} BB09 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB10 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB11 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB12 USE(0)={ } + ByrefExposed + GcHeap DEF(3)={V08 V26 V27} + ByrefExposed* + GcHeap* BB13 USE(1)={V34 } + ByrefExposed + GcHeap DEF(1)={ V15} BB14 USE(3)={V02 V15 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB15 USE(0)={ } + ByrefExposed + GcHeap DEF(2)={V34 V15} + ByrefExposed* + GcHeap* BB16 USE(2)={V02 V15} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states diverge *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V01 V00 } + ByrefExposed + GcHeap OUT(3)={ V17 V00 V16} + ByrefExposed + GcHeap BB02 IN (3)={ V17 V00 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V17 V00 V16} + ByrefExposed + GcHeap BB03 IN (5)={V02 V34 V17 V00 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap BB04 IN (5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap BB05 IN (5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap OUT(6)={V02 V34 V03 V17 V35 V16} + ByrefExposed + GcHeap BB06 IN (6)={V02 V34 V03 V17 V35 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap BB07 IN (5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap OUT(3)={V02 V34 V03 } + ByrefExposed + GcHeap BB08 IN (3)={V02 V34 V03 } + ByrefExposed + GcHeap OUT(3)={V02 V34 V05} + ByrefExposed + GcHeap BB09 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB10 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB11 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB12 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap BB13 IN (3)={V02 V34 V05} + ByrefExposed + GcHeap OUT(3)={V02 V15 V05} + ByrefExposed + GcHeap BB14 IN (3)={V02 V15 V05} + ByrefExposed + GcHeap OUT(0)={ } BB15 IN (1)={V02 } + ByrefExposed + GcHeap OUT(2)={V02 V15} + ByrefExposed + GcHeap BB16 IN (2)={V02 V15} + ByrefExposed + GcHeap OUT(0)={ } Local V02 should not be enregistered because: live in/out of a handler Removing dead store: N003 ( 1, 3) [000241] DA---------- * STORE_LCL_VAR int V21 tmp15 d:2 (last use) New refCnts for V21: refCnt = 0, refCntWtd = 0 Removing dead LclVar use: N001 ( 1, 1) [000048] ------------ * LCL_VAR int V03 loc1 u:2 $246 New refCnts for V03: refCnt = 6, refCntWtd = 5 In fgLocalVarLiveness, setting lvaSortAgain back to false (set during dead-code removal) *************** In fgUpdateFlowGraph() Before updating the flow graph: -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Liveness pass finished after lowering, IR: lvasortagain = 0 -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 $c0 /--* t360 byref [000516] -c---------- t516 = * LEA(b+0) byref /--* t516 byref N004 ( 4, 3) [000363] x----------- t363 = * IND byref /--* t363 byref N006 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 N007 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 (last use) $c0 /--* t366 byref [000517] -c---------- t517 = * LEA(b+8) byref /--* t517 byref N010 ( 4, 4) [000369] x----------- t369 = * IND int /--* t369 int N012 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 N005 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 /--* t133 long [000518] ------------ t518 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t134 int [000519] ------------ t519 = * PUTARG_REG int REG rdx /--* t518 long arg0 in rcx +--* t519 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t137 byref N012 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 $143 /--* t500 byref [000520] -c---------- t520 = * LEA(b+888) byref /--* t520 byref N017 ( 24, 30) [000140] ---XG------- t140 = * IND ref /--* t140 ref N019 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 /--* t11 ref [000521] ------------ t521 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t145 int [000522] ------------ t522 = * PUTARG_REG int REG rdx N001 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 (last use) /--* t523 ref N002 ( 2, 2) [000524] -c---------- t524 = * LEA(b+0) byref /--* t524 byref N003 ( 5, 4) [000525] ------------ t525 = * IND long /--* t525 long N004 ( 6, 5) [000526] -c---------- t526 = * LEA(b+64) long /--* t526 long N005 ( 9, 7) [000527] ------------ t527 = * IND long /--* t527 long N006 ( 10, 8) [000528] -c---------- t528 = * LEA(b+32) long /--* t528 long N007 ( 13, 10) [000529] -c---------- t529 = * IND long REG NA /--* t521 ref this in rcx +--* t522 int arg1 in rdx +--* t529 long control expr N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 /--* t13 ref N010 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 N011 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 /--* t496 ref N013 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 $80 /--* t19 ref [000530] ------------ t530 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t20 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdx N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 /--* t150 int [000532] ------------ t532 = * PUTARG_REG int REG r9 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t21 int [000533] ------------ t533 = * PUTARG_REG int REG r8 N001 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this (last use) /--* t534 ref N002 ( 2, 2) [000535] -c---------- t535 = * LEA(b+0) byref /--* t535 byref N003 ( 5, 4) [000536] ------------ t536 = * IND long /--* t536 long N004 ( 6, 5) [000537] -c---------- t537 = * LEA(b+96) long /--* t537 long N005 ( 9, 7) [000538] ------------ t538 = * IND long /--* t538 long N006 ( 10, 8) [000539] -c---------- t539 = * LEA(b+16) long /--* t539 long N007 ( 13, 10) [000540] -c---------- t540 = * IND long REG NA /--* t530 ref this in rcx +--* t531 ref arg1 in rdx +--* t532 int arg3 in r9 +--* t533 int arg2 in r8 +--* t540 long control expr N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 /--* t27 int N018 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 $246 /--* t34 int N002 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint $440 N003 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 /--* t155 int N004 ( 2, 3) [000041] ------------ t41 = * CAST long <- int /--* t35 long +--* t41 long N005 ( 5, 7) [000042] J------N---- * GT void N006 ( 7, 9) [000043] ------------ * JTRUE void ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 N001 ( 1, 1) [000046] -c---------- t46 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000165] -c---------- t165 = CNS_INT ref null $VN.Null /--* t46 ref +--* t165 ref N003 ( 3, 3) [000166] J------N---- * EQ void $482 N004 ( 5, 5) [000167] ------------ * JTRUE void ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} N001 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t196 ref [000541] -c---------- t541 = * LEA(b+8) byref /--* t541 byref N002 ( 5, 4) [000197] ---X-------- t197 = * IND int $500 /--* t197 int N004 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 N005 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 $500 N007 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 0 $40 /--* t509 int +--* t195 int N008 ( 14, 11) [000199] N--X---N-U-- * LT void $483 N009 ( 16, 13) [000200] ---X-------- * JTRUE void ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} N001 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 (last use) $500 N002 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 $246 /--* t511 int +--* t244 int N003 ( 3, 3) [000249] N------N-U-- * LT void $484 N004 ( 5, 5) [000250] ------------ * JTRUE void ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} N001 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000419] -c---------- t419 = CNS_INT long 16 field offset Fseq[m_arrayData] $102 /--* t418 ref +--* t419 long N003 ( 5, 4) [000420] -------N---- t420 = * ADD byref $146 /--* t420 byref N005 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 N001 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 (last use) $146 /--* t263 byref N003 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 N001 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 (last use) $146 /--* t427 byref N003 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 (last use) $146 /--* t430 byref N003 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 N004 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 $246 /--* t433 int N006 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 (last use) /--* t437 byref N003 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 N004 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 (last use) /--* t440 int N006 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 /--* t450 byref [000542] -c---------- t542 = * LEA(b+0) byref N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t542 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 /--* t457 byref [000543] -c---------- t543 = * LEA(b+8) byref N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t543 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 /--* t466 byref [000544] ------------ t544 = * PUTARG_REG byref REG rcx N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t468 byref [000545] ------------ t545 = * PUTARG_REG byref REG rdx /--* t544 byref this in rcx +--* t545 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c N030 ( 1, 1) [000286] -c---------- t286 = CNS_INT int 0 $40 /--* t280 int +--* t286 int N031 ( 45, 33) [000287] J--XG--N---- * EQ void $485 N032 ( 47, 35) [000288] ---XG------- * JTRUE void ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a N001 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t73 int N003 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int [000546] ------------ t546 = * PUTARG_REG int REG rcx /--* t546 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB12 [02E..039) (throw), preds={BB03} succs={} N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long [000547] ------------ t547 = * PUTARG_REG long REG rcx /--* t547 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 /--* t86 ref N007 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd /--* t395 ref [000549] ------------ t549 = * PUTARG_REG ref REG rcx N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t159 ref [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 /--* t401 ref [000551] ------------ t551 = * PUTARG_REG ref REG rdx N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t90 ref [000552] ------------ t552 = * PUTARG_REG ref REG rcx /--* t551 ref arg1 in rdx +--* t552 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref [000553] ------------ t553 = * PUTARG_REG ref REG rcx /--* t553 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} N001 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 (last use) $143 /--* t502 byref [000554] -c---------- t554 = * LEA(b+888) byref /--* t554 byref N004 ( 4, 7) [000334] ---XG------- t334 = * IND ref /--* t334 ref N006 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) /--* t345 ref [000555] ------------ t555 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t347 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t349 int [000557] ------------ t557 = * PUTARG_REG int REG r8 /--* t555 ref this in rcx +--* t556 ref arg1 in rdx +--* t557 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 (last use) $246 /--* t78 int N002 ( 4, 3) [000079] ------------ * RETURN int $252 ------------ BB15 [04E..05B), preds={} succs={BB16} ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e N005 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 /--* t323 long [000558] ------------ t558 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t324 int [000559] ------------ t559 = * PUTARG_REG int REG rdx /--* t558 long arg0 in rcx +--* t559 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t327 byref N012 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 (last use) $143 /--* t505 byref [000560] -c---------- t560 = * LEA(b+888) byref /--* t560 byref N017 ( 24, 30) [000330] ---XG------- t330 = * IND ref /--* t330 ref N019 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) /--* t319 ref [000561] ------------ t561 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t102 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t103 int [000563] ------------ t563 = * PUTARG_REG int REG r8 /--* t561 ref this in rcx +--* t562 ref arg1 in rdx +--* t563 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a N001 ( 0, 0) [000108] ------------ RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- *************** Exiting Lowering Trees after Lowering -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N001 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 $c0 /--* t360 byref [000516] -c---------- t516 = * LEA(b+0) byref /--* t516 byref N004 ( 4, 3) [000363] x----------- t363 = * IND byref /--* t363 byref N006 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 N007 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 (last use) $c0 /--* t366 byref [000517] -c---------- t517 = * LEA(b+8) byref /--* t517 byref N010 ( 4, 4) [000369] x----------- t369 = * IND int /--* t369 int N012 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 ------------ BB02 [000..012), preds={BB01} succs={BB03} ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 N005 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t132 long N006 ( 5, 12) [000133] #----------- t133 = * IND long $340 /--* t133 long [000518] ------------ t518 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 $45 /--* t134 int [000519] ------------ t519 = * PUTARG_REG int REG rdx /--* t518 long arg0 in rcx +--* t519 int arg1 in rdx N010 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t137 byref N012 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 $143 /--* t500 byref [000520] -c---------- t520 = * LEA(b+888) byref /--* t520 byref N017 ( 24, 30) [000140] ---XG------- t140 = * IND ref /--* t140 ref N019 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 N004 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 /--* t11 ref [000521] ------------ t521 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 /--* t145 int [000522] ------------ t522 = * PUTARG_REG int REG rdx N001 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 (last use) /--* t523 ref N002 ( 2, 2) [000524] -c---------- t524 = * LEA(b+0) byref /--* t524 byref N003 ( 5, 4) [000525] ------------ t525 = * IND long /--* t525 long N004 ( 6, 5) [000526] -c---------- t526 = * LEA(b+64) long /--* t526 long N005 ( 9, 7) [000527] ------------ t527 = * IND long /--* t527 long N006 ( 10, 8) [000528] -c---------- t528 = * LEA(b+32) long /--* t528 long N007 ( 13, 10) [000529] -c---------- t529 = * IND long REG NA /--* t521 ref this in rcx +--* t522 int arg1 in rdx +--* t529 long control expr N008 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 /--* t13 ref N010 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 N011 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 (last use) $3c3 /--* t496 ref N013 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} N008 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 $80 /--* t19 ref [000530] ------------ t530 = * PUTARG_REG ref REG rcx N009 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t20 ref [000531] ------------ t531 = * PUTARG_REG ref REG rdx N010 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 /--* t150 int [000532] ------------ t532 = * PUTARG_REG int REG r9 N011 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 $40 /--* t21 int [000533] ------------ t533 = * PUTARG_REG int REG r8 N001 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this (last use) /--* t534 ref N002 ( 2, 2) [000535] -c---------- t535 = * LEA(b+0) byref /--* t535 byref N003 ( 5, 4) [000536] ------------ t536 = * IND long /--* t536 long N004 ( 6, 5) [000537] -c---------- t537 = * LEA(b+96) long /--* t537 long N005 ( 9, 7) [000538] ------------ t538 = * IND long /--* t538 long N006 ( 10, 8) [000539] -c---------- t539 = * LEA(b+16) long /--* t539 long N007 ( 13, 10) [000540] -c---------- t540 = * IND long REG NA /--* t530 ref this in rcx +--* t531 ref arg1 in rdx +--* t532 int arg3 in r9 +--* t533 int arg2 in r8 +--* t540 long control expr N016 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 /--* t27 int N018 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 N001 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 $246 /--* t34 int N002 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint $440 N003 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 /--* t155 int N004 ( 2, 3) [000041] ------------ t41 = * CAST long <- int /--* t35 long +--* t41 long N005 ( 5, 7) [000042] J------N---- * GT void N006 ( 7, 9) [000043] ------------ * JTRUE void ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 N001 ( 1, 1) [000046] -c---------- t46 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000165] -c---------- t165 = CNS_INT ref null $VN.Null /--* t46 ref +--* t165 ref N003 ( 3, 3) [000166] J------N---- * EQ void $482 N004 ( 5, 5) [000167] ------------ * JTRUE void ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} N001 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 $3c3 /--* t196 ref [000541] -c---------- t541 = * LEA(b+8) byref /--* t541 byref N002 ( 5, 4) [000197] ---X-------- t197 = * IND int $500 /--* t197 int N004 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 N005 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 $500 N007 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 0 $40 /--* t509 int +--* t195 int N008 ( 14, 11) [000199] N--X---N-U-- * LT void $483 N009 ( 16, 13) [000200] ---X-------- * JTRUE void ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} N001 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 (last use) $500 N002 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 $246 /--* t511 int +--* t244 int N003 ( 3, 3) [000249] N------N-U-- * LT void $484 N004 ( 5, 5) [000250] ------------ * JTRUE void ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} N001 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 $3c3 N002 ( 1, 1) [000419] -c---------- t419 = CNS_INT long 16 field offset Fseq[m_arrayData] $102 /--* t418 ref +--* t419 long N003 ( 5, 4) [000420] -------N---- t420 = * ADD byref $146 /--* t420 byref N005 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 N001 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 (last use) $146 /--* t263 byref N003 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 N001 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 (last use) $146 /--* t427 byref N003 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 (last use) $146 /--* t430 byref N003 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 N004 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 $246 /--* t433 int N006 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 (last use) /--* t437 byref N003 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 N004 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 (last use) /--* t440 int N006 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 /--* t278 byref N004 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 N005 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 /--* t447 byref N008 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 N009 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 $1c8 /--* t450 byref [000542] -c---------- t542 = * LEA(b+0) byref N013 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 (last use) /--* t542 byref +--* t454 byref [000512] -A---------- * STOREIND byref N016 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 (last use) $1c8 /--* t457 byref [000543] -c---------- t543 = * LEA(b+8) byref N020 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 (last use) /--* t543 byref +--* t461 int [000513] -A--------L- * STOREIND int N024 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 (last use) $1c6 /--* t466 byref [000544] ------------ t544 = * PUTARG_REG byref REG rcx N025 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 /--* t468 byref [000545] ------------ t545 = * PUTARG_REG byref REG rdx /--* t544 byref this in rcx +--* t545 byref arg1 in rdx N029 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c N030 ( 1, 1) [000286] -c---------- t286 = CNS_INT int 0 $40 /--* t280 int +--* t286 int N031 ( 45, 33) [000287] J--XG--N---- * EQ void $485 N032 ( 47, 35) [000288] ---XG------- * JTRUE void ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a N001 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 (last use) $246 /--* t73 int N003 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 ------------ BB09 [042..043) (throw), preds={BB07} succs={} ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 N001 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} N001 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} N003 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 $4a /--* t253 int [000546] ------------ t546 = * PUTARG_REG int REG rcx /--* t546 int arg0 in rcx N005 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB12 [02E..039) (throw), preds={BB03} succs={} N003 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method $302 /--* t85 long [000547] ------------ t547 = * PUTARG_REG long REG rcx /--* t547 long arg0 in rcx N005 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 /--* t86 ref N007 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 N004 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 $49 /--* t388 int [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N006 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N008 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 N012 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 (last use) $3cd /--* t395 ref [000549] ------------ t549 = * PUTARG_REG ref REG rcx N013 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null $VN.Null /--* t159 ref [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N016 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N018 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 N020 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 (last use) $3d1 /--* t401 ref [000551] ------------ t551 = * PUTARG_REG ref REG rdx N021 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 $346 /--* t90 ref [000552] ------------ t552 = * PUTARG_REG ref REG rcx /--* t551 ref arg1 in rdx +--* t552 ref this in rcx N024 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 N003 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 (last use) $346 /--* t94 ref [000553] ------------ t553 = * PUTARG_REG ref REG rcx /--* t553 ref arg0 in rcx N005 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} N001 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 (last use) $143 /--* t502 byref [000554] -c---------- t554 = * LEA(b+888) byref /--* t554 byref N004 ( 4, 7) [000334] ---XG------- t334 = * IND ref /--* t334 ref N006 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 ------------ BB14 [05B..05D) (return), preds={BB13} succs={} N006 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 (last use) /--* t345 ref [000555] ------------ t555 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t347 ref [000556] ------------ t556 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 $40 /--* t349 int [000557] ------------ t557 = * PUTARG_REG int REG r8 /--* t555 ref this in rcx +--* t556 ref arg1 in rdx +--* t557 int arg2 in r8 N012 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b N001 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 (last use) $246 /--* t78 int N002 ( 4, 3) [000079] ------------ * RETURN int $252 ------------ BB15 [04E..05B), preds={} succs={BB16} ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e N005 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid $300 /--* t322 long N006 ( 5, 12) [000323] #----------- t323 = * IND long $340 /--* t323 long [000558] ------------ t558 = * PUTARG_REG long REG rcx N007 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 $45 /--* t324 int [000559] ------------ t559 = * PUTARG_REG int REG rdx /--* t558 long arg0 in rcx +--* t559 int arg1 in rdx N010 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t327 byref N012 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 N013 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 (last use) $143 /--* t505 byref [000560] -c---------- t560 = * LEA(b+888) byref /--* t560 byref N017 ( 24, 30) [000330] ---XG------- t330 = * IND ref /--* t330 ref N019 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 ------------ BB16 [???..???) (finret), preds={BB15} succs={} N006 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 (last use) /--* t319 ref [000561] ------------ t561 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 (last use) $3c3 /--* t102 ref [000562] ------------ t562 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 $40 /--* t103 int [000563] ------------ t563 = * PUTARG_REG int REG r8 /--* t561 ref this in rcx +--* t562 ref arg1 in rdx +--* t563 int arg2 in r8 N012 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a N001 ( 0, 0) [000108] ------------ RETFILT void $4c2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V01} {V16 V17} {V00 V01} {V00 V16 V17} BB02 use def in out {V17} {V02 V09 V33 V34} {V00 V16 V17} {V00 V02 V16 V17 V34} BB03 use def in out {V00 V02 V17} {V03} {V00 V02 V16 V17 V34} {V02 V03 V16 V17 V34} BB04 use def in out {V02} {} {V02 V03 V16 V17 V34} {V02 V03 V16 V17 V34} BB05 use def in out {V02} {V35} {V02 V03 V16 V17 V34} {V02 V03 V16 V17 V34 V35} BB06 use def in out {V03 V35} {} {V02 V03 V16 V17 V34 V35} {V02 V03 V16 V17 V34} BB07 use def in out {V02 V03 V16 V17} {V13 V20 V21 V22 V23 V24 V29 V30} {V02 V03 V16 V17 V34} {V02 V03 V34} BB08 use def in out {V03} {V05} {V02 V03 V34} {V02 V05 V34} BB09 use def in out {} {} {V02} {V02} BB10 use def in out {} {} {V02} {V02} BB11 use def in out {} {} {V02} {V02} BB12 use def in out {} {V08 V26 V27} {V02} {V02} BB13 use def in out {V34} {V15} {V02 V05 V34} {V02 V05 V15} BB14 use def in out {V02 V05 V15} {} {V02 V05 V15} {} BB15 use def in out {} {V15 V34} {V02} {V02 V15} BB16 use def in out {V02 V15} {} {V02 V15} {} Local V02 should not be enregistered because: live in/out of a handler Interval 0: RefPositions {} physReg:NA Preferences=[allInt] Interval 1: RefPositions {} physReg:NA Preferences=[allInt] Interval 2: RefPositions {} physReg:NA Preferences=[allInt] Interval 3: RefPositions {} physReg:NA Preferences=[allInt] Interval 4: RefPositions {} physReg:NA Preferences=[allInt] Interval 5: RefPositions {} physReg:NA Preferences=[allInt] Interval 6: RefPositions {} physReg:NA Preferences=[allInt] Interval 7: RefPositions {} physReg:NA Preferences=[allInt] Interval 8: RefPositions {} physReg:NA Preferences=[allInt] Interval 9: RefPositions {} physReg:NA Preferences=[allInt] Interval 10: RefPositions {} physReg:NA Preferences=[allInt] Interval 11: RefPositions {} physReg:NA Preferences=[allInt] Interval 12: RefPositions {} physReg:NA Preferences=[allInt] Interval 13: RefPositions {} physReg:NA Preferences=[allInt] Interval 14: RefPositions {} physReg:NA Preferences=[allInt] Interval 15: RefPositions {} physReg:NA Preferences=[allInt] Interval 16: RefPositions {} physReg:NA Preferences=[allInt] Interval 17: RefPositions {} physReg:NA Preferences=[allInt] Interval 18: RefPositions {} physReg:NA Preferences=[allInt] Interval 19: RefPositions {} physReg:NA Preferences=[allInt] Interval 20: RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 Removing register rbp from LSRA register masks After removing register: LSRA register masks. Total allocated: 64, total used: 35 0: [rax rcx rdx rbx rsi rdi r8-r15] 1: [mm0-mm15] 2: [rax] 3: [rcx] 4: [rdx] 5: [rbx] 6: [rsp] 7: [] 8: [rsi] 9: [rdi] 10: [r8] 11: [r9] 12: [r10] 13: [r11] 14: [r12] 15: [r13] 16: [r14] 17: [r15] 18: [mm0] 19: [mm1] 20: [mm2] 21: [mm3] 22: [mm4] 23: [mm5] 24: [mm6] 25: [mm7] 26: [mm8] 27: [mm9] 28: [mm10] 29: [mm11] 30: [mm12] 31: [mm13] 32: [mm14] 33: [mm15] 34: [] TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 1 ) BB04( 1 ) BB05( 0.50) BB06( 0.50) BB07( 1 ) BB08( 1 ) BB13( 1 ) BB14( 1 ) BB09( 0 ) BB10( 0 ) BB11( 0 ) BB12( 0 ) BB15( 0 ) BB16( 0 ) BB01 [???..???), preds={} succs={BB02} ===== N001. V01(t360) N000. t516 = LEA(b+0) ; t360 N004. t363 = IND ; t516 N006. V16(t364); t363 N007. V01(t366*) N000. t517 = LEA(b+8) ; t366* N010. t369 = IND ; t517 N012. V17(t370); t369 BB02 [000..012), preds={BB01} succs={BB03} ===== N000. IL_OFFSET IL offset: 0x0 N005. CNS_INT(h) 0x17dd3b1e7b0 cid/mid N006. t133 = IND N000. t518 = PUTARG_REG; t133 N007. t134 = CNS_INT 327 N000. t519 = PUTARG_REG; t134 N010. t137* = CALL help; t518,t519 N012. V34(t499); t137* N013. V34(t500) N000. t520 = LEA(b+888); t500 N017. t140 = IND ; t520 N019. V09(t127); t140 N004. V09(t11) N000. t521 = PUTARG_REG; t11 N005. V17(t145) N000. t522 = PUTARG_REG; t145 N001. V09(t523*) N002. t524 = LEA(b+0) ; t523* N003. t525 = IND ; t524 N004. t526 = LEA(b+64); t525 N005. t527 = IND ; t526 N006. t528 = LEA(b+32); t527 N007. t529 = IND ; t528 N008. t13 = CALLV ind; t521,t522,t529 N010. V33(t495); t13 N011. V33(t496*) N013. V02 MEM; t496* BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ===== N008. V00(t19) N000. t530 = PUTARG_REG; t19 N009. t20 = V02 MEM N000. t531 = PUTARG_REG; t20 N010. V17(t150) N000. t532 = PUTARG_REG; t150 N011. t21 = CNS_INT 0 N000. t533 = PUTARG_REG; t21 N001. V00(t534*) N002. t535 = LEA(b+0) ; t534* N003. t536 = IND ; t535 N004. t537 = LEA(b+96); t536 N005. t538 = IND ; t537 N006. t539 = LEA(b+16); t538 N007. t540 = IND ; t539 N016. t27 = CALLV ind; t530,t531,t532,t533,t540 N018. V03(t32); t27 N001. V03(t34) N002. t35 = CAST ; t34 N003. V17(t155) N004. t41 = CAST ; t155 N005. GT ; t35,t41 N006. JTRUE BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ===== N000. IL_OFFSET IL offset: 0x39 N001. V02 MEM N002. CNS_INT null N003. EQ N004. JTRUE BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ===== N001. t196 = V02 MEM N000. t541 = LEA(b+8) ; t196 N002. t197 = IND ; t541 N004. V35(t508); t197 N005. V35(t509) N007. CNS_INT 0 N008. LT ; t509 N009. JTRUE BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ===== N001. V35(t511*) N002. V03(t244) N003. LT ; t511*,t244 N004. JTRUE BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ===== N001. t418 = V02 MEM N002. CNS_INT 16 field offset Fseq[m_arrayData] N003. t420 = ADD ; t418 N005. V13(t265); t420 N001. V13(t263*) N003. V22(t230); t263* N001. V22(t427*) N003. V20(t428); t427* N000. IL_OFFSET IL offset: 0x41 N001. V20(t430*) N003. V18 MEM; t430* N004. V03(t433) N006. V19 MEM; t433 N000. IL_OFFSET IL offset: 0x42 N001. V16(t437*) N003. V23(t438); t437* N004. V17(t440*) N006. V24(t441); t440* N000. IL_OFFSET IL offset: 0x42 N001. t278 = LCL_VAR_ADDR V04 loc2 byref V04._pointer (offs=0x00) -> V18 tmp12 int V04._length (offs=0x08) -> V19 tmp13 N004. V30(t465); t278 N005. t447 = LCL_VAR_ADDR V28 tmp22 N008. V29(t449); t447 N009. V29(t450) N000. t542 = LEA(b+0) ; t450 N013. V23(t454*) N000. STOREIND ; t542,t454* N016. V29(t457*) N000. t543 = LEA(b+8) ; t457* N020. V24(t461*) N000. STOREIND ; t543,t461* N024. V30(t466*) N000. t544 = PUTARG_REG; t466* N025. t468 = LCL_VAR_ADDR V28 tmp22 N000. t545 = PUTARG_REG; t468 N029. t280 = CALL ; t544,t545 N030. CNS_INT 0 N031. EQ ; t280 N032. JTRUE BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ===== N000. IL_OFFSET IL offset: 0x4a N001. V03(t73*) N003. V05(t75); t73* BB13 [04E..05B), preds={BB08} succs={BB14} ===== N001. V34(t502*) N000. t554 = LEA(b+888); t502* N004. t334 = IND ; t554 N006. V15(t332); t334 BB14 [05B..05D) (return), preds={BB13} succs={} ===== N006. V15(t345*) N000. t555 = PUTARG_REG; t345* N007. t347* = V02 MEM N000. t556 = PUTARG_REG; t347* N008. t349 = CNS_INT 0 N000. t557 = PUTARG_REG; t349 N012. CALL nullcheck; t555,t556,t557 N000. IL_OFFSET IL offset: 0x5b N001. V05(t78*) N002. RETURN ; t78* BB09 [042..043) (throw), preds={BB07} succs={} ===== N000. IL_OFFSET IL offset: 0x42 N001. CALL BB10 [000..000) (throw), preds={BB05,BB06} succs={} ===== N001. CALL BB11 [000..000) (throw), preds={BB04} succs={} ===== N003. t253 = CNS_INT 2 N000. t546 = PUTARG_REG; t253 N005. CALL ; t546 BB12 [02E..039) (throw), preds={BB03} succs={} ===== N003. t85 = CNS_INT(h) 0x17dd3b22ac8 method N000. t547 = PUTARG_REG; t85 N005. t86 = CALL help; t547 N007. V08(t88); t86 N004. t388 = CNS_INT 0xE904 N000. t548 = PUTARG_REG; t388 N006. t390 = CALL help; t548 N008. V26(t394); t390 N012. V26(t395*) N000. t549 = PUTARG_REG; t395* N013. t159 = CNS_INT null N000. t550 = PUTARG_REG; t159 N016. t160 = CALL ; t549,t550 N018. V27(t400); t160 N020. V27(t401*) N000. t551 = PUTARG_REG; t401* N021. V08(t90) N000. t552 = PUTARG_REG; t90 N024. CALL ; t551,t552 N000. IL_OFFSET IL offset: 0x38 N003. V08(t94*) N000. t553 = PUTARG_REG; t94* N005. CALL help; t553 BB15 [04E..05B), preds={} succs={BB16} ===== N000. IL_OFFSET IL offset: 0x4e N005. CNS_INT(h) 0x17dd3b1e7b0 cid/mid N006. t323 = IND N000. t558 = PUTARG_REG; t323 N007. t324 = CNS_INT 327 N000. t559 = PUTARG_REG; t324 N010. t327* = CALL help; t558,t559 N012. V34(t504); t327* N013. V34(t505*) N000. t560 = LEA(b+888); t505* N017. t330 = IND ; t560 N019. V15(t317); t330 BB16 [???..???) (finret), preds={BB15} succs={} ===== N006. V15(t319*) N000. t561 = PUTARG_REG; t319* N007. t102* = V02 MEM N000. t562 = PUTARG_REG; t102* N008. t103 = CNS_INT 0 N000. t563 = PUTARG_REG; t103 N012. CALL nullcheck; t561,t562,t563 N000. IL_OFFSET IL offset: 0x5a N001. RETFILT buildIntervals second part ======== Int arg V01 in reg rdx BB00 regmask=[rdx] minReg=1 fixed> Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 ( 1, 1) [000360] ------------ * LCL_VAR byref V01 arg1 u:2 NA REG NA $c0 +[--] consume=0 produce=1 DefList: { N003.t360. LCL_VAR } N005 (???,???) [000516] -c---------- * LEA(b+0) byref REG NA +[--] Contained DefList: { N003.t360. LCL_VAR } N007 ( 4, 3) [000363] x----------- * IND byref REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 21: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB01 regmask=[allIntButFP] minReg=1> DefList: { N007.t363. IND } N009 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> DefList: { } N011 ( 1, 1) [000366] ------------ * LCL_VAR byref V01 arg1 u:2 NA (last use) REG NA $c0 +[--] consume=0 produce=1 DefList: { N011.t366. LCL_VAR } N013 (???,???) [000517] -c---------- * LEA(b+8) byref REG NA +[--] Contained DefList: { N011.t366. LCL_VAR } N015 ( 4, 4) [000369] x----------- * IND int REG NA +[--] consume=1 produce=1 LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 22: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB01 regmask=[allIntButFP] minReg=1> DefList: { N015.t369. IND } N017 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB01 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> CHECKING LAST USES for block 1, liveout={V00 V16 V17} ============================== use: {V01} def: {V16 V17} NEW BLOCK BB02 Setting BB02 as the predecessor for determining incoming variable registers of BB01 DefList: { } N021 ( 24, 30) [000128] ------------ * IL_OFFSET void IL offset: 0x0 REG NA +[--] consume=0 produce=0 DefList: { } N023 ( 3, 10) [000132] -c---------- * CNS_INT(h) long 0x17dd3b1e7b0 cid/mid REG NA $300 +[--] Contained DefList: { } N025 ( 5, 12) [000133] #----------- * IND long REG NA $340 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 23: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB02 regmask=[allIntButFP] minReg=1> DefList: { N025.t133. IND } N027 (???,???) [000518] ------------ * PUTARG_REG long REG rcx +[--] consume=1 produce=1 BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 24: RefPositions {} physReg:NA Preferences=[allIntButFP] BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> DefList: { N027.t518. PUTARG_REG } N029 ( 1, 4) [000134] ------------ * CNS_INT int 327 REG NA $45 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 25: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB02 regmask=[allIntButFP] minReg=1> DefList: { N027.t518. PUTARG_REG; N029.t134. CNS_INT } N031 (???,???) [000519] ------------ * PUTARG_REG int REG rdx +[--] consume=1 produce=1 BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 26: RefPositions {} physReg:NA Preferences=[allIntButFP] BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> DefList: { N027.t518. PUTARG_REG; N031.t519. PUTARG_REG } N033 ( 20, 23) [000137] H-CXG------- * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 +[--] consume=2 produce=1 BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> Interval 27: RefPositions {} physReg:NA Preferences=[allIntButFP] BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> DefList: { N033.t137. CALL } N035 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 NA REG NA +[--] consume=1 produce=0 Assigning related to BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> DefList: { } N037 ( 1, 1) [000500] ------------ * LCL_VAR byref V34 cse0 NA REG NA $143 +[--] consume=0 produce=1 DefList: { N037.t500. LCL_VAR } N039 (???,???) [000520] -c---------- * LEA(b+888) byref REG NA +[--] Contained DefList: { N037.t500. LCL_VAR } N041 ( 24, 30) [000140] ---XG------- * IND ref REG NA +[--] consume=1 produce=1 LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 28: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB02 regmask=[allIntButFP] minReg=1> DefList: { N041.t140. IND } N043 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> DefList: { } N045 ( 1, 1) [000011] ------------ * LCL_VAR ref V09 tmp3 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N045.t11. LCL_VAR } N047 (???,???) [000521] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 Setting putarg_reg as a pass-through of a non-last use lclVar BB02 regmask=[rcx] minReg=1> LCL_VAR BB02 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 29: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> DefList: { N047.t521. PUTARG_REG } N049 ( 1, 1) [000145] ------------ * LCL_VAR int V17 tmp11 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N047.t521. PUTARG_REG; N049.t145. LCL_VAR } N051 (???,???) [000522] ------------ * PUTARG_REG int REG rdx +[--] consume=1 produce=1 Setting putarg_reg as a pass-through of a non-last use lclVar BB02 regmask=[rdx] minReg=1> LCL_VAR BB02 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 30: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG } N053 ( 1, 1) [000523] ------------ * LCL_VAR ref V09 tmp3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N053.t523. LCL_VAR } N055 ( 2, 2) [000524] -c---------- * LEA(b+0) byref REG NA +[--] Contained DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N053.t523. LCL_VAR } N057 ( 5, 4) [000525] ------------ * IND long REG NA +[--] consume=1 produce=1 LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 31: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB02 regmask=[allIntButFP] minReg=1> DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N057.t525. IND } N059 ( 6, 5) [000526] -c---------- * LEA(b+64) long REG NA +[--] Contained DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N057.t525. IND } N061 ( 9, 7) [000527] ------------ * IND long REG NA +[--] consume=1 produce=1 BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 32: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB02 regmask=[allIntButFP] minReg=1> DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N061.t527. IND } N063 ( 10, 8) [000528] -c---------- * LEA(b+32) long REG NA +[--] Contained DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N061.t527. IND } N065 ( 13, 10) [000529] -c---------- * IND long REG NA +[--] Contained DefList: { N047.t521. PUTARG_REG; N051.t522. PUTARG_REG; N061.t527. IND } N067 ( 22, 12) [000013] --CXG------- * CALLV ind ref ArrayPool`1.Rent $3c3 +[--] consume=3 produce=1 BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [rax], Use candidates [allIntButFP] BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> Interval 33: RefPositions {} physReg:NA Preferences=[allIntButFP] BB02 regmask=[rax] minReg=1> CALL BB02 regmask=[rax] minReg=1 fixed> DefList: { N067.t13. CALL } N069 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB02 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> DefList: { } N071 ( 3, 2) [000496] ------------ * LCL_VAR ref V33 tmp27 u:2 NA (last use) REG NA $3c3 +[--] consume=0 produce=1 DefList: { N071.t496. LCL_VAR } N073 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 NA REG NA +[--] consume=1 produce=0 LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> CHECKING LAST USES for block 2, liveout={V00 V02 V16 V17 V34} ============================== use: {V17} def: {V02 V09 V33 V34} NEW BLOCK BB03 Setting BB03 as the predecessor for determining incoming variable registers of BB02 DefList: { } N077 ( 1, 1) [000019] ------------ * LCL_VAR ref V00 this u:2 NA REG NA $80 +[--] consume=0 produce=1 DefList: { N077.t19. LCL_VAR } N079 (???,???) [000530] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 Setting putarg_reg as a pass-through of a non-last use lclVar BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 34: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> DefList: { N079.t530. PUTARG_REG } N081 ( 1, 1) [000020] ------------ * LCL_VAR ref V02 loc0 u:2 NA REG NA $3c3 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 35: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB03 regmask=[allIntButFP] minReg=1> DefList: { N079.t530. PUTARG_REG; N081.t20. LCL_VAR } N083 (???,???) [000531] ------------ * PUTARG_REG ref REG rdx +[--] consume=1 produce=1 BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 36: RefPositions {} physReg:NA Preferences=[allIntButFP] BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG } N085 ( 1, 1) [000150] ------------ * LCL_VAR int V17 tmp11 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N085.t150. LCL_VAR } N087 (???,???) [000532] ------------ * PUTARG_REG int REG r9 +[--] consume=1 produce=1 Setting putarg_reg as a pass-through of a non-last use lclVar BB03 regmask=[r9] minReg=1> LCL_VAR BB03 regmask=[r9] minReg=1 last fixed> Def candidates [r9], Use candidates [r9] Interval 37: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to BB03 regmask=[r9] minReg=1> PUTARG_REG BB03 regmask=[r9] minReg=1 fixed> DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG } N089 ( 1, 1) [000021] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 38: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB03 regmask=[allIntButFP] minReg=1> DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N089.t21. CNS_INT } N091 (???,???) [000533] ------------ * PUTARG_REG int REG r8 +[--] consume=1 produce=1 BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> Def candidates [r8], Use candidates [r8] Interval 39: RefPositions {} physReg:NA Preferences=[allIntButFP] BB03 regmask=[r8] minReg=1> PUTARG_REG BB03 regmask=[r8] minReg=1 fixed> DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG } N093 ( 1, 1) [000534] ------------ * LCL_VAR ref V00 this NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N093.t534. LCL_VAR } N095 ( 2, 2) [000535] -c---------- * LEA(b+0) byref REG NA +[--] Contained DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N093.t534. LCL_VAR } N097 ( 5, 4) [000536] ------------ * IND long REG NA +[--] consume=1 produce=1 LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 40: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB03 regmask=[allIntButFP] minReg=1> DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N097.t536. IND } N099 ( 6, 5) [000537] -c---------- * LEA(b+96) long REG NA +[--] Contained DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N097.t536. IND } N101 ( 9, 7) [000538] ------------ * IND long REG NA +[--] consume=1 produce=1 BB03 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 41: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB03 regmask=[allIntButFP] minReg=1> DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N101.t538. IND } N103 ( 10, 8) [000539] -c---------- * LEA(b+16) long REG NA +[--] Contained DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N101.t538. IND } N105 ( 13, 10) [000540] -c---------- * IND long REG NA +[--] Contained DefList: { N079.t530. PUTARG_REG; N083.t531. PUTARG_REG; N087.t532. PUTARG_REG; N091.t533. PUTARG_REG; N101.t538. IND } N107 ( 24, 16) [000027] --CXG------- * CALLV ind int Stream.Read $246 +[--] consume=5 produce=1 BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[r9] minReg=1> BB03 regmask=[r9] minReg=1 last fixed> BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> BB03 regmask=[allIntButFP] minReg=1 last> Def candidates [rax], Use candidates [allIntButFP] BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> Interval 42: RefPositions {} physReg:NA Preferences=[allIntButFP] BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> DefList: { N107.t27. CALL } N109 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB03 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> DefList: { } N111 ( 1, 1) [000034] ------------ * LCL_VAR int V03 loc1 u:2 NA REG NA $246 +[--] consume=0 produce=1 DefList: { N111.t34. LCL_VAR } N113 ( 2, 3) [000035] ---------U-- * CAST long <- ulong <- uint REG NA $440 +[-O] consume=1 produce=1 LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 43: RefPositions {} physReg:NA Preferences=[allIntButFP] CAST BB03 regmask=[allIntButFP] minReg=1> DefList: { N113.t35. CAST } N115 ( 1, 1) [000155] ------------ * LCL_VAR int V17 tmp11 u:2 NA REG NA +[--] consume=0 produce=1 DefList: { N113.t35. CAST; N115.t155. LCL_VAR } N117 ( 2, 3) [000041] ------------ * CAST long <- int REG NA +[--] consume=1 produce=1 LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 44: RefPositions {} physReg:NA Preferences=[allIntButFP] CAST BB03 regmask=[allIntButFP] minReg=1> DefList: { N113.t35. CAST; N117.t41. CAST } N119 ( 5, 7) [000042] J------N---- * GT void REG NA +[--] consume=2 produce=0 BB03 regmask=[allIntButFP] minReg=1 last> BB03 regmask=[allIntButFP] minReg=1 last> DefList: { } N121 ( 7, 9) [000043] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 3, liveout={V02 V03 V16 V17 V34} ============================== use: {V00 V02 V17} def: {V03} NEW BLOCK BB04 Setting BB04 as the predecessor for determining incoming variable registers of BB03 DefList: { } N125 ( 0, 0) [000052] ------------ * IL_OFFSET void IL offset: 0x39 REG NA +[--] consume=0 produce=0 DefList: { } N127 ( 1, 1) [000046] -c---------- * LCL_VAR ref V02 loc0 u:2 NA REG NA $3c3 +[--] Contained DefList: { } N129 ( 1, 1) [000165] -c---------- * CNS_INT ref null REG NA $VN.Null +[--] Contained DefList: { } N131 ( 3, 3) [000166] J------N---- * EQ void REG NA $482 +[--] consume=0 produce=0 DefList: { } N133 ( 5, 5) [000167] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 4, liveout={V02 V03 V16 V17 V34} ============================== use: {V02} def: {} NEW BLOCK BB05 Setting BB05 as the predecessor for determining incoming variable registers of BB04 DefList: { } N137 ( 3, 2) [000196] ------------ * LCL_VAR ref V02 loc0 u:2 NA REG NA $3c3 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 45: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB05 regmask=[allIntButFP] minReg=1> DefList: { N137.t196. LCL_VAR } N139 (???,???) [000541] -c---------- * LEA(b+8) byref REG NA +[--] Contained DefList: { N137.t196. LCL_VAR } N141 ( 5, 4) [000197] ---X-------- * IND int REG NA $500 +[--] consume=1 produce=1 BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 46: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB05 regmask=[allIntButFP] minReg=1> DefList: { N141.t197. IND } N143 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 NA REG NA +[--] consume=1 produce=0 Assigning related to BB05 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N145 ( 3, 2) [000509] ------------ * LCL_VAR int V35 cse1 NA REG NA $500 +[-O] consume=0 produce=1 DefList: { N145.t509. LCL_VAR } N147 ( 1, 1) [000195] -c---------- * CNS_INT int 0 REG NA $40 +[--] Contained DefList: { N145.t509. LCL_VAR } N149 ( 14, 11) [000199] N--X---N-U-- * LT void REG NA $483 +[--] consume=1 produce=0 LCL_VAR BB05 regmask=[allIntButFP] minReg=1 last> DefList: { } N151 ( 16, 13) [000200] ---X-------- * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 5, liveout={V02 V03 V16 V17 V34 V35} ============================== use: {V02} def: {V35} NEW BLOCK BB06 Setting BB06 as the predecessor for determining incoming variable registers of BB05 DefList: { } N155 ( 1, 1) [000511] ------------ * LCL_VAR int V35 cse1 NA (last use) REG NA $500 +[-O] consume=0 produce=1 DefList: { N155.t511. LCL_VAR } N157 ( 1, 1) [000244] ------------ * LCL_VAR int V03 loc1 u:2 NA REG NA $246 +[--] consume=0 produce=1 DefList: { N155.t511. LCL_VAR; N157.t244. LCL_VAR } N159 ( 3, 3) [000249] N------N-U-- * LT void REG NA $484 +[--] consume=2 produce=0 LCL_VAR BB06 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 last> DefList: { } N161 ( 5, 5) [000250] ------------ * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 6, liveout={V02 V03 V16 V17 V34} ============================== use: {V03 V35} def: {} NEW BLOCK BB07 Setting BB07 as the predecessor for determining incoming variable registers of BB06 DefList: { } N165 ( 3, 2) [000418] ------------ * LCL_VAR ref V02 loc0 u:2 NA REG NA $3c3 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 47: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB07 regmask=[allIntButFP] minReg=1> DefList: { N165.t418. LCL_VAR } N167 ( 1, 1) [000419] -c---------- * CNS_INT long 16 field offset Fseq[m_arrayData] REG NA $102 +[--] Contained DefList: { N165.t418. LCL_VAR } N169 ( 5, 4) [000420] -------N---- * ADD byref REG NA $146 +[--] consume=1 produce=1 BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 48: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to ADD BB07 regmask=[allIntButFP] minReg=1> DefList: { N169.t420. ADD } N171 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N173 ( 1, 1) [000263] ------------ * LCL_VAR byref V13 tmp7 u:2 NA (last use) REG NA $146 +[--] consume=0 produce=1 DefList: { N173.t263. LCL_VAR } N175 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N177 ( 1, 1) [000427] -------N---- * LCL_VAR byref V22 tmp16 u:2 NA (last use) REG NA $146 +[--] consume=0 produce=1 DefList: { N177.t427. LCL_VAR } N179 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N181 ( 10, 8) [000064] ------------ * IL_OFFSET void IL offset: 0x41 REG NA +[--] consume=0 produce=0 DefList: { } N183 ( 1, 1) [000430] -------N---- * LCL_VAR byref V20 tmp14 u:2 NA (last use) REG NA $146 +[--] consume=0 produce=1 DefList: { N183.t430. LCL_VAR } N185 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 NA REG NA +[--] consume=1 produce=0 LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N187 ( 1, 1) [000433] -------N---- * LCL_VAR int V03 loc1 u:2 NA REG NA $246 +[--] consume=0 produce=1 DefList: { N187.t433. LCL_VAR } N189 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 NA REG NA +[--] consume=1 produce=0 LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N191 ( 10, 8) [000297] ------------ * IL_OFFSET void IL offset: 0x42 REG NA +[--] consume=0 produce=0 DefList: { } N193 ( 1, 1) [000437] -------N---- * LCL_VAR byref V16 tmp10 u:2 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N193.t437. LCL_VAR } N195 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N197 ( 1, 1) [000440] -------N---- * LCL_VAR int V17 tmp11 u:2 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N197.t440. LCL_VAR } N199 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N201 ( 47, 35) [000289] ------------ * IL_OFFSET void IL offset: 0x42 REG NA +[--] consume=0 produce=0 DefList: { } N203 ( 3, 2) [000278] -------N---- * LCL_VAR_ADDR byref V04 loc2 NA * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 49: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> DefList: { N203.t278. LCL_VAR_ADDR } N205 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N207 ( 3, 2) [000447] -------N---- * LCL_VAR_ADDR byref V28 tmp22 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 50: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> DefList: { N207.t447. LCL_VAR_ADDR } N209 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB07 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N211 ( 1, 1) [000450] ------------ * LCL_VAR byref V29 tmp23 u:2 NA REG NA $1c8 +[--] consume=0 produce=1 DefList: { N211.t450. LCL_VAR } N213 (???,???) [000542] -c---------- * LEA(b+0) byref REG NA +[--] Contained DefList: { N211.t450. LCL_VAR } N215 ( 3, 2) [000454] -------N---- * LCL_VAR byref V23 tmp17 u:2 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N211.t450. LCL_VAR; N215.t454. LCL_VAR } N217 (???,???) [000512] -A---------- * STOREIND byref REG NA +[--] consume=2 produce=0 LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N219 ( 1, 1) [000457] ------------ * LCL_VAR byref V29 tmp23 u:2 NA (last use) REG NA $1c8 +[--] consume=0 produce=1 DefList: { N219.t457. LCL_VAR } N221 (???,???) [000543] -c---------- * LEA(b+8) byref REG NA +[--] Contained DefList: { N219.t457. LCL_VAR } N223 ( 3, 2) [000461] -------N---- * LCL_VAR int V24 tmp18 u:2 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N219.t457. LCL_VAR; N223.t461. LCL_VAR } N225 (???,???) [000513] -A--------L- * STOREIND int REG NA +[--] consume=2 produce=0 LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N227 ( 1, 1) [000466] ------------ * LCL_VAR byref V30 tmp24 u:2 NA (last use) REG NA $1c6 +[--] consume=0 produce=1 DefList: { N227.t466. LCL_VAR } N229 (???,???) [000544] ------------ * PUTARG_REG byref REG rcx +[--] consume=1 produce=1 BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 51: RefPositions {} physReg:NA Preferences=[allIntButFP] BB07 regmask=[rcx] minReg=1> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> DefList: { N229.t544. PUTARG_REG } N231 ( 3, 2) [000468] -------N---- * LCL_VAR_ADDR byref V28 tmp22 NA REG NA +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 52: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> DefList: { N229.t544. PUTARG_REG; N231.t468. LCL_VAR_ADDR } N233 (???,???) [000545] ------------ * PUTARG_REG byref REG rdx +[--] consume=1 produce=1 BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 53: RefPositions {} physReg:NA Preferences=[allIntButFP] BB07 regmask=[rdx] minReg=1> PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> DefList: { N229.t544. PUTARG_REG; N233.t545. PUTARG_REG } N235 ( 43, 31) [000280] --CXG------- * CALL int Span`1.TryCopyTo $24c +[-O] consume=2 produce=1 BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB07 regmask=[rax] minReg=1> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rdx] minReg=1> BB07 regmask=[r8] minReg=1> BB07 regmask=[r9] minReg=1> BB07 regmask=[r10] minReg=1> BB07 regmask=[r11] minReg=1> Interval 54: RefPositions {} physReg:NA Preferences=[allIntButFP] BB07 regmask=[rax] minReg=1> CALL BB07 regmask=[rax] minReg=1 fixed> DefList: { N235.t280. CALL } N237 ( 1, 1) [000286] -c---------- * CNS_INT int 0 REG NA $40 +[--] Contained DefList: { N235.t280. CALL } N239 ( 45, 33) [000287] J--XG--N---- * EQ void REG NA $485 +[--] consume=1 produce=0 BB07 regmask=[allIntButFP] minReg=1 last> DefList: { } N241 ( 47, 35) [000288] ---XG------- * JTRUE void REG NA +[--] consume=0 produce=0 CHECKING LAST USES for block 7, liveout={V02 V03 V34} ============================== use: {V02 V03 V16 V17} def: {V13 V20 V21 V22 V23 V24 V29 V30} NEW BLOCK BB08 Setting BB08 as the predecessor for determining incoming variable registers of BB07 DefList: { } N245 ( 5, 4) [000076] ------------ * IL_OFFSET void IL offset: 0x4a REG NA +[--] consume=0 produce=0 DefList: { } N247 ( 1, 1) [000073] ------------ * LCL_VAR int V03 loc1 u:2 NA (last use) REG NA $246 +[--] consume=0 produce=1 DefList: { N247.t73. LCL_VAR } N249 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to LCL_VAR BB08 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB08 regmask=[allIntButFP] minReg=1 last> CHECKING LAST USES for block 8, liveout={V02 V05 V34} ============================== use: {V03} def: {V05} NEW BLOCK BB13 Setting BB13 as the predecessor for determining incoming variable registers of BB08 DefList: { } N253 ( 1, 1) [000502] ------------ * LCL_VAR byref V34 cse0 NA (last use) REG NA $143 +[--] consume=0 produce=1 DefList: { N253.t502. LCL_VAR } N255 (???,???) [000554] -c---------- * LEA(b+888) byref REG NA +[--] Contained DefList: { N253.t502. LCL_VAR } N257 ( 4, 7) [000334] ---XG------- * IND ref REG NA +[--] consume=1 produce=1 LCL_VAR BB13 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 55: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB13 regmask=[allIntButFP] minReg=1> DefList: { N257.t334. IND } N259 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 NA REG NA +[--] consume=1 produce=0 Assigning related to BB13 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB13 regmask=[allIntButFP] minReg=1 last> CHECKING LAST USES for block 13, liveout={V02 V05 V15} ============================== use: {V34} def: {V15} NEW BLOCK BB14 Setting BB14 as the predecessor for determining incoming variable registers of BB13 DefList: { } N263 ( 3, 2) [000345] ------------ * LCL_VAR ref V15 tmp9 u:3 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N263.t345. LCL_VAR } N265 (???,???) [000555] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB14 regmask=[rcx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 56: RefPositions {} physReg:NA Preferences=[allIntButFP] BB14 regmask=[rcx] minReg=1> PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> DefList: { N265.t555. PUTARG_REG } N267 ( 1, 1) [000347] ------------ * LCL_VAR ref V02 loc0 u:2 NA (last use) REG NA $3c3 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 57: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB14 regmask=[allIntButFP] minReg=1> DefList: { N265.t555. PUTARG_REG; N267.t347. LCL_VAR } N269 (???,???) [000556] ------------ * PUTARG_REG ref REG rdx +[--] consume=1 produce=1 BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 58: RefPositions {} physReg:NA Preferences=[allIntButFP] BB14 regmask=[rdx] minReg=1> PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> DefList: { N265.t555. PUTARG_REG; N269.t556. PUTARG_REG } N271 ( 1, 1) [000349] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 59: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB14 regmask=[allIntButFP] minReg=1> DefList: { N265.t555. PUTARG_REG; N269.t556. PUTARG_REG; N271.t349. CNS_INT } N273 (???,???) [000557] ------------ * PUTARG_REG int REG r8 +[--] consume=1 produce=1 BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> Def candidates [r8], Use candidates [r8] Interval 60: RefPositions {} physReg:NA Preferences=[allIntButFP] BB14 regmask=[r8] minReg=1> PUTARG_REG BB14 regmask=[r8] minReg=1 fixed> DefList: { N265.t555. PUTARG_REG; N269.t556. PUTARG_REG; N273.t557. PUTARG_REG } N275 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void +[--] consume=3 produce=0 BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> BB14 regmask=[rax] minReg=1> BB14 regmask=[rcx] minReg=1> BB14 regmask=[rdx] minReg=1> BB14 regmask=[r8] minReg=1> BB14 regmask=[r9] minReg=1> BB14 regmask=[r10] minReg=1> BB14 regmask=[r11] minReg=1> DefList: { } N277 ( 4, 3) [000080] ------------ * IL_OFFSET void IL offset: 0x5b REG NA +[--] consume=0 produce=0 DefList: { } N279 ( 3, 2) [000078] ------------ * LCL_VAR int V05 loc3 u:2 NA (last use) REG NA $246 +[--] consume=0 produce=1 DefList: { N279.t78. LCL_VAR } N281 ( 4, 3) [000079] ------------ * RETURN int REG NA $252 +[--] consume=1 produce=0 BB14 regmask=[rax] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for block 14, liveout={} ============================== use: {V02 V05 V15} def: {} NEW BLOCK BB09 Setting BB09 as the predecessor for determining incoming variable registers of BB07 DefList: { } N285 ( 14, 5) [000293] ------------ * IL_OFFSET void IL offset: 0x42 REG NA +[--] consume=0 produce=0 DefList: { } N287 ( 14, 5) [000292] --CXG------- * CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void +[--] consume=0 produce=0 BB09 regmask=[rax] minReg=1> BB09 regmask=[rcx] minReg=1> BB09 regmask=[rdx] minReg=1> BB09 regmask=[r8] minReg=1> BB09 regmask=[r9] minReg=1> BB09 regmask=[r10] minReg=1> BB09 regmask=[r11] minReg=1> CHECKING LAST USES for block 9, liveout={V02} ============================== use: {} def: {} NEW BLOCK BB10 Setting BB10 as the predecessor for determining incoming variable registers of BB05 DefList: { } N291 ( 14, 5) [000203] --CXG------- * CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void +[--] consume=0 produce=0 BB10 regmask=[rax] minReg=1> BB10 regmask=[rcx] minReg=1> BB10 regmask=[rdx] minReg=1> BB10 regmask=[r8] minReg=1> BB10 regmask=[r9] minReg=1> BB10 regmask=[r10] minReg=1> BB10 regmask=[r11] minReg=1> CHECKING LAST USES for block 10, liveout={V02} ============================== use: {} def: {} NEW BLOCK BB11 Setting BB11 as the predecessor for determining incoming variable registers of BB04 DefList: { } N295 ( 1, 1) [000253] ------------ * CNS_INT int 2 REG NA $4a +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 61: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB11 regmask=[allIntButFP] minReg=1> DefList: { N295.t253. CNS_INT } N297 (???,???) [000546] ------------ * PUTARG_REG int REG rcx +[--] consume=1 produce=1 BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 62: RefPositions {} physReg:NA Preferences=[allIntButFP] BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> DefList: { N297.t546. PUTARG_REG } N299 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void +[--] consume=1 produce=0 BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[r8] minReg=1> BB11 regmask=[r9] minReg=1> BB11 regmask=[r10] minReg=1> BB11 regmask=[r11] minReg=1> CHECKING LAST USES for block 11, liveout={V02} ============================== use: {} def: {} NEW BLOCK BB12 Setting BB12 as the predecessor for determining incoming variable registers of BB03 DefList: { } N303 ( 3, 10) [000085] ------------ * CNS_INT(h) long 0x17dd3b22ac8 method REG NA $302 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 63: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB12 regmask=[allIntButFP] minReg=1> DefList: { N303.t85. CNS_INT } N305 (???,???) [000547] ------------ * PUTARG_REG long REG rcx +[--] consume=1 produce=1 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 64: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> DefList: { N305.t547. PUTARG_REG } N307 ( 17, 16) [000086] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 +[--] consume=1 produce=1 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> Interval 65: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> DefList: { N307.t86. CALL } N309 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB12 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1 last> DefList: { } N311 ( 1, 4) [000388] ------------ * CNS_INT int 0xE904 REG NA $49 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 66: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB12 regmask=[allIntButFP] minReg=1> DefList: { N311.t388. CNS_INT } N313 (???,???) [000548] ------------ * PUTARG_REG int REG rcx +[--] consume=1 produce=1 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 67: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> DefList: { N313.t548. PUTARG_REG } N315 ( 15, 10) [000390] --CXG------- * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 +[--] consume=1 produce=1 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> Interval 68: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> DefList: { N315.t390. CALL } N317 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB12 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1 last> DefList: { } N319 ( 3, 2) [000395] ------------ * LCL_VAR ref V26 tmp20 u:2 NA (last use) REG NA $3cd +[--] consume=0 produce=1 DefList: { N319.t395. LCL_VAR } N321 (???,???) [000549] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 69: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> DefList: { N321.t549. PUTARG_REG } N323 ( 1, 1) [000159] ------------ * CNS_INT ref null REG NA $VN.Null +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 70: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB12 regmask=[allIntButFP] minReg=1> DefList: { N321.t549. PUTARG_REG; N323.t159. CNS_INT } N325 (???,???) [000550] ------------ * PUTARG_REG ref REG rdx +[--] consume=1 produce=1 BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 71: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> DefList: { N321.t549. PUTARG_REG; N325.t550. PUTARG_REG } N327 ( 40, 23) [000160] --CXG------- * CALL ref SR.GetResourceString $3d1 +[--] consume=2 produce=1 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> Interval 72: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> DefList: { N327.t160. CALL } N329 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB12 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1 last> DefList: { } N331 ( 3, 2) [000401] ------------ * LCL_VAR ref V27 tmp21 u:2 NA (last use) REG NA $3d1 +[--] consume=0 produce=1 DefList: { N331.t401. LCL_VAR } N333 (???,???) [000551] ------------ * PUTARG_REG ref REG rdx +[--] consume=1 produce=1 BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 73: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> DefList: { N333.t551. PUTARG_REG } N335 ( 3, 2) [000090] ------------ * LCL_VAR ref V08 tmp2 u:2 NA REG NA $346 +[--] consume=0 produce=1 DefList: { N333.t551. PUTARG_REG; N335.t90. LCL_VAR } N337 (???,???) [000552] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 Setting putarg_reg as a pass-through of a non-last use lclVar BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 74: RefPositions {} physReg:NA Preferences=[allIntButFP] Assigning related to BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> DefList: { N333.t551. PUTARG_REG; N337.t552. PUTARG_REG } N339 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void +[--] consume=2 produce=0 BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> DefList: { } N341 ( 17, 8) [000097] ------------ * IL_OFFSET void IL offset: 0x38 REG NA +[--] consume=0 produce=0 DefList: { } N343 ( 3, 2) [000094] ------------ * LCL_VAR ref V08 tmp2 u:2 NA (last use) REG NA $346 +[--] consume=0 produce=1 DefList: { N343.t94. LCL_VAR } N345 (???,???) [000553] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 75: RefPositions {} physReg:NA Preferences=[allIntButFP] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> DefList: { N345.t553. PUTARG_REG } N347 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 +[--] consume=1 produce=0 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> CHECKING LAST USES for block 12, liveout={V02} ============================== use: {} def: {V08 V26 V27} NEW BLOCK BB15 No allocated predecessor; Setting BB15 as the predecessor for determining incoming variable registers of BB12 DefList: { } N351 ( 24, 30) [000318] ------------ * IL_OFFSET void IL offset: 0x4e REG NA +[--] consume=0 produce=0 DefList: { } N353 ( 3, 10) [000322] -c---------- * CNS_INT(h) long 0x17dd3b1e7b0 cid/mid REG NA $300 +[--] Contained DefList: { } N355 ( 5, 12) [000323] #----------- * IND long REG NA $340 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 76: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB15 regmask=[allIntButFP] minReg=1> DefList: { N355.t323. IND } N357 (???,???) [000558] ------------ * PUTARG_REG long REG rcx +[--] consume=1 produce=1 BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 77: RefPositions {} physReg:NA Preferences=[allIntButFP] BB15 regmask=[rcx] minReg=1> PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> DefList: { N357.t558. PUTARG_REG } N359 ( 1, 4) [000324] ------------ * CNS_INT int 327 REG NA $45 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 78: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB15 regmask=[allIntButFP] minReg=1> DefList: { N357.t558. PUTARG_REG; N359.t324. CNS_INT } N361 (???,???) [000559] ------------ * PUTARG_REG int REG rdx +[--] consume=1 produce=1 BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 79: RefPositions {} physReg:NA Preferences=[allIntButFP] BB15 regmask=[rdx] minReg=1> PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> DefList: { N357.t558. PUTARG_REG; N361.t559. PUTARG_REG } N363 ( 20, 23) [000327] H-CXG------- * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 +[--] consume=2 produce=1 BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> Def candidates [rax], Use candidates [allIntButFP] BB15 regmask=[rax] minReg=1> BB15 regmask=[rcx] minReg=1> BB15 regmask=[rdx] minReg=1> BB15 regmask=[r8] minReg=1> BB15 regmask=[r9] minReg=1> BB15 regmask=[r10] minReg=1> BB15 regmask=[r11] minReg=1> Interval 80: RefPositions {} physReg:NA Preferences=[allIntButFP] BB15 regmask=[rax] minReg=1> CALL BB15 regmask=[rax] minReg=1 fixed> DefList: { N363.t327. CALL } N365 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 NA REG NA +[--] consume=1 produce=0 Assigning related to BB15 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> DefList: { } N367 ( 1, 1) [000505] ------------ * LCL_VAR byref V34 cse0 NA (last use) REG NA $143 +[--] consume=0 produce=1 DefList: { N367.t505. LCL_VAR } N369 (???,???) [000560] -c---------- * LEA(b+888) byref REG NA +[--] Contained DefList: { N367.t505. LCL_VAR } N371 ( 24, 30) [000330] ---XG------- * IND ref REG NA +[--] consume=1 produce=1 LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 81: RefPositions {} physReg:NA Preferences=[allIntButFP] IND BB15 regmask=[allIntButFP] minReg=1> DefList: { N371.t330. IND } N373 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 NA REG NA +[--] consume=1 produce=0 Assigning related to BB15 regmask=[allIntButFP] minReg=1 last> Def candidates [allIntButFP], Use candidates [allIntButFP] STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> CHECKING LAST USES for block 15, liveout={V02 V15} ============================== use: {} def: {V15 V34} NEW BLOCK BB16 Setting BB16 as the predecessor for determining incoming variable registers of BB15 DefList: { } N377 ( 3, 2) [000319] ------------ * LCL_VAR ref V15 tmp9 u:2 NA (last use) REG NA +[--] consume=0 produce=1 DefList: { N377.t319. LCL_VAR } N379 (???,???) [000561] ------------ * PUTARG_REG ref REG rcx +[--] consume=1 produce=1 BB16 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> Def candidates [rcx], Use candidates [rcx] Interval 82: RefPositions {} physReg:NA Preferences=[allIntButFP] BB16 regmask=[rcx] minReg=1> PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> DefList: { N379.t561. PUTARG_REG } N381 ( 1, 1) [000102] ------------ * LCL_VAR ref V02 loc0 u:2 NA (last use) REG NA $3c3 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 83: RefPositions {} physReg:NA Preferences=[allIntButFP] LCL_VAR BB16 regmask=[allIntButFP] minReg=1> DefList: { N379.t561. PUTARG_REG; N381.t102. LCL_VAR } N383 (???,???) [000562] ------------ * PUTARG_REG ref REG rdx +[--] consume=1 produce=1 BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> Def candidates [rdx], Use candidates [rdx] Interval 84: RefPositions {} physReg:NA Preferences=[allIntButFP] BB16 regmask=[rdx] minReg=1> PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> DefList: { N379.t561. PUTARG_REG; N383.t562. PUTARG_REG } N385 ( 1, 1) [000103] ------------ * CNS_INT int 0 REG NA $40 +[--] consume=0 produce=1 Def candidates [allIntButFP], Use candidates [allIntButFP] Interval 85: RefPositions {} physReg:NA Preferences=[allIntButFP] CNS_INT BB16 regmask=[allIntButFP] minReg=1> DefList: { N379.t561. PUTARG_REG; N383.t562. PUTARG_REG; N385.t103. CNS_INT } N387 (???,???) [000563] ------------ * PUTARG_REG int REG r8 +[--] consume=1 produce=1 BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> Def candidates [r8], Use candidates [r8] Interval 86: RefPositions {} physReg:NA Preferences=[allIntButFP] BB16 regmask=[r8] minReg=1> PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> DefList: { N379.t561. PUTARG_REG; N383.t562. PUTARG_REG; N387.t563. PUTARG_REG } N389 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void +[--] consume=3 produce=0 BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rax] minReg=1> BB16 regmask=[rcx] minReg=1> BB16 regmask=[rdx] minReg=1> BB16 regmask=[r8] minReg=1> BB16 regmask=[r9] minReg=1> BB16 regmask=[r10] minReg=1> BB16 regmask=[r11] minReg=1> DefList: { } N391 ( 0, 0) [000109] ------------ * IL_OFFSET void IL offset: 0x5a REG NA +[--] consume=0 produce=0 DefList: { } N393 ( 0, 0) [000108] ------------ * RETFILT void REG NA $4c2 +[--] consume=0 produce=0 CHECKING LAST USES for block 16, liveout={} ============================== use: {V02 V15} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) RefPositions {#1@0 #72@79 #89@97} physReg:rcx Preferences=[rbx rsi rdi r12-r15] Interval 1: (V01) RefPositions {#0@0 #3@7 #7@15} physReg:rdx Preferences=[rdx] Interval 2: (V03) RefPositions {#112@110 #113@113 #129@159 #141@189 #180@249} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD5169188] Interval 3: (V05) RefPositions {#181@250 #216@281} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 4: (V08) RefPositions {#266@310 #314@337 #329@345} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 5: (V09) RefPositions {#40@44 #42@47 #49@57} physReg:NA Preferences=[rcx] Interval 6: (V13) RefPositions {#135@172 #136@175} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169448] Interval 7: (V15) RefPositions {#186@260 #189@265 #370@374 #373@379} physReg:NA Preferences=[rcx] Interval 8: (V16) (struct) RefPositions {#6@10 #142@195} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD51694A0] Interval 9: (V17) (struct) RefPositions {#10@18 #46@51 #81@87 #115@117 #144@199} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD51694F8] Interval 10: (V20) (struct) RefPositions {#139@180 #140@185} physReg:NA Preferences=[allIntButFP] Interval 11: (V22) (struct) RefPositions {#137@176 #138@179} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51693F0] Interval 12: (V23) (struct) RefPositions {#143@196 #153@217} physReg:NA Preferences=[allIntButFP] Interval 13: (V24) (struct) RefPositions {#145@200 #155@225} physReg:NA Preferences=[allIntButFP] Interval 14: (V26) RefPositions {#284@318 #286@321} physReg:NA Preferences=[rcx] Interval 15: (V27) RefPositions {#308@330 #310@333} physReg:NA Preferences=[rdx] Interval 16: (V29) RefPositions {#151@210 #152@217 #154@225} physReg:NA Preferences=[allIntButFP] Interval 17: (V30) RefPositions {#148@206 #157@229} physReg:NA Preferences=[rcx] Interval 18: (V33) RefPositions {#68@70 #69@73} physReg:NA Preferences=[allIntButFP] Interval 19: (V34) RefPositions {#36@36 #37@41 #183@257 #366@366 #367@371} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 20: (V35) RefPositions {#125@144 #126@149 #128@159} physReg:NA Preferences=[allIntButFP] Interval 21: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169340] Interval 22: RefPositions {#8@16 #9@17} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169398] Interval 23: RefPositions {#12@26 #14@27} physReg:NA Preferences=[rcx] Interval 24: RefPositions {#16@28 #23@33} physReg:NA Preferences=[rcx] Interval 25: (constant) RefPositions {#17@30 #19@31} physReg:NA Preferences=[rdx] Interval 26: RefPositions {#21@32 #25@33} physReg:NA Preferences=[rdx] Interval 27: RefPositions {#34@34 #35@35} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169708] Interval 28: RefPositions {#38@42 #39@43} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169238] Interval 29: (specialPutArg) RefPositions {#44@48 #54@67} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD5169238] Interval 30: (specialPutArg) RefPositions {#48@52 #56@67} physReg:NA Preferences=[rdx] RelatedInterval [0000017DD5169398] Interval 31: RefPositions {#50@58 #51@61} physReg:NA Preferences=[allIntButFP] Interval 32: RefPositions {#52@62 #57@67} physReg:NA Preferences=[allIntButFP] Interval 33: RefPositions {#66@68 #67@69} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51696B0] Interval 34: (specialPutArg) RefPositions {#74@80 #94@107} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD5169080] Interval 35: RefPositions {#75@82 #77@83} physReg:NA Preferences=[rdx] Interval 36: RefPositions {#79@84 #96@107} physReg:NA Preferences=[rdx] Interval 37: (specialPutArg) RefPositions {#83@88 #98@107} physReg:NA Preferences=[r9] RelatedInterval [0000017DD5169398] Interval 38: (constant) RefPositions {#84@90 #86@91} physReg:NA Preferences=[r8] Interval 39: RefPositions {#88@92 #100@107} physReg:NA Preferences=[r8] Interval 40: RefPositions {#90@98 #91@101} physReg:NA Preferences=[allIntButFP] Interval 41: RefPositions {#92@102 #101@107} physReg:NA Preferences=[allIntButFP] Interval 42: RefPositions {#110@108 #111@109} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169130] Interval 43: RefPositions {#114@114 #117@119} physReg:NA Preferences=[allIntButFP] Interval 44: RefPositions {#116@118 #118@119} physReg:NA Preferences=[allIntButFP] Interval 45: RefPositions {#121@138 #122@141} physReg:NA Preferences=[allIntButFP] Interval 46: RefPositions {#123@142 #124@143} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169760] Interval 47: RefPositions {#131@166 #132@169} physReg:NA Preferences=[allIntButFP] Interval 48: RefPositions {#133@170 #134@171} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169290] Interval 49: RefPositions {#146@204 #147@205} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169658] Interval 50: RefPositions {#149@208 #150@209} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169600] Interval 51: RefPositions {#159@230 #166@235} physReg:NA Preferences=[rcx] Interval 52: RefPositions {#160@232 #162@233} physReg:NA Preferences=[rdx] Interval 53: RefPositions {#164@234 #168@235} physReg:NA Preferences=[rdx] Interval 54: RefPositions {#177@236 #178@239} physReg:NA Preferences=[rax] Interval 55: RefPositions {#184@258 #185@259} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51692E8] Interval 56: RefPositions {#191@266 #203@275} physReg:NA Preferences=[rcx] Interval 57: RefPositions {#192@268 #194@269} physReg:NA Preferences=[rdx] Interval 58: RefPositions {#196@270 #205@275} physReg:NA Preferences=[rdx] Interval 59: (constant) RefPositions {#197@272 #199@273} physReg:NA Preferences=[r8] Interval 60: RefPositions {#201@274 #207@275} physReg:NA Preferences=[r8] Interval 61: (constant) RefPositions {#234@296 #236@297} physReg:NA Preferences=[rcx] Interval 62: RefPositions {#238@298 #240@299} physReg:NA Preferences=[rcx] Interval 63: (constant) RefPositions {#249@304 #251@305} physReg:NA Preferences=[rcx] Interval 64: RefPositions {#253@306 #255@307} physReg:NA Preferences=[rcx] Interval 65: RefPositions {#264@308 #265@309} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51691E0] Interval 66: (constant) RefPositions {#267@312 #269@313} physReg:NA Preferences=[rcx] Interval 67: RefPositions {#271@314 #273@315} physReg:NA Preferences=[rcx] Interval 68: RefPositions {#282@316 #283@317} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169550] Interval 69: RefPositions {#288@322 #295@327} physReg:NA Preferences=[rcx] Interval 70: (constant) RefPositions {#289@324 #291@325} physReg:NA Preferences=[rdx] Interval 71: RefPositions {#293@326 #297@327} physReg:NA Preferences=[rdx] Interval 72: RefPositions {#306@328 #307@329} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51695A8] Interval 73: RefPositions {#312@334 #318@339} physReg:NA Preferences=[rdx] Interval 74: (specialPutArg) RefPositions {#316@338 #320@339} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD51691E0] Interval 75: RefPositions {#331@346 #333@347} physReg:NA Preferences=[rcx] Interval 76: RefPositions {#342@356 #344@357} physReg:NA Preferences=[rcx] Interval 77: RefPositions {#346@358 #353@363} physReg:NA Preferences=[rcx] Interval 78: (constant) RefPositions {#347@360 #349@361} physReg:NA Preferences=[rdx] Interval 79: RefPositions {#351@362 #355@363} physReg:NA Preferences=[rdx] Interval 80: RefPositions {#364@364 #365@365} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169708] Interval 81: RefPositions {#368@372 #369@373} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51692E8] Interval 82: RefPositions {#375@380 #387@389} physReg:NA Preferences=[rcx] Interval 83: RefPositions {#376@382 #378@383} physReg:NA Preferences=[rdx] Interval 84: RefPositions {#380@384 #389@389} physReg:NA Preferences=[rdx] Interval 85: (constant) RefPositions {#381@386 #383@387} physReg:NA Preferences=[r8] Interval 86: RefPositions {#385@388 #391@389} physReg:NA Preferences=[r8] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ #3 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #72 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #7 RefTypeUse LCL_VAR BB01 regmask=[allIntButFP] minReg=1> #5 RefTypeDef IND BB01 regmask=[allIntButFP] minReg=1> BB01 regmask=[allIntButFP] minReg=1 last> #142 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> #9 RefTypeDef IND BB01 regmask=[allIntButFP] minReg=1> BB01 regmask=[allIntButFP] minReg=1 last> #46 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> #14 RefTypeDef IND BB02 regmask=[rcx] minReg=1> #15 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #22 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #23 RefTypeDef PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> #19 RefTypeDef CNS_INT BB02 regmask=[rdx] minReg=1> #20 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> #24 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #25 RefTypeDef PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> #27 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #28 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> #33 RefTypeKill BB02 regmask=[rax] minReg=1 last> #41 RefTypeKill BB02 regmask=[rcx] minReg=1 last> #45 RefTypeKill BB02 regmask=[rdx] minReg=1 last> #61 RefTypeKill BB02 regmask=[r8] minReg=1 last> #62 RefTypeKill BB02 regmask=[r9] minReg=1 last> #63 RefTypeKill BB02 regmask=[r10] minReg=1 last> #64 RefTypeKill BB02 regmask=[r11] minReg=1 last> #58 RefTypeFixedReg BB02 regmask=[rax] minReg=1> #35 RefTypeDef CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allIntButFP] minReg=1 last> #37 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #183 RefTypeUse LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #39 RefTypeDef IND BB02 regmask=[allIntButFP] minReg=1> BB02 regmask=[allIntButFP] minReg=1 last> #42 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #43 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #49 RefTypeUse LCL_VAR BB02 regmask=[rcx] minReg=1 fixed> #53 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #54 RefTypeDef PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> #47 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #81 RefTypeUse LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> #55 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #56 RefTypeDef PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> #51 RefTypeDef IND BB02 regmask=[allIntButFP] minReg=1> BB02 regmask=[allIntButFP] minReg=1 last> #57 RefTypeDef IND BB02 regmask=[allIntButFP] minReg=1> #59 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #60 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[allIntButFP] minReg=1 last> #65 RefTypeKill BB02 regmask=[rax] minReg=1 last> #71 RefTypeKill BB02 regmask=[rcx] minReg=1 last> #76 RefTypeKill BB02 regmask=[rdx] minReg=1 last> #85 RefTypeKill BB02 regmask=[r8] minReg=1 last> #80 RefTypeKill BB02 regmask=[r9] minReg=1 last> #107 RefTypeKill BB02 regmask=[r10] minReg=1 last> #108 RefTypeKill BB02 regmask=[r11] minReg=1 last> #102 RefTypeFixedReg BB02 regmask=[rax] minReg=1> #67 RefTypeDef CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allIntButFP] minReg=1 last> #69 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> #73 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> #89 RefTypeUse LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> #93 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> #94 RefTypeDef PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> #77 RefTypeDef LCL_VAR BB03 regmask=[rdx] minReg=1> #78 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> #95 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> #96 RefTypeDef PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> #82 RefTypeFixedReg BB03 regmask=[r9] minReg=1> #115 RefTypeUse LCL_VAR BB03 regmask=[r9] minReg=1 fixed> #97 RefTypeFixedReg BB03 regmask=[r9] minReg=1> #98 RefTypeDef PUTARG_REG BB03 regmask=[r9] minReg=1 fixed> #86 RefTypeDef CNS_INT BB03 regmask=[r8] minReg=1> #87 RefTypeFixedReg BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> #99 RefTypeFixedReg BB03 regmask=[r8] minReg=1> #100 RefTypeDef PUTARG_REG BB03 regmask=[r8] minReg=1 fixed> LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> #91 RefTypeDef IND BB03 regmask=[allIntButFP] minReg=1> BB03 regmask=[allIntButFP] minReg=1 last> #101 RefTypeDef IND BB03 regmask=[allIntButFP] minReg=1> #103 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> #104 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> #106 RefTypeFixedReg BB03 regmask=[r9] minReg=1> BB03 regmask=[r9] minReg=1 last fixed> #105 RefTypeFixedReg BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> BB03 regmask=[allIntButFP] minReg=1 last> #109 RefTypeKill BB03 regmask=[rax] minReg=1 last> #156 RefTypeKill BB03 regmask=[rcx] minReg=1 last> #161 RefTypeKill BB03 regmask=[rdx] minReg=1 last> #172 RefTypeKill BB03 regmask=[r8] minReg=1 last> #173 RefTypeKill BB03 regmask=[r9] minReg=1 last> #174 RefTypeKill BB03 regmask=[r10] minReg=1 last> #175 RefTypeKill BB03 regmask=[r11] minReg=1 last> #169 RefTypeFixedReg BB03 regmask=[rax] minReg=1> #111 RefTypeDef CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[allIntButFP] minReg=1 last> #113 RefTypeDef STORE_LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #129 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #117 RefTypeDef CAST BB03 regmask=[allIntButFP] minReg=1> #144 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #118 RefTypeDef CAST BB03 regmask=[allIntButFP] minReg=1> BB03 regmask=[allIntButFP] minReg=1 last regOptional> BB03 regmask=[allIntButFP] minReg=1 last> #122 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #124 RefTypeDef IND BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #126 RefTypeDef STORE_LCL_VAR BB05 regmask=[allIntButFP] minReg=1> #128 RefTypeUse LCL_VAR BB05 regmask=[allIntButFP] minReg=1 regOptional> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 last regOptional> #141 RefTypeUse LCL_VAR BB06 regmask=[allIntButFP] minReg=1> #132 RefTypeDef LCL_VAR BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #134 RefTypeDef ADD BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #136 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #138 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #140 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #180 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #153 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #155 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #147 RefTypeDef LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #157 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #150 RefTypeDef LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #152 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #154 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #158 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> #165 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> #166 RefTypeDef PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> #162 RefTypeDef LCL_VAR_ADDR BB07 regmask=[rdx] minReg=1> #163 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> #167 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> #168 RefTypeDef PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> #170 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> #171 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> #176 RefTypeKill BB07 regmask=[rax] minReg=1 last> #188 RefTypeKill BB07 regmask=[rcx] minReg=1 last> #193 RefTypeKill BB07 regmask=[rdx] minReg=1 last> #198 RefTypeKill BB07 regmask=[r8] minReg=1 last> #212 RefTypeKill BB07 regmask=[r9] minReg=1 last> #213 RefTypeKill BB07 regmask=[r10] minReg=1 last> #214 RefTypeKill BB07 regmask=[r11] minReg=1 last> #208 RefTypeFixedReg BB07 regmask=[rax] minReg=1> #178 RefTypeDef CALL BB07 regmask=[rax] minReg=1 fixed> BB07 regmask=[allIntButFP] minReg=1 last regOptional> LCL_VAR BB08 regmask=[allIntButFP] minReg=1 last> #216 RefTypeDef STORE_LCL_VAR BB08 regmask=[allIntButFP] minReg=1> #366 RefTypeUse LCL_VAR BB13 regmask=[allIntButFP] minReg=1 last> #185 RefTypeDef IND BB13 regmask=[allIntButFP] minReg=1> BB13 regmask=[allIntButFP] minReg=1 last> #189 RefTypeDef STORE_LCL_VAR BB13 regmask=[allIntButFP] minReg=1> #190 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> #370 RefTypeUse LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> #202 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> #203 RefTypeDef PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> #194 RefTypeDef LCL_VAR BB14 regmask=[rdx] minReg=1> #195 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> #204 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> #205 RefTypeDef PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> #199 RefTypeDef CNS_INT BB14 regmask=[r8] minReg=1> #200 RefTypeFixedReg BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> #206 RefTypeFixedReg BB14 regmask=[r8] minReg=1> #207 RefTypeDef PUTARG_REG BB14 regmask=[r8] minReg=1 fixed> #209 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> #210 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> #211 RefTypeFixedReg BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> #215 RefTypeKill BB14 regmask=[rax] minReg=1 last> #219 RefTypeKill BB14 regmask=[rcx] minReg=1 last> #220 RefTypeKill BB14 regmask=[rdx] minReg=1 last> #221 RefTypeKill BB14 regmask=[r8] minReg=1 last> #222 RefTypeKill BB14 regmask=[r9] minReg=1 last> #223 RefTypeKill BB14 regmask=[r10] minReg=1 last> #224 RefTypeKill BB14 regmask=[r11] minReg=1 last> #218 RefTypeFixedReg BB14 regmask=[rax] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last fixed> #226 RefTypeKill BB09 regmask=[rax] minReg=1 last> #227 RefTypeKill BB09 regmask=[rcx] minReg=1 last> #228 RefTypeKill BB09 regmask=[rdx] minReg=1 last> #229 RefTypeKill BB09 regmask=[r8] minReg=1 last> #230 RefTypeKill BB09 regmask=[r9] minReg=1 last> #231 RefTypeKill BB09 regmask=[r10] minReg=1 last> #232 RefTypeKill BB09 regmask=[r11] minReg=1 last> #241 RefTypeKill BB10 regmask=[rax] minReg=1 last> #235 RefTypeKill BB10 regmask=[rcx] minReg=1 last> #243 RefTypeKill BB10 regmask=[rdx] minReg=1 last> #244 RefTypeKill BB10 regmask=[r8] minReg=1 last> #245 RefTypeKill BB10 regmask=[r9] minReg=1 last> #246 RefTypeKill BB10 regmask=[r10] minReg=1 last> #247 RefTypeKill BB10 regmask=[r11] minReg=1 last> #236 RefTypeDef CNS_INT BB11 regmask=[rcx] minReg=1> #237 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #239 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> #240 RefTypeDef PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> #242 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #256 RefTypeKill BB11 regmask=[rax] minReg=1 last> #250 RefTypeKill BB11 regmask=[rcx] minReg=1 last> #258 RefTypeKill BB11 regmask=[rdx] minReg=1 last> #259 RefTypeKill BB11 regmask=[r8] minReg=1 last> #260 RefTypeKill BB11 regmask=[r9] minReg=1 last> #261 RefTypeKill BB11 regmask=[r10] minReg=1 last> #262 RefTypeKill BB11 regmask=[r11] minReg=1 last> #251 RefTypeDef CNS_INT BB12 regmask=[rcx] minReg=1> #252 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #254 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #255 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #257 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #263 RefTypeKill BB12 regmask=[rax] minReg=1 last> #268 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #276 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #277 RefTypeKill BB12 regmask=[r8] minReg=1 last> #278 RefTypeKill BB12 regmask=[r9] minReg=1 last> #279 RefTypeKill BB12 regmask=[r10] minReg=1 last> #280 RefTypeKill BB12 regmask=[r11] minReg=1 last> #274 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #265 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allIntButFP] minReg=1 last> #314 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #269 RefTypeDef CNS_INT BB12 regmask=[rcx] minReg=1> #270 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #272 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #273 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #275 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #281 RefTypeKill BB12 regmask=[rax] minReg=1 last> #285 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #290 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #301 RefTypeKill BB12 regmask=[r8] minReg=1 last> #302 RefTypeKill BB12 regmask=[r9] minReg=1 last> #303 RefTypeKill BB12 regmask=[r10] minReg=1 last> #304 RefTypeKill BB12 regmask=[r11] minReg=1 last> #298 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #283 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allIntButFP] minReg=1 last> #286 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #287 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> #294 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #295 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #291 RefTypeDef CNS_INT BB12 regmask=[rdx] minReg=1> #292 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #296 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> #297 RefTypeDef PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> #299 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #300 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #305 RefTypeKill BB12 regmask=[rax] minReg=1 last> #313 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #309 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #324 RefTypeKill BB12 regmask=[r8] minReg=1 last> #325 RefTypeKill BB12 regmask=[r9] minReg=1 last> #326 RefTypeKill BB12 regmask=[r10] minReg=1 last> #327 RefTypeKill BB12 regmask=[r11] minReg=1 last> #321 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #307 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allIntButFP] minReg=1 last> #310 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #311 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> #317 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> #318 RefTypeDef PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> #315 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #329 RefTypeUse LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> #319 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #320 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #323 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #322 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #334 RefTypeKill BB12 regmask=[rax] minReg=1 last> #328 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #336 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #337 RefTypeKill BB12 regmask=[r8] minReg=1 last> #338 RefTypeKill BB12 regmask=[r9] minReg=1 last> #339 RefTypeKill BB12 regmask=[r10] minReg=1 last> #340 RefTypeKill BB12 regmask=[r11] minReg=1 last> #330 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> #332 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #333 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #335 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #356 RefTypeKill BB12 regmask=[rax] minReg=1 last> #343 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #348 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #359 RefTypeKill BB12 regmask=[r8] minReg=1 last> #360 RefTypeKill BB12 regmask=[r9] minReg=1 last> #361 RefTypeKill BB12 regmask=[r10] minReg=1 last> #362 RefTypeKill BB12 regmask=[r11] minReg=1 last> #344 RefTypeDef IND BB15 regmask=[rcx] minReg=1> #345 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> #352 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> #353 RefTypeDef PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> #349 RefTypeDef CNS_INT BB15 regmask=[rdx] minReg=1> #350 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> #354 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> #355 RefTypeDef PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> #357 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> #358 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> #363 RefTypeKill BB15 regmask=[rax] minReg=1 last> #372 RefTypeKill BB15 regmask=[rcx] minReg=1 last> #377 RefTypeKill BB15 regmask=[rdx] minReg=1 last> #382 RefTypeKill BB15 regmask=[r8] minReg=1 last> #396 RefTypeKill BB15 regmask=[r9] minReg=1 last> #397 RefTypeKill BB15 regmask=[r10] minReg=1 last> #398 RefTypeKill BB15 regmask=[r11] minReg=1 last> #392 RefTypeFixedReg BB15 regmask=[rax] minReg=1> #365 RefTypeDef CALL BB15 regmask=[rax] minReg=1 fixed> BB15 regmask=[allIntButFP] minReg=1 last> #367 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> #369 RefTypeDef IND BB15 regmask=[allIntButFP] minReg=1> BB15 regmask=[allIntButFP] minReg=1 last> #373 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> #374 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> #386 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> #387 RefTypeDef PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> #378 RefTypeDef LCL_VAR BB16 regmask=[rdx] minReg=1> #379 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> #388 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> #389 RefTypeDef PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> #383 RefTypeDef CNS_INT BB16 regmask=[r8] minReg=1> #384 RefTypeFixedReg BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> #390 RefTypeFixedReg BB16 regmask=[r8] minReg=1> #391 RefTypeDef PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> #393 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> #394 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> #395 RefTypeFixedReg BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rcx] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[r8] minReg=1 last> BB16 regmask=[r9] minReg=1 last> BB16 regmask=[r10] minReg=1 last> BB16 regmask=[r11] minReg=1 last> ----------------- #3 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #7 RefTypeUse LCL_VAR BB01 regmask=[allIntButFP] minReg=1> LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> ----------------- #37 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #183 RefTypeUse LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #366 RefTypeUse LCL_VAR BB13 regmask=[allIntButFP] minReg=1 last> #367 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> ----------------- #113 RefTypeDef STORE_LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #129 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #141 RefTypeUse LCL_VAR BB06 regmask=[allIntButFP] minReg=1> #180 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB08 regmask=[allIntButFP] minReg=1 last> ----------------- #46 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> #81 RefTypeUse LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> #115 RefTypeUse LCL_VAR BB03 regmask=[r9] minReg=1 fixed> #144 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #72 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #89 RefTypeUse LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> ----------------- #136 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #152 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #154 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #42 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #49 RefTypeUse LCL_VAR BB02 regmask=[rcx] minReg=1 fixed> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> ----------------- #157 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> ----------------- #189 RefTypeDef STORE_LCL_VAR BB13 regmask=[allIntButFP] minReg=1> #370 RefTypeUse LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> #373 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> ----------------- #126 RefTypeDef STORE_LCL_VAR BB05 regmask=[allIntButFP] minReg=1> #128 RefTypeUse LCL_VAR BB05 regmask=[allIntButFP] minReg=1 regOptional> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 last regOptional> ----------------- #142 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #140 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #138 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #153 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #69 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> ----------------- #216 RefTypeDef STORE_LCL_VAR BB08 regmask=[allIntButFP] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last fixed> ----------------- #155 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> ----------------- #314 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #329 RefTypeUse LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> ----------------- #286 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> ----------------- #310 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V01 V00 BB01 [???..???), preds={} succs={BB02} ===== N003. V01(L1) N005. LEA(b+0) N007. IND Use:(#3) Def:(#4) Pref: N009. V16(L8) Use:(#5) * Def:(#6) Pref: N011. V01(L1) N013. LEA(b+8) N015. IND Use:(#7) * Def:(#8) Pref: N017. V17(L9) Use:(#9) * Def:(#10) Pref: BB02 [000..012), preds={BB01} succs={BB03} ===== N021. IL_OFFSET IL offset: 0x0 REG NA N023. CNS_INT(h) 0x17dd3b1e7b0 cid/mid REG NA N025. IND Def:(#12) N027. PUTARG_REG Use:(#14) Fixed:rcx(#13) * Def:(#16) rcx N029. CNS_INT 327 REG NA Def:(#17) N031. PUTARG_REG Use:(#19) Fixed:rdx(#18) * Def:(#21) rdx N033. CALL help Use:(#23) Fixed:rcx(#22) * Use:(#25) Fixed:rdx(#24) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#34) rax Pref: N035. V34(L19) Use:(#35) * Def:(#36) N037. V34(L19) N039. LEA(b+888) N041. IND Use:(#37) Def:(#38) Pref: N043. V09(L5) Use:(#39) * Def:(#40) N045. V09(L5) N047. PUTARG_REG Use:(#42) Fixed:rcx(#41) Def:(#44) rcx Pref: N049. V17(L9) N051. PUTARG_REG Use:(#46) Fixed:rdx(#45) Def:(#48) rdx Pref: N053. V09(L5) N055. LEA(b+0) N057. IND Use:(#49) * Def:(#50) N059. LEA(b+64) N061. IND Use:(#51) * Def:(#52) N063. LEA(b+32) N065. IND N067. CALLV ind Use:(#54) Fixed:rcx(#53) * Use:(#56) Fixed:rdx(#55) * Use:(#57) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#66) rax Pref: N069. V33(L18) Use:(#67) * Def:(#68) N071. V33(L18) N073. V02 MEM Use:(#69) * BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ===== N077. V00(L0) N079. PUTARG_REG Use:(#72) Fixed:rcx(#71) Def:(#74) rcx Pref: N081. V02 MEM Def:(#75) N083. PUTARG_REG Use:(#77) Fixed:rdx(#76) * Def:(#79) rdx N085. V17(L9) N087. PUTARG_REG Use:(#81) Fixed:r9(#80) Def:(#83) r9 Pref: N089. CNS_INT 0 REG NA Def:(#84) N091. PUTARG_REG Use:(#86) Fixed:r8(#85) * Def:(#88) r8 N093. V00(L0) N095. LEA(b+0) N097. IND Use:(#89) * Def:(#90) N099. LEA(b+96) N101. IND Use:(#91) * Def:(#92) N103. LEA(b+16) N105. IND N107. CALLV ind Use:(#94) Fixed:rcx(#93) * Use:(#96) Fixed:rdx(#95) * Use:(#98) Fixed:r9(#97) * Use:(#100) Fixed:r8(#99) * Use:(#101) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#110) rax Pref: N109. V03(L2) Use:(#111) * Def:(#112) Pref: N111. V03(L2) N113. CAST Use:(#113) Def:(#114) N115. V17(L9) N117. CAST Use:(#115) Def:(#116) N119. GT Use:(#117) * Use:(#118) * N121. JTRUE BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ===== N125. IL_OFFSET IL offset: 0x39 REG NA N127. V02 MEM N129. CNS_INT null REG NA N131. EQ N133. JTRUE BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ===== N137. V02 MEM Def:(#121) N139. LEA(b+8) N141. IND Use:(#122) * Def:(#123) Pref: N143. V35(L20) Use:(#124) * Def:(#125) N145. V35(L20) N147. CNS_INT 0 REG NA N149. LT Use:(#126) N151. JTRUE BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ===== N155. V35(L20) N157. V03(L2) N159. LT Use:(#128) * Use:(#129) N161. JTRUE BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ===== N165. V02 MEM Def:(#131) N167. CNS_INT 16 field offset Fseq[m_arrayData] REG NA N169. ADD Use:(#132) * Def:(#133) Pref: N171. V13(L6) Use:(#134) * Def:(#135) Pref: N173. V13(L6) N175. V22(L11) Use:(#136) * Def:(#137) Pref: N177. V22(L11) N179. V20(L10) Use:(#138) * Def:(#139) N181. IL_OFFSET IL offset: 0x41 REG NA N183. V20(L10) N185. V18 MEM Use:(#140) * N187. V03(L2) N189. V19 MEM Use:(#141) N191. IL_OFFSET IL offset: 0x42 REG NA N193. V16(L8) N195. V23(L12) Use:(#142) * Def:(#143) N197. V17(L9) N199. V24(L13) Use:(#144) * Def:(#145) N201. IL_OFFSET IL offset: 0x42 REG NA N203. LCL_VAR_ADDR V04 loc2 NA byref V04._pointer (offs=0x00) -> V18 tmp12 int V04._length (offs=0x08) -> V19 tmp13 REG NA Def:(#146) Pref: N205. V30(L17) Use:(#147) * Def:(#148) N207. LCL_VAR_ADDR V28 tmp22 NA REG NA Def:(#149) Pref: N209. V29(L16) Use:(#150) * Def:(#151) N211. V29(L16) N213. LEA(b+0) N215. V23(L12) N217. STOREIND Use:(#152) Use:(#153) * N219. V29(L16) N221. LEA(b+8) N223. V24(L13) N225. STOREIND Use:(#154) * Use:(#155) * N227. V30(L17) N229. PUTARG_REG Use:(#157) Fixed:rcx(#156) * Def:(#159) rcx N231. LCL_VAR_ADDR V28 tmp22 NA REG NA Def:(#160) N233. PUTARG_REG Use:(#162) Fixed:rdx(#161) * Def:(#164) rdx N235. CALL Use:(#166) Fixed:rcx(#165) * Use:(#168) Fixed:rdx(#167) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#177) rax N237. CNS_INT 0 REG NA N239. EQ Use:(#178) * N241. JTRUE BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ===== N245. IL_OFFSET IL offset: 0x4a REG NA N247. V03(L2) N249. V05(L3) Use:(#180) * Def:(#181) BB13 [04E..05B), preds={BB08} succs={BB14} ===== N253. V34(L19) N255. LEA(b+888) N257. IND Use:(#183) * Def:(#184) Pref: N259. V15(L7) Use:(#185) * Def:(#186) BB14 [05B..05D) (return), preds={BB13} succs={} ===== N263. V15(L7) N265. PUTARG_REG Use:(#189) Fixed:rcx(#188) * Def:(#191) rcx N267. V02 MEM Def:(#192) N269. PUTARG_REG Use:(#194) Fixed:rdx(#193) * Def:(#196) rdx N271. CNS_INT 0 REG NA Def:(#197) N273. PUTARG_REG Use:(#199) Fixed:r8(#198) * Def:(#201) r8 N275. CALL nullcheck Use:(#203) Fixed:rcx(#202) * Use:(#205) Fixed:rdx(#204) * Use:(#207) Fixed:r8(#206) * Kill: rax rcx rdx r8 r9 r10 r11 N277. IL_OFFSET IL offset: 0x5b REG NA N279. V05(L3) N281. RETURN Use:(#216) Fixed:rax(#215) * BB09 [042..043) (throw), preds={BB07} succs={} ===== N285. IL_OFFSET IL offset: 0x42 REG NA N287. CALL Kill: rax rcx rdx r8 r9 r10 r11 BB10 [000..000) (throw), preds={BB05,BB06} succs={} ===== N291. CALL Kill: rax rcx rdx r8 r9 r10 r11 BB11 [000..000) (throw), preds={BB04} succs={} ===== N295. CNS_INT 2 REG NA Def:(#234) N297. PUTARG_REG Use:(#236) Fixed:rcx(#235) * Def:(#238) rcx N299. CALL Use:(#240) Fixed:rcx(#239) * Kill: rax rcx rdx r8 r9 r10 r11 BB12 [02E..039) (throw), preds={BB03} succs={} ===== N303. CNS_INT(h) 0x17dd3b22ac8 method REG NA Def:(#249) N305. PUTARG_REG Use:(#251) Fixed:rcx(#250) * Def:(#253) rcx N307. CALL help Use:(#255) Fixed:rcx(#254) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#264) rax Pref: N309. V08(L4) Use:(#265) * Def:(#266) N311. CNS_INT 0xE904 REG NA Def:(#267) N313. PUTARG_REG Use:(#269) Fixed:rcx(#268) * Def:(#271) rcx N315. CALL help Use:(#273) Fixed:rcx(#272) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#282) rax Pref: N317. V26(L14) Use:(#283) * Def:(#284) N319. V26(L14) N321. PUTARG_REG Use:(#286) Fixed:rcx(#285) * Def:(#288) rcx N323. CNS_INT null REG NA Def:(#289) N325. PUTARG_REG Use:(#291) Fixed:rdx(#290) * Def:(#293) rdx N327. CALL Use:(#295) Fixed:rcx(#294) * Use:(#297) Fixed:rdx(#296) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#306) rax Pref: N329. V27(L15) Use:(#307) * Def:(#308) N331. V27(L15) N333. PUTARG_REG Use:(#310) Fixed:rdx(#309) * Def:(#312) rdx N335. V08(L4) N337. PUTARG_REG Use:(#314) Fixed:rcx(#313) Def:(#316) rcx Pref: N339. CALL Use:(#318) Fixed:rdx(#317) * Use:(#320) Fixed:rcx(#319) * Kill: rax rcx rdx r8 r9 r10 r11 N341. IL_OFFSET IL offset: 0x38 REG NA N343. V08(L4) N345. PUTARG_REG Use:(#329) Fixed:rcx(#328) * Def:(#331) rcx N347. CALL help Use:(#333) Fixed:rcx(#332) * Kill: rax rcx rdx r8 r9 r10 r11 BB15 [04E..05B), preds={} succs={BB16} ===== N351. IL_OFFSET IL offset: 0x4e REG NA N353. CNS_INT(h) 0x17dd3b1e7b0 cid/mid REG NA N355. IND Def:(#342) N357. PUTARG_REG Use:(#344) Fixed:rcx(#343) * Def:(#346) rcx N359. CNS_INT 327 REG NA Def:(#347) N361. PUTARG_REG Use:(#349) Fixed:rdx(#348) * Def:(#351) rdx N363. CALL help Use:(#353) Fixed:rcx(#352) * Use:(#355) Fixed:rdx(#354) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#364) rax Pref: N365. V34(L19) Use:(#365) * Def:(#366) N367. V34(L19) N369. LEA(b+888) N371. IND Use:(#367) * Def:(#368) Pref: N373. V15(L7) Use:(#369) * Def:(#370) BB16 [???..???) (finret), preds={BB15} succs={} ===== N377. V15(L7) N379. PUTARG_REG Use:(#373) Fixed:rcx(#372) * Def:(#375) rcx N381. V02 MEM Def:(#376) N383. PUTARG_REG Use:(#378) Fixed:rdx(#377) * Def:(#380) rdx N385. CNS_INT 0 REG NA Def:(#381) N387. PUTARG_REG Use:(#383) Fixed:r8(#382) * Def:(#385) r8 N389. CALL nullcheck Use:(#387) Fixed:rcx(#386) * Use:(#389) Fixed:rdx(#388) * Use:(#391) Fixed:r8(#390) * Kill: rax rcx rdx r8 r9 r10 r11 N391. IL_OFFSET IL offset: 0x5a REG NA N393. RETFILT Linear scan intervals after buildIntervals: Interval 0: (V00) RefPositions {#1@0 #72@79 #89@97} physReg:rcx Preferences=[rbx rsi rdi r12-r15] Interval 1: (V01) RefPositions {#0@0 #3@7 #7@15} physReg:rdx Preferences=[rdx] Interval 2: (V03) RefPositions {#112@110 #113@113 #129@159 #141@189 #180@249} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD5169188] Interval 3: (V05) RefPositions {#181@250 #216@281} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 4: (V08) RefPositions {#266@310 #314@337 #329@345} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 5: (V09) RefPositions {#40@44 #42@47 #49@57} physReg:NA Preferences=[rcx] Interval 6: (V13) RefPositions {#135@172 #136@175} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169448] Interval 7: (V15) RefPositions {#186@260 #189@265 #370@374 #373@379} physReg:NA Preferences=[rcx] Interval 8: (V16) (struct) RefPositions {#6@10 #142@195} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD51694A0] Interval 9: (V17) (struct) RefPositions {#10@18 #46@51 #81@87 #115@117 #144@199} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD51694F8] Interval 10: (V20) (struct) RefPositions {#139@180 #140@185} physReg:NA Preferences=[allIntButFP] Interval 11: (V22) (struct) RefPositions {#137@176 #138@179} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51693F0] Interval 12: (V23) (struct) RefPositions {#143@196 #153@217} physReg:NA Preferences=[allIntButFP] Interval 13: (V24) (struct) RefPositions {#145@200 #155@225} physReg:NA Preferences=[allIntButFP] Interval 14: (V26) RefPositions {#284@318 #286@321} physReg:NA Preferences=[rcx] Interval 15: (V27) RefPositions {#308@330 #310@333} physReg:NA Preferences=[rdx] Interval 16: (V29) RefPositions {#151@210 #152@217 #154@225} physReg:NA Preferences=[allIntButFP] Interval 17: (V30) RefPositions {#148@206 #157@229} physReg:NA Preferences=[rcx] Interval 18: (V33) RefPositions {#68@70 #69@73} physReg:NA Preferences=[allIntButFP] Interval 19: (V34) RefPositions {#36@36 #37@41 #183@257 #366@366 #367@371} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 20: (V35) RefPositions {#125@144 #126@149 #128@159} physReg:NA Preferences=[allIntButFP] Interval 21: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169340] Interval 22: RefPositions {#8@16 #9@17} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169398] Interval 23: RefPositions {#12@26 #14@27} physReg:NA Preferences=[rcx] Interval 24: RefPositions {#16@28 #23@33} physReg:NA Preferences=[rcx] Interval 25: (constant) RefPositions {#17@30 #19@31} physReg:NA Preferences=[rdx] Interval 26: RefPositions {#21@32 #25@33} physReg:NA Preferences=[rdx] Interval 27: RefPositions {#34@34 #35@35} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169708] Interval 28: RefPositions {#38@42 #39@43} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169238] Interval 29: (specialPutArg) RefPositions {#44@48 #54@67} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD5169238] Interval 30: (specialPutArg) RefPositions {#48@52 #56@67} physReg:NA Preferences=[rdx] RelatedInterval [0000017DD5169398] Interval 31: RefPositions {#50@58 #51@61} physReg:NA Preferences=[allIntButFP] Interval 32: RefPositions {#52@62 #57@67} physReg:NA Preferences=[allIntButFP] Interval 33: RefPositions {#66@68 #67@69} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51696B0] Interval 34: (specialPutArg) RefPositions {#74@80 #94@107} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD5169080] Interval 35: RefPositions {#75@82 #77@83} physReg:NA Preferences=[rdx] Interval 36: RefPositions {#79@84 #96@107} physReg:NA Preferences=[rdx] Interval 37: (specialPutArg) RefPositions {#83@88 #98@107} physReg:NA Preferences=[r9] RelatedInterval [0000017DD5169398] Interval 38: (constant) RefPositions {#84@90 #86@91} physReg:NA Preferences=[r8] Interval 39: RefPositions {#88@92 #100@107} physReg:NA Preferences=[r8] Interval 40: RefPositions {#90@98 #91@101} physReg:NA Preferences=[allIntButFP] Interval 41: RefPositions {#92@102 #101@107} physReg:NA Preferences=[allIntButFP] Interval 42: RefPositions {#110@108 #111@109} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169130] Interval 43: RefPositions {#114@114 #117@119} physReg:NA Preferences=[allIntButFP] Interval 44: RefPositions {#116@118 #118@119} physReg:NA Preferences=[allIntButFP] Interval 45: RefPositions {#121@138 #122@141} physReg:NA Preferences=[allIntButFP] Interval 46: RefPositions {#123@142 #124@143} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169760] Interval 47: RefPositions {#131@166 #132@169} physReg:NA Preferences=[allIntButFP] Interval 48: RefPositions {#133@170 #134@171} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169290] Interval 49: RefPositions {#146@204 #147@205} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169658] Interval 50: RefPositions {#149@208 #150@209} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169600] Interval 51: RefPositions {#159@230 #166@235} physReg:NA Preferences=[rcx] Interval 52: RefPositions {#160@232 #162@233} physReg:NA Preferences=[rdx] Interval 53: RefPositions {#164@234 #168@235} physReg:NA Preferences=[rdx] Interval 54: RefPositions {#177@236 #178@239} physReg:NA Preferences=[rax] Interval 55: RefPositions {#184@258 #185@259} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51692E8] Interval 56: RefPositions {#191@266 #203@275} physReg:NA Preferences=[rcx] Interval 57: RefPositions {#192@268 #194@269} physReg:NA Preferences=[rdx] Interval 58: RefPositions {#196@270 #205@275} physReg:NA Preferences=[rdx] Interval 59: (constant) RefPositions {#197@272 #199@273} physReg:NA Preferences=[r8] Interval 60: RefPositions {#201@274 #207@275} physReg:NA Preferences=[r8] Interval 61: (constant) RefPositions {#234@296 #236@297} physReg:NA Preferences=[rcx] Interval 62: RefPositions {#238@298 #240@299} physReg:NA Preferences=[rcx] Interval 63: (constant) RefPositions {#249@304 #251@305} physReg:NA Preferences=[rcx] Interval 64: RefPositions {#253@306 #255@307} physReg:NA Preferences=[rcx] Interval 65: RefPositions {#264@308 #265@309} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51691E0] Interval 66: (constant) RefPositions {#267@312 #269@313} physReg:NA Preferences=[rcx] Interval 67: RefPositions {#271@314 #273@315} physReg:NA Preferences=[rcx] Interval 68: RefPositions {#282@316 #283@317} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169550] Interval 69: RefPositions {#288@322 #295@327} physReg:NA Preferences=[rcx] Interval 70: (constant) RefPositions {#289@324 #291@325} physReg:NA Preferences=[rdx] Interval 71: RefPositions {#293@326 #297@327} physReg:NA Preferences=[rdx] Interval 72: RefPositions {#306@328 #307@329} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51695A8] Interval 73: RefPositions {#312@334 #318@339} physReg:NA Preferences=[rdx] Interval 74: (specialPutArg) RefPositions {#316@338 #320@339} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD51691E0] Interval 75: RefPositions {#331@346 #333@347} physReg:NA Preferences=[rcx] Interval 76: RefPositions {#342@356 #344@357} physReg:NA Preferences=[rcx] Interval 77: RefPositions {#346@358 #353@363} physReg:NA Preferences=[rcx] Interval 78: (constant) RefPositions {#347@360 #349@361} physReg:NA Preferences=[rdx] Interval 79: RefPositions {#351@362 #355@363} physReg:NA Preferences=[rdx] Interval 80: RefPositions {#364@364 #365@365} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169708] Interval 81: RefPositions {#368@372 #369@373} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51692E8] Interval 82: RefPositions {#375@380 #387@389} physReg:NA Preferences=[rcx] Interval 83: RefPositions {#376@382 #378@383} physReg:NA Preferences=[rdx] Interval 84: RefPositions {#380@384 #389@389} physReg:NA Preferences=[rdx] Interval 85: (constant) RefPositions {#381@386 #383@387} physReg:NA Preferences=[r8] Interval 86: RefPositions {#385@388 #391@389} physReg:NA Preferences=[r8] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) RefPositions {#1@0 #72@79 #89@97} physReg:rcx Preferences=[rbx rsi rdi r12-r15] Interval 1: (V01) RefPositions {#0@0 #3@7 #7@15} physReg:rdx Preferences=[rdx] Interval 2: (V03) RefPositions {#112@110 #113@113 #129@159 #141@189 #180@249} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD5169188] Interval 3: (V05) RefPositions {#181@250 #216@281} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 4: (V08) RefPositions {#266@310 #314@337 #329@345} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 5: (V09) RefPositions {#40@44 #42@47 #49@57} physReg:NA Preferences=[rcx] Interval 6: (V13) RefPositions {#135@172 #136@175} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169448] Interval 7: (V15) RefPositions {#186@260 #189@265 #370@374 #373@379} physReg:NA Preferences=[rcx] Interval 8: (V16) (struct) RefPositions {#6@10 #142@195} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD51694A0] Interval 9: (V17) (struct) RefPositions {#10@18 #46@51 #81@87 #115@117 #144@199} physReg:NA Preferences=[rbx rsi rdi r12-r15] RelatedInterval [0000017DD51694F8] Interval 10: (V20) (struct) RefPositions {#139@180 #140@185} physReg:NA Preferences=[allIntButFP] Interval 11: (V22) (struct) RefPositions {#137@176 #138@179} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51693F0] Interval 12: (V23) (struct) RefPositions {#143@196 #153@217} physReg:NA Preferences=[allIntButFP] Interval 13: (V24) (struct) RefPositions {#145@200 #155@225} physReg:NA Preferences=[allIntButFP] Interval 14: (V26) RefPositions {#284@318 #286@321} physReg:NA Preferences=[rcx] Interval 15: (V27) RefPositions {#308@330 #310@333} physReg:NA Preferences=[rdx] Interval 16: (V29) RefPositions {#151@210 #152@217 #154@225} physReg:NA Preferences=[allIntButFP] Interval 17: (V30) RefPositions {#148@206 #157@229} physReg:NA Preferences=[rcx] Interval 18: (V33) RefPositions {#68@70 #69@73} physReg:NA Preferences=[allIntButFP] Interval 19: (V34) RefPositions {#36@36 #37@41 #183@257 #366@366 #367@371} physReg:NA Preferences=[rbx rsi rdi r12-r15] Interval 20: (V35) RefPositions {#125@144 #126@149 #128@159} physReg:NA Preferences=[allIntButFP] Interval 21: RefPositions {#4@8 #5@9} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169340] Interval 22: RefPositions {#8@16 #9@17} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169398] Interval 23: RefPositions {#12@26 #14@27} physReg:NA Preferences=[rcx] Interval 24: RefPositions {#16@28 #23@33} physReg:NA Preferences=[rcx] Interval 25: (constant) RefPositions {#17@30 #19@31} physReg:NA Preferences=[rdx] Interval 26: RefPositions {#21@32 #25@33} physReg:NA Preferences=[rdx] Interval 27: RefPositions {#34@34 #35@35} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169708] Interval 28: RefPositions {#38@42 #39@43} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169238] Interval 29: (specialPutArg) RefPositions {#44@48 #54@67} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD5169238] Interval 30: (specialPutArg) RefPositions {#48@52 #56@67} physReg:NA Preferences=[rdx] RelatedInterval [0000017DD5169398] Interval 31: RefPositions {#50@58 #51@61} physReg:NA Preferences=[allIntButFP] Interval 32: RefPositions {#52@62 #57@67} physReg:NA Preferences=[allIntButFP] Interval 33: RefPositions {#66@68 #67@69} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51696B0] Interval 34: (specialPutArg) RefPositions {#74@80 #94@107} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD5169080] Interval 35: RefPositions {#75@82 #77@83} physReg:NA Preferences=[rdx] Interval 36: RefPositions {#79@84 #96@107} physReg:NA Preferences=[rdx] Interval 37: (specialPutArg) RefPositions {#83@88 #98@107} physReg:NA Preferences=[r9] RelatedInterval [0000017DD5169398] Interval 38: (constant) RefPositions {#84@90 #86@91} physReg:NA Preferences=[r8] Interval 39: RefPositions {#88@92 #100@107} physReg:NA Preferences=[r8] Interval 40: RefPositions {#90@98 #91@101} physReg:NA Preferences=[allIntButFP] Interval 41: RefPositions {#92@102 #101@107} physReg:NA Preferences=[allIntButFP] Interval 42: RefPositions {#110@108 #111@109} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169130] Interval 43: RefPositions {#114@114 #117@119} physReg:NA Preferences=[allIntButFP] Interval 44: RefPositions {#116@118 #118@119} physReg:NA Preferences=[allIntButFP] Interval 45: RefPositions {#121@138 #122@141} physReg:NA Preferences=[allIntButFP] Interval 46: RefPositions {#123@142 #124@143} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169760] Interval 47: RefPositions {#131@166 #132@169} physReg:NA Preferences=[allIntButFP] Interval 48: RefPositions {#133@170 #134@171} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169290] Interval 49: RefPositions {#146@204 #147@205} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169658] Interval 50: RefPositions {#149@208 #150@209} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD5169600] Interval 51: RefPositions {#159@230 #166@235} physReg:NA Preferences=[rcx] Interval 52: RefPositions {#160@232 #162@233} physReg:NA Preferences=[rdx] Interval 53: RefPositions {#164@234 #168@235} physReg:NA Preferences=[rdx] Interval 54: RefPositions {#177@236 #178@239} physReg:NA Preferences=[rax] Interval 55: RefPositions {#184@258 #185@259} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51692E8] Interval 56: RefPositions {#191@266 #203@275} physReg:NA Preferences=[rcx] Interval 57: RefPositions {#192@268 #194@269} physReg:NA Preferences=[rdx] Interval 58: RefPositions {#196@270 #205@275} physReg:NA Preferences=[rdx] Interval 59: (constant) RefPositions {#197@272 #199@273} physReg:NA Preferences=[r8] Interval 60: RefPositions {#201@274 #207@275} physReg:NA Preferences=[r8] Interval 61: (constant) RefPositions {#234@296 #236@297} physReg:NA Preferences=[rcx] Interval 62: RefPositions {#238@298 #240@299} physReg:NA Preferences=[rcx] Interval 63: (constant) RefPositions {#249@304 #251@305} physReg:NA Preferences=[rcx] Interval 64: RefPositions {#253@306 #255@307} physReg:NA Preferences=[rcx] Interval 65: RefPositions {#264@308 #265@309} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51691E0] Interval 66: (constant) RefPositions {#267@312 #269@313} physReg:NA Preferences=[rcx] Interval 67: RefPositions {#271@314 #273@315} physReg:NA Preferences=[rcx] Interval 68: RefPositions {#282@316 #283@317} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169550] Interval 69: RefPositions {#288@322 #295@327} physReg:NA Preferences=[rcx] Interval 70: (constant) RefPositions {#289@324 #291@325} physReg:NA Preferences=[rdx] Interval 71: RefPositions {#293@326 #297@327} physReg:NA Preferences=[rdx] Interval 72: RefPositions {#306@328 #307@329} physReg:NA Preferences=[rax] RelatedInterval [0000017DD51695A8] Interval 73: RefPositions {#312@334 #318@339} physReg:NA Preferences=[rdx] Interval 74: (specialPutArg) RefPositions {#316@338 #320@339} physReg:NA Preferences=[rcx] RelatedInterval [0000017DD51691E0] Interval 75: RefPositions {#331@346 #333@347} physReg:NA Preferences=[rcx] Interval 76: RefPositions {#342@356 #344@357} physReg:NA Preferences=[rcx] Interval 77: RefPositions {#346@358 #353@363} physReg:NA Preferences=[rcx] Interval 78: (constant) RefPositions {#347@360 #349@361} physReg:NA Preferences=[rdx] Interval 79: RefPositions {#351@362 #355@363} physReg:NA Preferences=[rdx] Interval 80: RefPositions {#364@364 #365@365} physReg:NA Preferences=[rax] RelatedInterval [0000017DD5169708] Interval 81: RefPositions {#368@372 #369@373} physReg:NA Preferences=[allIntButFP] RelatedInterval [0000017DD51692E8] Interval 82: RefPositions {#375@380 #387@389} physReg:NA Preferences=[rcx] Interval 83: RefPositions {#376@382 #378@383} physReg:NA Preferences=[rdx] Interval 84: RefPositions {#380@384 #389@389} physReg:NA Preferences=[rdx] Interval 85: (constant) RefPositions {#381@386 #383@387} physReg:NA Preferences=[r8] Interval 86: RefPositions {#385@388 #391@389} physReg:NA Preferences=[r8] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ #3 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #72 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #7 RefTypeUse LCL_VAR BB01 regmask=[allIntButFP] minReg=1> #5 RefTypeDef IND BB01 regmask=[allIntButFP] minReg=1> BB01 regmask=[allIntButFP] minReg=1 last> #142 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> #9 RefTypeDef IND BB01 regmask=[allIntButFP] minReg=1> BB01 regmask=[allIntButFP] minReg=1 last> #46 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> #14 RefTypeDef IND BB02 regmask=[rcx] minReg=1> #15 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #22 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #23 RefTypeDef PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> #19 RefTypeDef CNS_INT BB02 regmask=[rdx] minReg=1> #20 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> #24 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #25 RefTypeDef PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> #27 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #28 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> #33 RefTypeKill BB02 regmask=[rax] minReg=1 last> #41 RefTypeKill BB02 regmask=[rcx] minReg=1 last> #45 RefTypeKill BB02 regmask=[rdx] minReg=1 last> #61 RefTypeKill BB02 regmask=[r8] minReg=1 last> #62 RefTypeKill BB02 regmask=[r9] minReg=1 last> #63 RefTypeKill BB02 regmask=[r10] minReg=1 last> #64 RefTypeKill BB02 regmask=[r11] minReg=1 last> #58 RefTypeFixedReg BB02 regmask=[rax] minReg=1> #35 RefTypeDef CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allIntButFP] minReg=1 last> #37 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #183 RefTypeUse LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #39 RefTypeDef IND BB02 regmask=[allIntButFP] minReg=1> BB02 regmask=[allIntButFP] minReg=1 last> #42 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #43 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #49 RefTypeUse LCL_VAR BB02 regmask=[rcx] minReg=1 fixed> #53 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #54 RefTypeDef PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> #47 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #81 RefTypeUse LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> #55 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #56 RefTypeDef PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> #51 RefTypeDef IND BB02 regmask=[allIntButFP] minReg=1> BB02 regmask=[allIntButFP] minReg=1 last> #57 RefTypeDef IND BB02 regmask=[allIntButFP] minReg=1> #59 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #60 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[allIntButFP] minReg=1 last> #65 RefTypeKill BB02 regmask=[rax] minReg=1 last> #71 RefTypeKill BB02 regmask=[rcx] minReg=1 last> #76 RefTypeKill BB02 regmask=[rdx] minReg=1 last> #85 RefTypeKill BB02 regmask=[r8] minReg=1 last> #80 RefTypeKill BB02 regmask=[r9] minReg=1 last> #107 RefTypeKill BB02 regmask=[r10] minReg=1 last> #108 RefTypeKill BB02 regmask=[r11] minReg=1 last> #102 RefTypeFixedReg BB02 regmask=[rax] minReg=1> #67 RefTypeDef CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[allIntButFP] minReg=1 last> #69 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> #73 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> #89 RefTypeUse LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> #93 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> #94 RefTypeDef PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> #77 RefTypeDef LCL_VAR BB03 regmask=[rdx] minReg=1> #78 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> #95 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> #96 RefTypeDef PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> #82 RefTypeFixedReg BB03 regmask=[r9] minReg=1> #115 RefTypeUse LCL_VAR BB03 regmask=[r9] minReg=1 fixed> #97 RefTypeFixedReg BB03 regmask=[r9] minReg=1> #98 RefTypeDef PUTARG_REG BB03 regmask=[r9] minReg=1 fixed> #86 RefTypeDef CNS_INT BB03 regmask=[r8] minReg=1> #87 RefTypeFixedReg BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> #99 RefTypeFixedReg BB03 regmask=[r8] minReg=1> #100 RefTypeDef PUTARG_REG BB03 regmask=[r8] minReg=1 fixed> LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> #91 RefTypeDef IND BB03 regmask=[allIntButFP] minReg=1> BB03 regmask=[allIntButFP] minReg=1 last> #101 RefTypeDef IND BB03 regmask=[allIntButFP] minReg=1> #103 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> #104 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> #106 RefTypeFixedReg BB03 regmask=[r9] minReg=1> BB03 regmask=[r9] minReg=1 last fixed> #105 RefTypeFixedReg BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> BB03 regmask=[allIntButFP] minReg=1 last> #109 RefTypeKill BB03 regmask=[rax] minReg=1 last> #156 RefTypeKill BB03 regmask=[rcx] minReg=1 last> #161 RefTypeKill BB03 regmask=[rdx] minReg=1 last> #172 RefTypeKill BB03 regmask=[r8] minReg=1 last> #173 RefTypeKill BB03 regmask=[r9] minReg=1 last> #174 RefTypeKill BB03 regmask=[r10] minReg=1 last> #175 RefTypeKill BB03 regmask=[r11] minReg=1 last> #169 RefTypeFixedReg BB03 regmask=[rax] minReg=1> #111 RefTypeDef CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[allIntButFP] minReg=1 last> #113 RefTypeDef STORE_LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #129 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #117 RefTypeDef CAST BB03 regmask=[allIntButFP] minReg=1> #144 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #118 RefTypeDef CAST BB03 regmask=[allIntButFP] minReg=1> BB03 regmask=[allIntButFP] minReg=1 last regOptional> BB03 regmask=[allIntButFP] minReg=1 last> #122 RefTypeDef LCL_VAR BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #124 RefTypeDef IND BB05 regmask=[allIntButFP] minReg=1> BB05 regmask=[allIntButFP] minReg=1 last> #126 RefTypeDef STORE_LCL_VAR BB05 regmask=[allIntButFP] minReg=1> #128 RefTypeUse LCL_VAR BB05 regmask=[allIntButFP] minReg=1 regOptional> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 last regOptional> #141 RefTypeUse LCL_VAR BB06 regmask=[allIntButFP] minReg=1> #132 RefTypeDef LCL_VAR BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #134 RefTypeDef ADD BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #136 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #138 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #140 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #180 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #153 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #155 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #147 RefTypeDef LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #157 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #150 RefTypeDef LCL_VAR_ADDR BB07 regmask=[allIntButFP] minReg=1> BB07 regmask=[allIntButFP] minReg=1 last> #152 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #154 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> #158 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> #165 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> #166 RefTypeDef PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> #162 RefTypeDef LCL_VAR_ADDR BB07 regmask=[rdx] minReg=1> #163 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> #167 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> #168 RefTypeDef PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> #170 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> #171 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> #176 RefTypeKill BB07 regmask=[rax] minReg=1 last> #188 RefTypeKill BB07 regmask=[rcx] minReg=1 last> #193 RefTypeKill BB07 regmask=[rdx] minReg=1 last> #198 RefTypeKill BB07 regmask=[r8] minReg=1 last> #212 RefTypeKill BB07 regmask=[r9] minReg=1 last> #213 RefTypeKill BB07 regmask=[r10] minReg=1 last> #214 RefTypeKill BB07 regmask=[r11] minReg=1 last> #208 RefTypeFixedReg BB07 regmask=[rax] minReg=1> #178 RefTypeDef CALL BB07 regmask=[rax] minReg=1 fixed> BB07 regmask=[allIntButFP] minReg=1 last regOptional> LCL_VAR BB08 regmask=[allIntButFP] minReg=1 last> #216 RefTypeDef STORE_LCL_VAR BB08 regmask=[allIntButFP] minReg=1> #366 RefTypeUse LCL_VAR BB13 regmask=[allIntButFP] minReg=1 last> #185 RefTypeDef IND BB13 regmask=[allIntButFP] minReg=1> BB13 regmask=[allIntButFP] minReg=1 last> #189 RefTypeDef STORE_LCL_VAR BB13 regmask=[allIntButFP] minReg=1> #190 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> #370 RefTypeUse LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> #202 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> #203 RefTypeDef PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> #194 RefTypeDef LCL_VAR BB14 regmask=[rdx] minReg=1> #195 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> #204 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> #205 RefTypeDef PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> #199 RefTypeDef CNS_INT BB14 regmask=[r8] minReg=1> #200 RefTypeFixedReg BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> #206 RefTypeFixedReg BB14 regmask=[r8] minReg=1> #207 RefTypeDef PUTARG_REG BB14 regmask=[r8] minReg=1 fixed> #209 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> #210 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> #211 RefTypeFixedReg BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> #215 RefTypeKill BB14 regmask=[rax] minReg=1 last> #219 RefTypeKill BB14 regmask=[rcx] minReg=1 last> #220 RefTypeKill BB14 regmask=[rdx] minReg=1 last> #221 RefTypeKill BB14 regmask=[r8] minReg=1 last> #222 RefTypeKill BB14 regmask=[r9] minReg=1 last> #223 RefTypeKill BB14 regmask=[r10] minReg=1 last> #224 RefTypeKill BB14 regmask=[r11] minReg=1 last> #218 RefTypeFixedReg BB14 regmask=[rax] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last fixed> #226 RefTypeKill BB09 regmask=[rax] minReg=1 last> #227 RefTypeKill BB09 regmask=[rcx] minReg=1 last> #228 RefTypeKill BB09 regmask=[rdx] minReg=1 last> #229 RefTypeKill BB09 regmask=[r8] minReg=1 last> #230 RefTypeKill BB09 regmask=[r9] minReg=1 last> #231 RefTypeKill BB09 regmask=[r10] minReg=1 last> #232 RefTypeKill BB09 regmask=[r11] minReg=1 last> #241 RefTypeKill BB10 regmask=[rax] minReg=1 last> #235 RefTypeKill BB10 regmask=[rcx] minReg=1 last> #243 RefTypeKill BB10 regmask=[rdx] minReg=1 last> #244 RefTypeKill BB10 regmask=[r8] minReg=1 last> #245 RefTypeKill BB10 regmask=[r9] minReg=1 last> #246 RefTypeKill BB10 regmask=[r10] minReg=1 last> #247 RefTypeKill BB10 regmask=[r11] minReg=1 last> #236 RefTypeDef CNS_INT BB11 regmask=[rcx] minReg=1> #237 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #239 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> #240 RefTypeDef PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> #242 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #256 RefTypeKill BB11 regmask=[rax] minReg=1 last> #250 RefTypeKill BB11 regmask=[rcx] minReg=1 last> #258 RefTypeKill BB11 regmask=[rdx] minReg=1 last> #259 RefTypeKill BB11 regmask=[r8] minReg=1 last> #260 RefTypeKill BB11 regmask=[r9] minReg=1 last> #261 RefTypeKill BB11 regmask=[r10] minReg=1 last> #262 RefTypeKill BB11 regmask=[r11] minReg=1 last> #251 RefTypeDef CNS_INT BB12 regmask=[rcx] minReg=1> #252 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #254 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #255 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #257 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #263 RefTypeKill BB12 regmask=[rax] minReg=1 last> #268 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #276 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #277 RefTypeKill BB12 regmask=[r8] minReg=1 last> #278 RefTypeKill BB12 regmask=[r9] minReg=1 last> #279 RefTypeKill BB12 regmask=[r10] minReg=1 last> #280 RefTypeKill BB12 regmask=[r11] minReg=1 last> #274 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #265 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allIntButFP] minReg=1 last> #314 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #269 RefTypeDef CNS_INT BB12 regmask=[rcx] minReg=1> #270 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #272 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #273 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #275 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #281 RefTypeKill BB12 regmask=[rax] minReg=1 last> #285 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #290 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #301 RefTypeKill BB12 regmask=[r8] minReg=1 last> #302 RefTypeKill BB12 regmask=[r9] minReg=1 last> #303 RefTypeKill BB12 regmask=[r10] minReg=1 last> #304 RefTypeKill BB12 regmask=[r11] minReg=1 last> #298 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #283 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allIntButFP] minReg=1 last> #286 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #287 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> #294 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #295 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #291 RefTypeDef CNS_INT BB12 regmask=[rdx] minReg=1> #292 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #296 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> #297 RefTypeDef PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> #299 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #300 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #305 RefTypeKill BB12 regmask=[rax] minReg=1 last> #313 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #309 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #324 RefTypeKill BB12 regmask=[r8] minReg=1 last> #325 RefTypeKill BB12 regmask=[r9] minReg=1 last> #326 RefTypeKill BB12 regmask=[r10] minReg=1 last> #327 RefTypeKill BB12 regmask=[r11] minReg=1 last> #321 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #307 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allIntButFP] minReg=1 last> #310 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #311 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> #317 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> #318 RefTypeDef PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> #315 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #329 RefTypeUse LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> #319 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #320 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #323 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #322 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #334 RefTypeKill BB12 regmask=[rax] minReg=1 last> #328 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #336 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #337 RefTypeKill BB12 regmask=[r8] minReg=1 last> #338 RefTypeKill BB12 regmask=[r9] minReg=1 last> #339 RefTypeKill BB12 regmask=[r10] minReg=1 last> #340 RefTypeKill BB12 regmask=[r11] minReg=1 last> #330 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> #332 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #333 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #335 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #356 RefTypeKill BB12 regmask=[rax] minReg=1 last> #343 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #348 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #359 RefTypeKill BB12 regmask=[r8] minReg=1 last> #360 RefTypeKill BB12 regmask=[r9] minReg=1 last> #361 RefTypeKill BB12 regmask=[r10] minReg=1 last> #362 RefTypeKill BB12 regmask=[r11] minReg=1 last> #344 RefTypeDef IND BB15 regmask=[rcx] minReg=1> #345 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> #352 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> #353 RefTypeDef PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> #349 RefTypeDef CNS_INT BB15 regmask=[rdx] minReg=1> #350 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> #354 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> #355 RefTypeDef PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> #357 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> #358 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> #363 RefTypeKill BB15 regmask=[rax] minReg=1 last> #372 RefTypeKill BB15 regmask=[rcx] minReg=1 last> #377 RefTypeKill BB15 regmask=[rdx] minReg=1 last> #382 RefTypeKill BB15 regmask=[r8] minReg=1 last> #396 RefTypeKill BB15 regmask=[r9] minReg=1 last> #397 RefTypeKill BB15 regmask=[r10] minReg=1 last> #398 RefTypeKill BB15 regmask=[r11] minReg=1 last> #392 RefTypeFixedReg BB15 regmask=[rax] minReg=1> #365 RefTypeDef CALL BB15 regmask=[rax] minReg=1 fixed> BB15 regmask=[allIntButFP] minReg=1 last> #367 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> #369 RefTypeDef IND BB15 regmask=[allIntButFP] minReg=1> BB15 regmask=[allIntButFP] minReg=1 last> #373 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> #374 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> #386 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> #387 RefTypeDef PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> #378 RefTypeDef LCL_VAR BB16 regmask=[rdx] minReg=1> #379 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> #388 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> #389 RefTypeDef PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> #383 RefTypeDef CNS_INT BB16 regmask=[r8] minReg=1> #384 RefTypeFixedReg BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> #390 RefTypeFixedReg BB16 regmask=[r8] minReg=1> #391 RefTypeDef PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> #393 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> #394 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> #395 RefTypeFixedReg BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rcx] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[r8] minReg=1 last> BB16 regmask=[r9] minReg=1 last> BB16 regmask=[r10] minReg=1 last> BB16 regmask=[r11] minReg=1 last> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 #72 RefTypeParamDef BB00 regmask=[rcx] minReg=1 fixed> #89 RefTypeUse LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB03 regmask=[allIntButFP] minReg=1 last> --- V01 #3 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #7 RefTypeUse LCL_VAR BB01 regmask=[allIntButFP] minReg=1> LCL_VAR BB01 regmask=[allIntButFP] minReg=1 last> --- V02 --- V03 #113 RefTypeDef STORE_LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #129 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> #141 RefTypeUse LCL_VAR BB06 regmask=[allIntButFP] minReg=1> #180 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB08 regmask=[allIntButFP] minReg=1 last> --- V04 --- V05 #216 RefTypeDef STORE_LCL_VAR BB08 regmask=[allIntButFP] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last fixed> --- V06 --- V07 --- V08 #314 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> #329 RefTypeUse LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> --- V09 #42 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #49 RefTypeUse LCL_VAR BB02 regmask=[rcx] minReg=1 fixed> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> --- V10 --- V11 --- V12 --- V13 #136 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V14 --- V15 #189 RefTypeDef STORE_LCL_VAR BB13 regmask=[allIntButFP] minReg=1> #370 RefTypeUse LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> #373 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> --- V16 #142 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V17 #46 RefTypeDef STORE_LCL_VAR BB01 regmask=[allIntButFP] minReg=1> #81 RefTypeUse LCL_VAR BB02 regmask=[rdx] minReg=1 fixed> #115 RefTypeUse LCL_VAR BB03 regmask=[r9] minReg=1 fixed> #144 RefTypeUse LCL_VAR BB03 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V18 --- V19 --- V20 #140 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V21 --- V22 #138 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V23 #153 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V24 #155 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V25 --- V26 #286 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> --- V27 #310 RefTypeDef STORE_LCL_VAR BB12 regmask=[allIntButFP] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> --- V28 --- V29 #152 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> #154 RefTypeUse LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[allIntButFP] minReg=1 last> --- V30 #157 RefTypeDef STORE_LCL_VAR BB07 regmask=[allIntButFP] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> --- V31 --- V32 --- V33 #69 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> LCL_VAR BB02 regmask=[allIntButFP] minReg=1 last> --- V34 #37 RefTypeDef STORE_LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #183 RefTypeUse LCL_VAR BB02 regmask=[allIntButFP] minReg=1> #366 RefTypeUse LCL_VAR BB13 regmask=[allIntButFP] minReg=1 last> #367 RefTypeDef STORE_LCL_VAR BB15 regmask=[allIntButFP] minReg=1> LCL_VAR BB15 regmask=[allIntButFP] minReg=1 last> --- V35 #126 RefTypeDef STORE_LCL_VAR BB05 regmask=[allIntButFP] minReg=1> #128 RefTypeUse LCL_VAR BB05 regmask=[allIntButFP] minReg=1 regOptional> LCL_VAR BB06 regmask=[allIntButFP] minReg=1 last regOptional> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rbx |rbp |rsi |rdi | --------------------------------+----+----+----+----+----+----+ | |V0 a| | | | | --------------------------------+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi | --------------------------------+----+----+----+----+----+----+----+ 0.#0 V1 Parm Keep rdx | |V0 a|V1 a| | | | | 0.#1 V0 Parm Alloc rsi | | |V1 a| | |V0 a| | 1.#2 BB1 PredBB0 | | |V1 a| | |V0 a| | 7.#3 V1 Use Keep rdx | | |V1 a| | |V0 a| | 8.#4 I21 Def Alloc rdi | | |V1 a| | |V0 a|I21a| 9.#5 I21 Use * Keep rdi | | |V1 a| | |V0 a|I21a| 10.#6 V16 Def Alloc rdi | | |V1 a| | |V0 a|V16a| 15.#7 V1 Use * Keep rdx | | |V1 a| | |V0 a|V16a| 16.#8 I22 Def Alloc rbx | | | |I22a| |V0 a|V16a| 17.#9 I22 Use * Keep rbx | | | |I22a| |V0 a|V16a| 18.#10 V17 Def Alloc rbx | | | |V17a| |V0 a|V16a| --------------------------------+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi | --------------------------------+----+----+----+----+----+----+----+ 19.#11 BB2 PredBB1 | | | |V17a| |V0 a|V16a| 26.#12 I23 Def Alloc rcx | |I23a| |V17a| |V0 a|V16a| 27.#13 rcx Fixd Keep rcx | |I23a| |V17a| |V0 a|V16a| 27.#14 I23 Use * Keep rcx | |I23a| |V17a| |V0 a|V16a| 28.#15 rcx Fixd Keep rcx | | | |V17a| |V0 a|V16a| 28.#16 I24 Def Alloc rcx | |I24a| |V17a| |V0 a|V16a| 30.#17 C25 Def Alloc rdx | |I24a|C25a|V17a| |V0 a|V16a| 31.#18 rdx Fixd Keep rdx | |I24a|C25a|V17a| |V0 a|V16a| 31.#19 C25 Use * Keep rdx | |I24a|C25a|V17a| |V0 a|V16a| 32.#20 rdx Fixd Keep rdx | |I24a| |V17a| |V0 a|V16a| 32.#21 I26 Def Alloc rdx | |I24a|I26a|V17a| |V0 a|V16a| 33.#22 rcx Fixd Keep rcx | |I24a|I26a|V17a| |V0 a|V16a| 33.#23 I24 Use * Keep rcx | |I24a|I26a|V17a| |V0 a|V16a| 33.#24 rdx Fixd Keep rdx | |I24a|I26a|V17a| |V0 a|V16a| 33.#25 I26 Use * Keep rdx | |I24a|I26a|V17a| |V0 a|V16a| 34.#26 rax Kill Keep rax | | | |V17a| |V0 a|V16a| 34.#27 rcx Kill Keep rcx | | | |V17a| |V0 a|V16a| 34.#28 rdx Kill Keep rdx | | | |V17a| |V0 a|V16a| 34.#29 r8 Kill Keep r8 | | | |V17a| |V0 a|V16a| 34.#30 r9 Kill Keep r9 | | | |V17a| |V0 a|V16a| 34.#31 r10 Kill Keep r10 | | | |V17a| |V0 a|V16a| 34.#32 r11 Kill Keep r11 | | | |V17a| |V0 a|V16a| 34.#33 rax Fixd Keep rax | | | |V17a| |V0 a|V16a| 34.#34 I27 Def Alloc rax |I27a| | |V17a| |V0 a|V16a| 35.#35 I27 Use * Keep rax |I27a| | |V17a| |V0 a|V16a| --------------------------------+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | --------------------------------+----+----+----+----+----+----+----+----+ 36.#36 V34 Def Alloc r14 | | | |V17a| |V0 a|V16a|V34a| 41.#37 V34 Use Keep r14 | | | |V17a| |V0 a|V16a|V34a| 42.#38 I28 Def Alloc rcx | |I28a| |V17a| |V0 a|V16a|V34a| 43.#39 I28 Use * Keep rcx | |I28a| |V17a| |V0 a|V16a|V34a| 44.#40 V9 Def Alloc rcx | |V9 a| |V17a| |V0 a|V16a|V34a| 47.#41 rcx Fixd Keep rcx | |V9 a| |V17a| |V0 a|V16a|V34a| 47.#42 V9 Use Keep rcx | |V9 a| |V17a| |V0 a|V16a|V34a| 48.#43 rcx Fixd Keep rcx | |V9 a| |V17a| |V0 a|V16a|V34a| 48.#44 I29 Def PtArg rcx | |V9 a| |V17a| |V0 a|V16a|V34a| 51.#45 rdx Fixd Keep rdx | |V9 a| |V17a| |V0 a|V16a|V34a| 51.#46 V17 Use Copy rdx | |V9 a|V17a|V17a| |V0 a|V16a|V34a| 52.#47 rdx Fixd Keep rdx | |V9 a|V17a|V17a| |V0 a|V16a|V34a| 52.#48 I30 Def Alloc rdx | |V9 a|I30a|V17a| |V0 a|V16a|V34a| 57.#49 V9 Use * Keep rcx | |V9 a|I30a|V17a| |V0 a|V16a|V34a| 58.#50 I31 Def Alloc rax |I31a|Busy|I30a|V17a| |V0 a|V16a|V34a| 61.#51 I31 Use * Keep rax |I31a|Busy|I30a|V17a| |V0 a|V16a|V34a| 62.#52 I32 Def Alloc rax |I32a|Busy|I30a|V17a| |V0 a|V16a|V34a| 67.#53 rcx Fixd Keep rcx |I32a|Busy|I30a|V17a| |V0 a|V16a|V34a| 67.#54 I29 Use * PtArg rcx |I32a|Busy|I30a|V17a| |V0 a|V16a|V34a| 67.#55 rdx Fixd Keep rdx |I32a|Busy|I30a|V17a| |V0 a|V16a|V34a| 67.#56 I30 Use * Keep rdx |I32a|Busy|I30a|V17a| |V0 a|V16a|V34a| 67.#57 I32 Use * Keep rax |I32a|Busy|I30a|V17a| |V0 a|V16a|V34a| 68.#58 rax Kill Keep rax | |Busy| |V17a| |V0 a|V16a|V34a| 68.#59 rcx Kill Keep rcx | | | |V17a| |V0 a|V16a|V34a| 68.#60 rdx Kill Keep rdx | | | |V17a| |V0 a|V16a|V34a| 68.#61 r8 Kill Keep r8 | | | |V17a| |V0 a|V16a|V34a| 68.#62 r9 Kill Keep r9 | | | |V17a| |V0 a|V16a|V34a| 68.#63 r10 Kill Keep r10 | | | |V17a| |V0 a|V16a|V34a| 68.#64 r11 Kill Keep r11 | | | |V17a| |V0 a|V16a|V34a| 68.#65 rax Fixd Keep rax | | | |V17a| |V0 a|V16a|V34a| 68.#66 I33 Def Alloc rax |I33a| | |V17a| |V0 a|V16a|V34a| 69.#67 I33 Use * Keep rax |I33a| | |V17a| |V0 a|V16a|V34a| 70.#68 V33 Def Alloc rax |V33a| | |V17a| |V0 a|V16a|V34a| 73.#69 V33 Use * Keep rax |V33a| | |V17a| |V0 a|V16a|V34a| --------------------------------+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r14 | --------------------------------+----+----+----+----+----+----+----+----+ 75.#70 BB3 PredBB2 | | | |V17a| |V0 a|V16a|V34a| 79.#71 rcx Fixd Keep rcx | | | |V17a| |V0 a|V16a|V34a| 79.#72 V0 Use Copy rcx | |V0 a| |V17a| |V0 a|V16a|V34a| 80.#73 rcx Fixd Keep rcx | |V0 a| |V17a| |V0 a|V16a|V34a| 80.#74 I34 Def Alloc rcx | |I34a| |V17a| |V0 a|V16a|V34a| 82.#75 I35 Def Alloc rdx | |I34a|I35a|V17a| |V0 a|V16a|V34a| 83.#76 rdx Fixd Keep rdx | |I34a|I35a|V17a| |V0 a|V16a|V34a| 83.#77 I35 Use * Keep rdx | |I34a|I35a|V17a| |V0 a|V16a|V34a| 84.#78 rdx Fixd Keep rdx | |I34a| |V17a| |V0 a|V16a|V34a| 84.#79 I36 Def Alloc rdx | |I34a|I36a|V17a| |V0 a|V16a|V34a| 87.#80 r9 Fixd Keep r9 | |I34a|I36a|V17a| |V0 a|V16a|V34a| --------------------------------+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+ 87.#81 V17 Use Copy r9 | |I34a|I36a|V17a| |V0 a|V16a|V17a|V34a| 88.#82 r9 Fixd Keep r9 | |I34a|I36a|V17a| |V0 a|V16a|V17a|V34a| 88.#83 I37 Def Alloc r9 | |I34a|I36a|V17a| |V0 a|V16a|I37a|V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 90.#84 C38 Def Alloc r8 | |I34a|I36a|V17a| |V0 a|V16a|C38a|I37a|V34a| 91.#85 r8 Fixd Keep r8 | |I34a|I36a|V17a| |V0 a|V16a|C38a|I37a|V34a| 91.#86 C38 Use * Keep r8 | |I34a|I36a|V17a| |V0 a|V16a|C38a|I37a|V34a| 92.#87 r8 Fixd Keep r8 | |I34a|I36a|V17a| |V0 a|V16a| |I37a|V34a| 92.#88 I39 Def Alloc r8 | |I34a|I36a|V17a| |V0 a|V16a|I39a|I37a|V34a| 97.#89 V0 Use * Keep rsi | |I34a|I36a|V17a| |V0 a|V16a|I39a|I37a|V34a| 98.#90 I40 Def Alloc rax |I40a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 101.#91 I40 Use * Keep rax |I40a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 102.#92 I41 Def Alloc rax |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#93 rcx Fixd Keep rcx |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#94 I34 Use * Keep rcx |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#95 rdx Fixd Keep rdx |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#96 I36 Use * Keep rdx |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#97 r9 Fixd Keep r9 |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#98 I37 Use * Keep r9 |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#99 r8 Fixd Keep r8 |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#100 I39 Use * Keep r8 |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#101 I41 Use * Keep rax |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 108.#102 rax Kill Keep rax | | | |V17a| | |V16a| | |V34a| 108.#103 rcx Kill Keep rcx | | | |V17a| | |V16a| | |V34a| 108.#104 rdx Kill Keep rdx | | | |V17a| | |V16a| | |V34a| 108.#105 r8 Kill Keep r8 | | | |V17a| | |V16a| | |V34a| 108.#106 r9 Kill Keep r9 | | | |V17a| | |V16a| | |V34a| 108.#107 r10 Kill Keep r10 | | | |V17a| | |V16a| | |V34a| 108.#108 r11 Kill Keep r11 | | | |V17a| | |V16a| | |V34a| 108.#109 rax Fixd Keep rax | | | |V17a| | |V16a| | |V34a| 108.#110 I42 Def Alloc rax |I42a| | |V17a| | |V16a| | |V34a| 109.#111 I42 Use * Keep rax |I42a| | |V17a| | |V16a| | |V34a| 110.#112 V3 Def Alloc rsi | | | |V17a| |V3 a|V16a| | |V34a| 113.#113 V3 Use Keep rsi | | | |V17a| |V3 a|V16a| | |V34a| 114.#114 I43 Def Alloc rcx | |I43a| |V17a| |V3 a|V16a| | |V34a| 117.#115 V17 Use Keep rbx | |I43a| |V17a| |V3 a|V16a| | |V34a| 118.#116 I44 Def Alloc rdx | |I43a|I44a|V17a| |V3 a|V16a| | |V34a| 119.#117 I43 Use * Keep rcx | |I43a|I44a|V17a| |V3 a|V16a| | |V34a| 119.#118 I44 Use * Keep rdx | |I43a|I44a|V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 123.#119 BB4 PredBB3 | | | |V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 135.#120 BB5 PredBB4 | | | |V17a| |V3 a|V16a| | |V34a| 138.#121 I45 Def Alloc rcx | |I45a| |V17a| |V3 a|V16a| | |V34a| 141.#122 I45 Use * Keep rcx | |I45a| |V17a| |V3 a|V16a| | |V34a| 142.#123 I46 Def Alloc rcx | |I46a| |V17a| |V3 a|V16a| | |V34a| 143.#124 I46 Use * Keep rcx | |I46a| |V17a| |V3 a|V16a| | |V34a| 144.#125 V35 Def Alloc rcx | |V35a| |V17a| |V3 a|V16a| | |V34a| 149.#126 V35 Use Keep rcx | |V35a| |V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 153.#127 BB6 PredBB5 | |V35a| |V17a| |V3 a|V16a| | |V34a| 159.#128 V35 Use * Keep rcx | |V35a| |V17a| |V3 a|V16a| | |V34a| 159.#129 V3 Use Keep rsi | |V35a| |V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 163.#130 BB7 PredBB6 | | | |V17a| |V3 a|V16a| | |V34a| 166.#131 I47 Def Alloc rcx | |I47a| |V17a| |V3 a|V16a| | |V34a| 169.#132 I47 Use * Keep rcx | |I47a| |V17a| |V3 a|V16a| | |V34a| 170.#133 I48 Def Alloc rcx | |I48a| |V17a| |V3 a|V16a| | |V34a| 171.#134 I48 Use * Keep rcx | |I48a| |V17a| |V3 a|V16a| | |V34a| 172.#135 V13 Def Alloc rcx | |V13a| |V17a| |V3 a|V16a| | |V34a| 175.#136 V13 Use * Keep rcx | |V13a| |V17a| |V3 a|V16a| | |V34a| 176.#137 V22 Def Alloc rcx | |V22a| |V17a| |V3 a|V16a| | |V34a| 179.#138 V22 Use * Keep rcx | |V22a| |V17a| |V3 a|V16a| | |V34a| 180.#139 V20 Def Alloc rcx | |V20a| |V17a| |V3 a|V16a| | |V34a| 185.#140 V20 Use * Keep rcx | |V20a| |V17a| |V3 a|V16a| | |V34a| 189.#141 V3 Use Keep rsi | | | |V17a| |V3 a|V16a| | |V34a| 195.#142 V16 Use * Keep rdi | | | |V17a| |V3 a|V16a| | |V34a| 196.#143 V23 Def Alloc rdi | | | |V17a| |V3 a|V23a| | |V34a| 199.#144 V17 Use * Keep rbx | | | |V17a| |V3 a|V23a| | |V34a| 200.#145 V24 Def Alloc rbx | | | |V24a| |V3 a|V23a| | |V34a| 204.#146 I49 Def Alloc rcx | |I49a| |V24a| |V3 a|V23a| | |V34a| 205.#147 I49 Use * Keep rcx | |I49a| |V24a| |V3 a|V23a| | |V34a| 206.#148 V30 Def Alloc rcx | |V30a| |V24a| |V3 a|V23a| | |V34a| 208.#149 I50 Def Alloc rdx | |V30a|I50a|V24a| |V3 a|V23a| | |V34a| 209.#150 I50 Use * Keep rdx | |V30a|I50a|V24a| |V3 a|V23a| | |V34a| 210.#151 V29 Def Alloc rdx | |V30a|V29a|V24a| |V3 a|V23a| | |V34a| 217.#152 V29 Use Keep rdx | |V30a|V29a|V24a| |V3 a|V23a| | |V34a| 217.#153 V23 Use * Keep rdi | |V30a|V29a|V24a| |V3 a|V23a| | |V34a| 225.#154 V29 Use * Keep rdx | |V30a|V29a|V24a| |V3 a| | | |V34a| 225.#155 V24 Use * Keep rbx | |V30a|V29a|V24a| |V3 a| | | |V34a| 229.#156 rcx Fixd Keep rcx | |V30a| | | |V3 a| | | |V34a| 229.#157 V30 Use * Keep rcx | |V30a| | | |V3 a| | | |V34a| 230.#158 rcx Fixd Keep rcx | | | | | |V3 a| | | |V34a| 230.#159 I51 Def Alloc rcx | |I51a| | | |V3 a| | | |V34a| 232.#160 I52 Def Alloc rdx | |I51a|I52a| | |V3 a| | | |V34a| 233.#161 rdx Fixd Keep rdx | |I51a|I52a| | |V3 a| | | |V34a| 233.#162 I52 Use * Keep rdx | |I51a|I52a| | |V3 a| | | |V34a| 234.#163 rdx Fixd Keep rdx | |I51a| | | |V3 a| | | |V34a| 234.#164 I53 Def Alloc rdx | |I51a|I53a| | |V3 a| | | |V34a| 235.#165 rcx Fixd Keep rcx | |I51a|I53a| | |V3 a| | | |V34a| 235.#166 I51 Use * Keep rcx | |I51a|I53a| | |V3 a| | | |V34a| 235.#167 rdx Fixd Keep rdx | |I51a|I53a| | |V3 a| | | |V34a| 235.#168 I53 Use * Keep rdx | |I51a|I53a| | |V3 a| | | |V34a| 236.#169 rax Kill Keep rax | | | | | |V3 a| | | |V34a| 236.#170 rcx Kill Keep rcx | | | | | |V3 a| | | |V34a| 236.#171 rdx Kill Keep rdx | | | | | |V3 a| | | |V34a| 236.#172 r8 Kill Keep r8 | | | | | |V3 a| | | |V34a| 236.#173 r9 Kill Keep r9 | | | | | |V3 a| | | |V34a| 236.#174 r10 Kill Keep r10 | | | | | |V3 a| | | |V34a| 236.#175 r11 Kill Keep r11 | | | | | |V3 a| | | |V34a| 236.#176 rax Fixd Keep rax | | | | | |V3 a| | | |V34a| 236.#177 I54 Def Alloc rax |I54a| | | | |V3 a| | | |V34a| 239.#178 I54 Use * Keep rax |I54a| | | | |V3 a| | | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 243.#179 BB8 PredBB7 | | | | | |V3 a| | | |V34a| 249.#180 V3 Use * Keep rsi | | | | | |V3 a| | | |V34a| 250.#181 V5 Def Alloc rsi | | | | | |V5 a| | | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 251.#182 BB13 PredBB8 | | | | | |V5 a| | | |V34a| 257.#183 V34 Use * Keep r14 | | | | | |V5 a| | | |V34i| 258.#184 I55 Def Alloc rcx | |I55a| | | |V5 a| | | |V34i| 259.#185 I55 Use * Keep rcx | |I55a| | | |V5 a| | | |V34i| 260.#186 V15 Def Alloc rcx | |V15a| | | |V5 a| | | |V34i| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 261.#187 BB14 PredBB13 | |V15a| | | |V5 a| | | |V34i| 265.#188 rcx Fixd Keep rcx | |V15a| | | |V5 a| | | |V34i| 265.#189 V15 Use * Keep rcx | |V15i| | | |V5 a| | | |V34i| 266.#190 rcx Fixd Keep rcx | |V15i| | | |V5 a| | | |V34i| 266.#191 I56 Def Alloc rcx | |I56a| | | |V5 a| | | |V34i| 268.#192 I57 Def Alloc rdx | |I56a|I57a| | |V5 a| | | |V34i| 269.#193 rdx Fixd Keep rdx | |I56a|I57a| | |V5 a| | | |V34i| 269.#194 I57 Use * Keep rdx | |I56a|I57a| | |V5 a| | | |V34i| 270.#195 rdx Fixd Keep rdx | |I56a| | | |V5 a| | | |V34i| 270.#196 I58 Def Alloc rdx | |I56a|I58a| | |V5 a| | | |V34i| 272.#197 C59 Def Alloc r8 | |I56a|I58a| | |V5 a| |C59a| |V34i| 273.#198 r8 Fixd Keep r8 | |I56a|I58a| | |V5 a| |C59a| |V34i| 273.#199 C59 Use * Keep r8 | |I56a|I58a| | |V5 a| |C59a| |V34i| 274.#200 r8 Fixd Keep r8 | |I56a|I58a| | |V5 a| | | |V34i| 274.#201 I60 Def Alloc r8 | |I56a|I58a| | |V5 a| |I60a| |V34i| 275.#202 rcx Fixd Keep rcx | |I56a|I58a| | |V5 a| |I60a| |V34i| 275.#203 I56 Use * Keep rcx | |I56a|I58a| | |V5 a| |I60a| |V34i| 275.#204 rdx Fixd Keep rdx | |I56a|I58a| | |V5 a| |I60a| |V34i| 275.#205 I58 Use * Keep rdx | |I56a|I58a| | |V5 a| |I60a| |V34i| 275.#206 r8 Fixd Keep r8 | |I56a|I58a| | |V5 a| |I60a| |V34i| 275.#207 I60 Use * Keep r8 | |I56a|I58a| | |V5 a| |I60a| |V34i| Restr rcx | |V15i|I58a| | |V5 a| |I60a| |V34i| 276.#208 rax Kill Keep rax | |V15i| | | |V5 a| | | |V34i| 276.#209 rcx Kill Keep rcx | | | | | |V5 a| | | |V34i| 276.#210 rdx Kill Keep rdx | | | | | |V5 a| | | |V34i| 276.#211 r8 Kill Keep r8 | | | | | |V5 a| | | |V34i| 276.#212 r9 Kill Keep r9 | | | | | |V5 a| | | |V34i| 276.#213 r10 Kill Keep r10 | | | | | |V5 a| | | |V34i| 276.#214 r11 Kill Keep r11 | | | | | |V5 a| | | |V34i| 281.#215 rax Fixd Keep rax | | | | | |V5 a| | | |V34i| 281.#216 V5 Use * Copy rax |V5 a| | | | |V5 a| | | |V34i| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 283.#217 BB9 PredBB7 | | | | | | | | | |V34i| 288.#218 rax Kill Keep rax | | | | | | | | | |V34i| 288.#219 rcx Kill Keep rcx | | | | | | | | | |V34i| 288.#220 rdx Kill Keep rdx | | | | | | | | | |V34i| 288.#221 r8 Kill Keep r8 | | | | | | | | | |V34i| 288.#222 r9 Kill Keep r9 | | | | | | | | | |V34i| 288.#223 r10 Kill Keep r10 | | | | | | | | | |V34i| 288.#224 r11 Kill Keep r11 | | | | | | | | | |V34i| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 289.#225 BB10 PredBB5 | | | | | | | | | |V34i| 292.#226 rax Kill Keep rax | | | | | | | | | |V34i| 292.#227 rcx Kill Keep rcx | | | | | | | | | |V34i| 292.#228 rdx Kill Keep rdx | | | | | | | | | |V34i| 292.#229 r8 Kill Keep r8 | | | | | | | | | |V34i| 292.#230 r9 Kill Keep r9 | | | | | | | | | |V34i| 292.#231 r10 Kill Keep r10 | | | | | | | | | |V34i| 292.#232 r11 Kill Keep r11 | | | | | | | | | |V34i| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 293.#233 BB11 PredBB4 | | | | | | | | | |V34i| 296.#234 C61 Def Alloc rcx | |C61a| | | | | | | |V34i| 297.#235 rcx Fixd Keep rcx | |C61a| | | | | | | |V34i| 297.#236 C61 Use * Keep rcx | |C61a| | | | | | | |V34i| 298.#237 rcx Fixd Keep rcx | | | | | | | | | |V34i| 298.#238 I62 Def Alloc rcx | |I62a| | | | | | | |V34i| 299.#239 rcx Fixd Keep rcx | |I62a| | | | | | | |V34i| 299.#240 I62 Use * Keep rcx | |I62a| | | | | | | |V34i| 300.#241 rax Kill Keep rax | | | | | | | | | |V34i| 300.#242 rcx Kill Keep rcx | | | | | | | | | |V34i| 300.#243 rdx Kill Keep rdx | | | | | | | | | |V34i| 300.#244 r8 Kill Keep r8 | | | | | | | | | |V34i| 300.#245 r9 Kill Keep r9 | | | | | | | | | |V34i| 300.#246 r10 Kill Keep r10 | | | | | | | | | |V34i| 300.#247 r11 Kill Keep r11 | | | | | | | | | |V34i| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 301.#248 BB12 PredBB3 | | | | | | | | | |V34i| 304.#249 C63 Def Alloc rcx | |C63a| | | | | | | |V34i| 305.#250 rcx Fixd Keep rcx | |C63a| | | | | | | |V34i| 305.#251 C63 Use * Keep rcx | |C63a| | | | | | | |V34i| 306.#252 rcx Fixd Keep rcx | | | | | | | | | |V34i| 306.#253 I64 Def Alloc rcx | |I64a| | | | | | | |V34i| 307.#254 rcx Fixd Keep rcx | |I64a| | | | | | | |V34i| 307.#255 I64 Use * Keep rcx | |I64a| | | | | | | |V34i| 308.#256 rax Kill Keep rax | | | | | | | | | |V34i| 308.#257 rcx Kill Keep rcx | | | | | | | | | |V34i| 308.#258 rdx Kill Keep rdx | | | | | | | | | |V34i| 308.#259 r8 Kill Keep r8 | | | | | | | | | |V34i| 308.#260 r9 Kill Keep r9 | | | | | | | | | |V34i| 308.#261 r10 Kill Keep r10 | | | | | | | | | |V34i| 308.#262 r11 Kill Keep r11 | | | | | | | | | |V34i| 308.#263 rax Fixd Keep rax | | | | | | | | | |V34i| 308.#264 I65 Def Alloc rax |I65a| | | | | | | | |V34i| 309.#265 I65 Use * Keep rax |I65a| | | | | | | | |V34i| 310.#266 V8 Def Alloc r14 | | | | | | | | | |V8 a| 312.#267 C66 Def Alloc rcx | |C66a| | | | | | | |V8 a| 313.#268 rcx Fixd Keep rcx | |C66a| | | | | | | |V8 a| 313.#269 C66 Use * Keep rcx | |C66a| | | | | | | |V8 a| 314.#270 rcx Fixd Keep rcx | | | | | | | | | |V8 a| 314.#271 I67 Def Alloc rcx | |I67a| | | | | | | |V8 a| 315.#272 rcx Fixd Keep rcx | |I67a| | | | | | | |V8 a| 315.#273 I67 Use * Keep rcx | |I67a| | | | | | | |V8 a| 316.#274 rax Kill Keep rax | | | | | | | | | |V8 a| 316.#275 rcx Kill Keep rcx | | | | | | | | | |V8 a| 316.#276 rdx Kill Keep rdx | | | | | | | | | |V8 a| 316.#277 r8 Kill Keep r8 | | | | | | | | | |V8 a| 316.#278 r9 Kill Keep r9 | | | | | | | | | |V8 a| 316.#279 r10 Kill Keep r10 | | | | | | | | | |V8 a| 316.#280 r11 Kill Keep r11 | | | | | | | | | |V8 a| 316.#281 rax Fixd Keep rax | | | | | | | | | |V8 a| 316.#282 I68 Def Alloc rax |I68a| | | | | | | | |V8 a| 317.#283 I68 Use * Keep rax |I68a| | | | | | | | |V8 a| 318.#284 V26 Def Alloc rcx | |V26a| | | | | | | |V8 a| 321.#285 rcx Fixd Keep rcx | |V26a| | | | | | | |V8 a| 321.#286 V26 Use * Keep rcx | |V26a| | | | | | | |V8 a| 322.#287 rcx Fixd Keep rcx | | | | | | | | | |V8 a| 322.#288 I69 Def Alloc rcx | |I69a| | | | | | | |V8 a| 324.#289 C70 Def Alloc rdx | |I69a|C70a| | | | | | |V8 a| 325.#290 rdx Fixd Keep rdx | |I69a|C70a| | | | | | |V8 a| 325.#291 C70 Use * Keep rdx | |I69a|C70a| | | | | | |V8 a| 326.#292 rdx Fixd Keep rdx | |I69a| | | | | | | |V8 a| 326.#293 I71 Def Alloc rdx | |I69a|I71a| | | | | | |V8 a| 327.#294 rcx Fixd Keep rcx | |I69a|I71a| | | | | | |V8 a| 327.#295 I69 Use * Keep rcx | |I69a|I71a| | | | | | |V8 a| 327.#296 rdx Fixd Keep rdx | |I69a|I71a| | | | | | |V8 a| 327.#297 I71 Use * Keep rdx | |I69a|I71a| | | | | | |V8 a| 328.#298 rax Kill Keep rax | | | | | | | | | |V8 a| 328.#299 rcx Kill Keep rcx | | | | | | | | | |V8 a| 328.#300 rdx Kill Keep rdx | | | | | | | | | |V8 a| 328.#301 r8 Kill Keep r8 | | | | | | | | | |V8 a| 328.#302 r9 Kill Keep r9 | | | | | | | | | |V8 a| 328.#303 r10 Kill Keep r10 | | | | | | | | | |V8 a| 328.#304 r11 Kill Keep r11 | | | | | | | | | |V8 a| 328.#305 rax Fixd Keep rax | | | | | | | | | |V8 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 328.#306 I72 Def Alloc rax |I72a| | | | | | | | |V8 a| 329.#307 I72 Use * Keep rax |I72a| | | | | | | | |V8 a| 330.#308 V27 Def Alloc rdx | | |V27a| | | | | | |V8 a| 333.#309 rdx Fixd Keep rdx | | |V27a| | | | | | |V8 a| 333.#310 V27 Use * Keep rdx | | |V27a| | | | | | |V8 a| 334.#311 rdx Fixd Keep rdx | | | | | | | | | |V8 a| 334.#312 I73 Def Alloc rdx | | |I73a| | | | | | |V8 a| 337.#313 rcx Fixd Keep rcx | | |I73a| | | | | | |V8 a| 337.#314 V8 Use Copy rcx | |V8 a|I73a| | | | | | |V8 a| 338.#315 rcx Fixd Keep rcx | |V8 a|I73a| | | | | | |V8 a| 338.#316 I74 Def Alloc rcx | |I74a|I73a| | | | | | |V8 a| 339.#317 rdx Fixd Keep rdx | |I74a|I73a| | | | | | |V8 a| 339.#318 I73 Use * Keep rdx | |I74a|I73a| | | | | | |V8 a| 339.#319 rcx Fixd Keep rcx | |I74a|I73a| | | | | | |V8 a| 339.#320 I74 Use * Keep rcx | |I74a|I73a| | | | | | |V8 a| 340.#321 rax Kill Keep rax | | | | | | | | | |V8 a| 340.#322 rcx Kill Keep rcx | | | | | | | | | |V8 a| 340.#323 rdx Kill Keep rdx | | | | | | | | | |V8 a| 340.#324 r8 Kill Keep r8 | | | | | | | | | |V8 a| 340.#325 r9 Kill Keep r9 | | | | | | | | | |V8 a| 340.#326 r10 Kill Keep r10 | | | | | | | | | |V8 a| 340.#327 r11 Kill Keep r11 | | | | | | | | | |V8 a| 345.#328 rcx Fixd Keep rcx | | | | | | | | | |V8 a| 345.#329 V8 Use * Copy rcx | |V8 a| | | | | | | |V8 a| Restr r14 | | | | | | | | | |V34i| 346.#330 rcx Fixd Keep rcx | | | | | | | | | |V34i| 346.#331 I75 Def Alloc rcx | |I75a| | | | | | | |V34i| 347.#332 rcx Fixd Keep rcx | |I75a| | | | | | | |V34i| 347.#333 I75 Use * Keep rcx | |I75a| | | | | | | |V34i| 348.#334 rax Kill Keep rax | | | | | | | | | |V34i| 348.#335 rcx Kill Keep rcx | | | | | | | | | |V34i| 348.#336 rdx Kill Keep rdx | | | | | | | | | |V34i| 348.#337 r8 Kill Keep r8 | | | | | | | | | |V34i| 348.#338 r9 Kill Keep r9 | | | | | | | | | |V34i| 348.#339 r10 Kill Keep r10 | | | | | | | | | |V34i| 348.#340 r11 Kill Keep r11 | | | | | | | | | |V34i| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 349.#341 BB15 PredBB12 | | | | | | | | | |V34i| 356.#342 I76 Def Alloc rcx | |I76a| | | | | | | |V34i| 357.#343 rcx Fixd Keep rcx | |I76a| | | | | | | |V34i| 357.#344 I76 Use * Keep rcx | |I76a| | | | | | | |V34i| 358.#345 rcx Fixd Keep rcx | | | | | | | | | |V34i| 358.#346 I77 Def Alloc rcx | |I77a| | | | | | | |V34i| 360.#347 C78 Def Alloc rdx | |I77a|C78a| | | | | | |V34i| 361.#348 rdx Fixd Keep rdx | |I77a|C78a| | | | | | |V34i| 361.#349 C78 Use * Keep rdx | |I77a|C78a| | | | | | |V34i| 362.#350 rdx Fixd Keep rdx | |I77a| | | | | | | |V34i| 362.#351 I79 Def Alloc rdx | |I77a|I79a| | | | | | |V34i| 363.#352 rcx Fixd Keep rcx | |I77a|I79a| | | | | | |V34i| 363.#353 I77 Use * Keep rcx | |I77a|I79a| | | | | | |V34i| 363.#354 rdx Fixd Keep rdx | |I77a|I79a| | | | | | |V34i| 363.#355 I79 Use * Keep rdx | |I77a|I79a| | | | | | |V34i| 364.#356 rax Kill Keep rax | | | | | | | | | |V34i| 364.#357 rcx Kill Keep rcx | | | | | | | | | |V34i| 364.#358 rdx Kill Keep rdx | | | | | | | | | |V34i| 364.#359 r8 Kill Keep r8 | | | | | | | | | |V34i| 364.#360 r9 Kill Keep r9 | | | | | | | | | |V34i| 364.#361 r10 Kill Keep r10 | | | | | | | | | |V34i| 364.#362 r11 Kill Keep r11 | | | | | | | | | |V34i| 364.#363 rax Fixd Keep rax | | | | | | | | | |V34i| 364.#364 I80 Def Alloc rax |I80a| | | | | | | | |V34i| 365.#365 I80 Use * Keep rax |I80a| | | | | | | | |V34i| 366.#366 V34 Def Alloc r14 | | | | | | | | | |V34a| 371.#367 V34 Use * Keep r14 | | | | | | | | | |V34a| 372.#368 I81 Def Alloc rcx | |I81a| | | | | | | | | 373.#369 I81 Use * Keep rcx | |I81a| | | | | | | | | 374.#370 V15 Def Alloc rcx | |V15a| | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 375.#371 BB16 PredBB15 | |V15a| | | | | | | | | 379.#372 rcx Fixd Keep rcx | |V15a| | | | | | | | | 379.#373 V15 Use * Keep rcx | |V15a| | | | | | | | | 380.#374 rcx Fixd Keep rcx | | | | | | | | | | | 380.#375 I82 Def Alloc rcx | |I82a| | | | | | | | | 382.#376 I83 Def Alloc rdx | |I82a|I83a| | | | | | | | 383.#377 rdx Fixd Keep rdx | |I82a|I83a| | | | | | | | 383.#378 I83 Use * Keep rdx | |I82a|I83a| | | | | | | | 384.#379 rdx Fixd Keep rdx | |I82a| | | | | | | | | 384.#380 I84 Def Alloc rdx | |I82a|I84a| | | | | | | | 386.#381 C85 Def Alloc r8 | |I82a|I84a| | | | |C85a| | | 387.#382 r8 Fixd Keep r8 | |I82a|I84a| | | | |C85a| | | 387.#383 C85 Use * Keep r8 | |I82a|I84a| | | | |C85a| | | 388.#384 r8 Fixd Keep r8 | |I82a|I84a| | | | | | | | 388.#385 I86 Def Alloc r8 | |I82a|I84a| | | | |I86a| | | 389.#386 rcx Fixd Keep rcx | |I82a|I84a| | | | |I86a| | | 389.#387 I82 Use * Keep rcx | |I82a|I84a| | | | |I86a| | | 389.#388 rdx Fixd Keep rdx | |I82a|I84a| | | | |I86a| | | 389.#389 I84 Use * Keep rdx | |I82a|I84a| | | | |I86a| | | 389.#390 r8 Fixd Keep r8 | |I82a|I84a| | | | |I86a| | | 389.#391 I86 Use * Keep r8 | |I82a|I84a| | | | |I86a| | | 390.#392 rax Kill Keep rax | | | | | | | | | | | 390.#393 rcx Kill Keep rcx | | | | | | | | | | | 390.#394 rdx Kill Keep rdx | | | | | | | | | | | 390.#395 r8 Kill Keep r8 | | | | | | | | | | | 390.#396 r9 Kill Keep r9 | | | | | | | | | | | 390.#397 r10 Kill Keep r10 | | | | | | | | | | | 390.#398 r11 Kill Keep r11 | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ #3 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #72 RefTypeParamDef BB00 regmask=[rsi] minReg=1 fixed> #7 RefTypeUse LCL_VAR BB01 regmask=[rdx] minReg=1> #5 RefTypeDef IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> #142 RefTypeDef STORE_LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rdx] minReg=1 last> #9 RefTypeDef IND BB01 regmask=[rbx] minReg=1> BB01 regmask=[rbx] minReg=1 last> #46 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> #14 RefTypeDef IND BB02 regmask=[rcx] minReg=1> #15 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #22 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #23 RefTypeDef PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> #19 RefTypeDef CNS_INT BB02 regmask=[rdx] minReg=1> #20 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> #24 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #25 RefTypeDef PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> #27 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #28 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> #33 RefTypeKill BB02 regmask=[rax] minReg=1 last> #41 RefTypeKill BB02 regmask=[rcx] minReg=1 last> #45 RefTypeKill BB02 regmask=[rdx] minReg=1 last> #61 RefTypeKill BB02 regmask=[r8] minReg=1 last> #62 RefTypeKill BB02 regmask=[r9] minReg=1 last> #63 RefTypeKill BB02 regmask=[r10] minReg=1 last> #64 RefTypeKill BB02 regmask=[r11] minReg=1 last> #58 RefTypeFixedReg BB02 regmask=[rax] minReg=1> #35 RefTypeDef CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rax] minReg=1 last> #37 RefTypeDef STORE_LCL_VAR BB02 regmask=[r14] minReg=1> #183 RefTypeUse LCL_VAR BB02 regmask=[r14] minReg=1> #39 RefTypeDef IND BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last> #42 RefTypeDef STORE_LCL_VAR BB02 regmask=[rcx] minReg=1> #43 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #49 RefTypeUse LCL_VAR BB02 regmask=[rcx] minReg=1 fixed> #53 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> #54 RefTypeDef PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> #47 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #81 RefTypeUse LCL_VAR BB02 regmask=[rdx] minReg=1 copy fixed> #55 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> #56 RefTypeDef PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> LCL_VAR BB02 regmask=[rcx] minReg=1 last> #51 RefTypeDef IND BB02 regmask=[rax] minReg=1> BB02 regmask=[rax] minReg=1 last> #57 RefTypeDef IND BB02 regmask=[rax] minReg=1> #59 RefTypeFixedReg BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> #60 RefTypeFixedReg BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rax] minReg=1 last> #65 RefTypeKill BB02 regmask=[rax] minReg=1 last> #71 RefTypeKill BB02 regmask=[rcx] minReg=1 last> #76 RefTypeKill BB02 regmask=[rdx] minReg=1 last> #85 RefTypeKill BB02 regmask=[r8] minReg=1 last> #80 RefTypeKill BB02 regmask=[r9] minReg=1 last> #107 RefTypeKill BB02 regmask=[r10] minReg=1 last> #108 RefTypeKill BB02 regmask=[r11] minReg=1 last> #102 RefTypeFixedReg BB02 regmask=[rax] minReg=1> #67 RefTypeDef CALL BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rax] minReg=1 last> #69 RefTypeDef STORE_LCL_VAR BB02 regmask=[rax] minReg=1> LCL_VAR BB02 regmask=[rax] minReg=1 last> #73 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> #89 RefTypeUse LCL_VAR BB03 regmask=[rcx] minReg=1 copy fixed> #93 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> #94 RefTypeDef PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> #77 RefTypeDef LCL_VAR BB03 regmask=[rdx] minReg=1> #78 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> #95 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> #96 RefTypeDef PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> #82 RefTypeFixedReg BB03 regmask=[r9] minReg=1> #115 RefTypeUse LCL_VAR BB03 regmask=[r9] minReg=1 copy fixed> #97 RefTypeFixedReg BB03 regmask=[r9] minReg=1> #98 RefTypeDef PUTARG_REG BB03 regmask=[r9] minReg=1 fixed> #86 RefTypeDef CNS_INT BB03 regmask=[r8] minReg=1> #87 RefTypeFixedReg BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> #99 RefTypeFixedReg BB03 regmask=[r8] minReg=1> #100 RefTypeDef PUTARG_REG BB03 regmask=[r8] minReg=1 fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last> #91 RefTypeDef IND BB03 regmask=[rax] minReg=1> BB03 regmask=[rax] minReg=1 last> #101 RefTypeDef IND BB03 regmask=[rax] minReg=1> #103 RefTypeFixedReg BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> #104 RefTypeFixedReg BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> #106 RefTypeFixedReg BB03 regmask=[r9] minReg=1> BB03 regmask=[r9] minReg=1 last fixed> #105 RefTypeFixedReg BB03 regmask=[r8] minReg=1> BB03 regmask=[r8] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> #109 RefTypeKill BB03 regmask=[rax] minReg=1 last> #156 RefTypeKill BB03 regmask=[rcx] minReg=1 last> #161 RefTypeKill BB03 regmask=[rdx] minReg=1 last> #172 RefTypeKill BB03 regmask=[r8] minReg=1 last> #173 RefTypeKill BB03 regmask=[r9] minReg=1 last> #174 RefTypeKill BB03 regmask=[r10] minReg=1 last> #175 RefTypeKill BB03 regmask=[r11] minReg=1 last> #169 RefTypeFixedReg BB03 regmask=[rax] minReg=1> #111 RefTypeDef CALL BB03 regmask=[rax] minReg=1 fixed> BB03 regmask=[rax] minReg=1 last> #113 RefTypeDef STORE_LCL_VAR BB03 regmask=[rsi] minReg=1> #129 RefTypeUse LCL_VAR BB03 regmask=[rsi] minReg=1> #117 RefTypeDef CAST BB03 regmask=[rcx] minReg=1> #144 RefTypeUse LCL_VAR BB03 regmask=[rbx] minReg=1> #118 RefTypeDef CAST BB03 regmask=[rdx] minReg=1> BB03 regmask=[rcx] minReg=1 last regOptional> BB03 regmask=[rdx] minReg=1 last> #122 RefTypeDef LCL_VAR BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #124 RefTypeDef IND BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last> #126 RefTypeDef STORE_LCL_VAR BB05 regmask=[rcx] minReg=1> #128 RefTypeUse LCL_VAR BB05 regmask=[rcx] minReg=1 regOptional> LCL_VAR BB06 regmask=[rcx] minReg=1 last regOptional> #141 RefTypeUse LCL_VAR BB06 regmask=[rsi] minReg=1> #132 RefTypeDef LCL_VAR BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last> #134 RefTypeDef ADD BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last> #136 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last> #138 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last> #140 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last> #180 RefTypeUse LCL_VAR BB07 regmask=[rsi] minReg=1> LCL_VAR BB07 regmask=[rdi] minReg=1 last> #153 RefTypeDef STORE_LCL_VAR BB07 regmask=[rdi] minReg=1> LCL_VAR BB07 regmask=[rbx] minReg=1 last> #155 RefTypeDef STORE_LCL_VAR BB07 regmask=[rbx] minReg=1> #147 RefTypeDef LCL_VAR_ADDR BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last> #157 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> #150 RefTypeDef LCL_VAR_ADDR BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last> #152 RefTypeDef STORE_LCL_VAR BB07 regmask=[rdx] minReg=1> #154 RefTypeUse LCL_VAR BB07 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdi] minReg=1 last> LCL_VAR BB07 regmask=[rdx] minReg=1 last> LCL_VAR BB07 regmask=[rbx] minReg=1 last> #158 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> #165 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> #166 RefTypeDef PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> #162 RefTypeDef LCL_VAR_ADDR BB07 regmask=[rdx] minReg=1> #163 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> #167 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> #168 RefTypeDef PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> #170 RefTypeFixedReg BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> #171 RefTypeFixedReg BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> #176 RefTypeKill BB07 regmask=[rax] minReg=1 last> #188 RefTypeKill BB07 regmask=[rcx] minReg=1 last> #193 RefTypeKill BB07 regmask=[rdx] minReg=1 last> #198 RefTypeKill BB07 regmask=[r8] minReg=1 last> #212 RefTypeKill BB07 regmask=[r9] minReg=1 last> #213 RefTypeKill BB07 regmask=[r10] minReg=1 last> #214 RefTypeKill BB07 regmask=[r11] minReg=1 last> #208 RefTypeFixedReg BB07 regmask=[rax] minReg=1> #178 RefTypeDef CALL BB07 regmask=[rax] minReg=1 fixed> BB07 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB08 regmask=[rsi] minReg=1 last> #216 RefTypeDef STORE_LCL_VAR BB08 regmask=[rsi] minReg=1> #366 RefTypeUse LCL_VAR BB13 regmask=[r14] minReg=1 last> #185 RefTypeDef IND BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last> #189 RefTypeDef STORE_LCL_VAR BB13 regmask=[rcx] minReg=1> #190 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> #370 RefTypeUse LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> #202 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> #203 RefTypeDef PUTARG_REG BB14 regmask=[rcx] minReg=1 fixed> #194 RefTypeDef LCL_VAR BB14 regmask=[rdx] minReg=1> #195 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> #204 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> #205 RefTypeDef PUTARG_REG BB14 regmask=[rdx] minReg=1 fixed> #199 RefTypeDef CNS_INT BB14 regmask=[r8] minReg=1> #200 RefTypeFixedReg BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> #206 RefTypeFixedReg BB14 regmask=[r8] minReg=1> #207 RefTypeDef PUTARG_REG BB14 regmask=[r8] minReg=1 fixed> #209 RefTypeFixedReg BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last fixed> #210 RefTypeFixedReg BB14 regmask=[rdx] minReg=1> BB14 regmask=[rdx] minReg=1 last fixed> #211 RefTypeFixedReg BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last fixed> #215 RefTypeKill BB14 regmask=[rax] minReg=1 last> #219 RefTypeKill BB14 regmask=[rcx] minReg=1 last> #220 RefTypeKill BB14 regmask=[rdx] minReg=1 last> #221 RefTypeKill BB14 regmask=[r8] minReg=1 last> #222 RefTypeKill BB14 regmask=[r9] minReg=1 last> #223 RefTypeKill BB14 regmask=[r10] minReg=1 last> #224 RefTypeKill BB14 regmask=[r11] minReg=1 last> #218 RefTypeFixedReg BB14 regmask=[rax] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last copy fixed> #226 RefTypeKill BB09 regmask=[rax] minReg=1 last> #227 RefTypeKill BB09 regmask=[rcx] minReg=1 last> #228 RefTypeKill BB09 regmask=[rdx] minReg=1 last> #229 RefTypeKill BB09 regmask=[r8] minReg=1 last> #230 RefTypeKill BB09 regmask=[r9] minReg=1 last> #231 RefTypeKill BB09 regmask=[r10] minReg=1 last> #232 RefTypeKill BB09 regmask=[r11] minReg=1 last> #241 RefTypeKill BB10 regmask=[rax] minReg=1 last> #235 RefTypeKill BB10 regmask=[rcx] minReg=1 last> #243 RefTypeKill BB10 regmask=[rdx] minReg=1 last> #244 RefTypeKill BB10 regmask=[r8] minReg=1 last> #245 RefTypeKill BB10 regmask=[r9] minReg=1 last> #246 RefTypeKill BB10 regmask=[r10] minReg=1 last> #247 RefTypeKill BB10 regmask=[r11] minReg=1 last> #236 RefTypeDef CNS_INT BB11 regmask=[rcx] minReg=1> #237 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #239 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> #240 RefTypeDef PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> #242 RefTypeFixedReg BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> #256 RefTypeKill BB11 regmask=[rax] minReg=1 last> #250 RefTypeKill BB11 regmask=[rcx] minReg=1 last> #258 RefTypeKill BB11 regmask=[rdx] minReg=1 last> #259 RefTypeKill BB11 regmask=[r8] minReg=1 last> #260 RefTypeKill BB11 regmask=[r9] minReg=1 last> #261 RefTypeKill BB11 regmask=[r10] minReg=1 last> #262 RefTypeKill BB11 regmask=[r11] minReg=1 last> #251 RefTypeDef CNS_INT BB12 regmask=[rcx] minReg=1> #252 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #254 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #255 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #257 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #263 RefTypeKill BB12 regmask=[rax] minReg=1 last> #268 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #276 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #277 RefTypeKill BB12 regmask=[r8] minReg=1 last> #278 RefTypeKill BB12 regmask=[r9] minReg=1 last> #279 RefTypeKill BB12 regmask=[r10] minReg=1 last> #280 RefTypeKill BB12 regmask=[r11] minReg=1 last> #274 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #265 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[rax] minReg=1 last> #314 RefTypeDef STORE_LCL_VAR BB12 regmask=[r14] minReg=1> #269 RefTypeDef CNS_INT BB12 regmask=[rcx] minReg=1> #270 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #272 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #273 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #275 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #281 RefTypeKill BB12 regmask=[rax] minReg=1 last> #285 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #290 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #301 RefTypeKill BB12 regmask=[r8] minReg=1 last> #302 RefTypeKill BB12 regmask=[r9] minReg=1 last> #303 RefTypeKill BB12 regmask=[r10] minReg=1 last> #304 RefTypeKill BB12 regmask=[r11] minReg=1 last> #298 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #283 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[rax] minReg=1 last> #286 RefTypeDef STORE_LCL_VAR BB12 regmask=[rcx] minReg=1> #287 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> #294 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #295 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #291 RefTypeDef CNS_INT BB12 regmask=[rdx] minReg=1> #292 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #296 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> #297 RefTypeDef PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> #299 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #300 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #305 RefTypeKill BB12 regmask=[rax] minReg=1 last> #313 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #309 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #324 RefTypeKill BB12 regmask=[r8] minReg=1 last> #325 RefTypeKill BB12 regmask=[r9] minReg=1 last> #326 RefTypeKill BB12 regmask=[r10] minReg=1 last> #327 RefTypeKill BB12 regmask=[r11] minReg=1 last> #321 RefTypeFixedReg BB12 regmask=[rax] minReg=1> #307 RefTypeDef CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[rax] minReg=1 last> #310 RefTypeDef STORE_LCL_VAR BB12 regmask=[rdx] minReg=1> #311 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> #317 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> #318 RefTypeDef PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> #315 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #329 RefTypeUse LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> #319 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #320 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #323 RefTypeFixedReg BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> #322 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #334 RefTypeKill BB12 regmask=[rax] minReg=1 last> #328 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #336 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #337 RefTypeKill BB12 regmask=[r8] minReg=1 last> #338 RefTypeKill BB12 regmask=[r9] minReg=1 last> #339 RefTypeKill BB12 regmask=[r10] minReg=1 last> #340 RefTypeKill BB12 regmask=[r11] minReg=1 last> #330 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last copy fixed> #332 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> #333 RefTypeDef PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> #335 RefTypeFixedReg BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> #356 RefTypeKill BB12 regmask=[rax] minReg=1 last> #343 RefTypeKill BB12 regmask=[rcx] minReg=1 last> #348 RefTypeKill BB12 regmask=[rdx] minReg=1 last> #359 RefTypeKill BB12 regmask=[r8] minReg=1 last> #360 RefTypeKill BB12 regmask=[r9] minReg=1 last> #361 RefTypeKill BB12 regmask=[r10] minReg=1 last> #362 RefTypeKill BB12 regmask=[r11] minReg=1 last> #344 RefTypeDef IND BB15 regmask=[rcx] minReg=1> #345 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> #352 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> #353 RefTypeDef PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> #349 RefTypeDef CNS_INT BB15 regmask=[rdx] minReg=1> #350 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> #354 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> #355 RefTypeDef PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> #357 RefTypeFixedReg BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> #358 RefTypeFixedReg BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> #363 RefTypeKill BB15 regmask=[rax] minReg=1 last> #372 RefTypeKill BB15 regmask=[rcx] minReg=1 last> #377 RefTypeKill BB15 regmask=[rdx] minReg=1 last> #382 RefTypeKill BB15 regmask=[r8] minReg=1 last> #396 RefTypeKill BB15 regmask=[r9] minReg=1 last> #397 RefTypeKill BB15 regmask=[r10] minReg=1 last> #398 RefTypeKill BB15 regmask=[r11] minReg=1 last> #392 RefTypeFixedReg BB15 regmask=[rax] minReg=1> #365 RefTypeDef CALL BB15 regmask=[rax] minReg=1 fixed> BB15 regmask=[rax] minReg=1 last> #367 RefTypeDef STORE_LCL_VAR BB15 regmask=[r14] minReg=1> LCL_VAR BB15 regmask=[r14] minReg=1 last> #369 RefTypeDef IND BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last> #373 RefTypeDef STORE_LCL_VAR BB15 regmask=[rcx] minReg=1> #374 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> #386 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> #387 RefTypeDef PUTARG_REG BB16 regmask=[rcx] minReg=1 fixed> #378 RefTypeDef LCL_VAR BB16 regmask=[rdx] minReg=1> #379 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> #388 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> #389 RefTypeDef PUTARG_REG BB16 regmask=[rdx] minReg=1 fixed> #383 RefTypeDef CNS_INT BB16 regmask=[r8] minReg=1> #384 RefTypeFixedReg BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> #390 RefTypeFixedReg BB16 regmask=[r8] minReg=1> #391 RefTypeDef PUTARG_REG BB16 regmask=[r8] minReg=1 fixed> #393 RefTypeFixedReg BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last fixed> #394 RefTypeFixedReg BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last fixed> #395 RefTypeFixedReg BB16 regmask=[r8] minReg=1> BB16 regmask=[r8] minReg=1 last fixed> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rcx] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[r8] minReg=1 last> BB16 regmask=[r9] minReg=1 last> BB16 regmask=[r10] minReg=1 last> BB16 regmask=[r11] minReg=1 last> VAR REFPOSITIONS AFTER ALLOCATION --- V00 #72 RefTypeParamDef BB00 regmask=[rsi] minReg=1 fixed> #89 RefTypeUse LCL_VAR BB03 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB03 regmask=[rsi] minReg=1 last> --- V01 #3 RefTypeParamDef BB00 regmask=[rdx] minReg=1 fixed> #7 RefTypeUse LCL_VAR BB01 regmask=[rdx] minReg=1> LCL_VAR BB01 regmask=[rdx] minReg=1 last> --- V02 --- V03 #113 RefTypeDef STORE_LCL_VAR BB03 regmask=[rsi] minReg=1> #129 RefTypeUse LCL_VAR BB03 regmask=[rsi] minReg=1> #141 RefTypeUse LCL_VAR BB06 regmask=[rsi] minReg=1> #180 RefTypeUse LCL_VAR BB07 regmask=[rsi] minReg=1> LCL_VAR BB08 regmask=[rsi] minReg=1 last> --- V04 --- V05 #216 RefTypeDef STORE_LCL_VAR BB08 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rax] minReg=1 last copy fixed> --- V06 --- V07 --- V08 #314 RefTypeDef STORE_LCL_VAR BB12 regmask=[r14] minReg=1> #329 RefTypeUse LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB12 regmask=[rcx] minReg=1 last copy fixed> --- V09 #42 RefTypeDef STORE_LCL_VAR BB02 regmask=[rcx] minReg=1> #49 RefTypeUse LCL_VAR BB02 regmask=[rcx] minReg=1 fixed> LCL_VAR BB02 regmask=[rcx] minReg=1 last> --- V10 --- V11 --- V12 --- V13 #136 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last> --- V14 --- V15 #189 RefTypeDef STORE_LCL_VAR BB13 regmask=[rcx] minReg=1> #370 RefTypeUse LCL_VAR BB14 regmask=[rcx] minReg=1 last fixed> #373 RefTypeDef STORE_LCL_VAR BB15 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last fixed> --- V16 #142 RefTypeDef STORE_LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB07 regmask=[rdi] minReg=1 last> --- V17 #46 RefTypeDef STORE_LCL_VAR BB01 regmask=[rbx] minReg=1> #81 RefTypeUse LCL_VAR BB02 regmask=[rdx] minReg=1 copy fixed> #115 RefTypeUse LCL_VAR BB03 regmask=[r9] minReg=1 copy fixed> #144 RefTypeUse LCL_VAR BB03 regmask=[rbx] minReg=1> LCL_VAR BB07 regmask=[rbx] minReg=1 last> --- V18 --- V19 --- V20 #140 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last> --- V21 --- V22 #138 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last> --- V23 #153 RefTypeDef STORE_LCL_VAR BB07 regmask=[rdi] minReg=1> LCL_VAR BB07 regmask=[rdi] minReg=1 last> --- V24 #155 RefTypeDef STORE_LCL_VAR BB07 regmask=[rbx] minReg=1> LCL_VAR BB07 regmask=[rbx] minReg=1 last> --- V25 --- V26 #286 RefTypeDef STORE_LCL_VAR BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> --- V27 #310 RefTypeDef STORE_LCL_VAR BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> --- V28 --- V29 #152 RefTypeDef STORE_LCL_VAR BB07 regmask=[rdx] minReg=1> #154 RefTypeUse LCL_VAR BB07 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last> --- V30 #157 RefTypeDef STORE_LCL_VAR BB07 regmask=[rcx] minReg=1> LCL_VAR BB07 regmask=[rcx] minReg=1 last fixed> --- V31 --- V32 --- V33 #69 RefTypeDef STORE_LCL_VAR BB02 regmask=[rax] minReg=1> LCL_VAR BB02 regmask=[rax] minReg=1 last> --- V34 #37 RefTypeDef STORE_LCL_VAR BB02 regmask=[r14] minReg=1> #183 RefTypeUse LCL_VAR BB02 regmask=[r14] minReg=1> #366 RefTypeUse LCL_VAR BB13 regmask=[r14] minReg=1 last> #367 RefTypeDef STORE_LCL_VAR BB15 regmask=[r14] minReg=1> LCL_VAR BB15 regmask=[r14] minReg=1 last> --- V35 #126 RefTypeDef STORE_LCL_VAR BB05 regmask=[rcx] minReg=1> #128 RefTypeUse LCL_VAR BB05 regmask=[rcx] minReg=1 regOptional> LCL_VAR BB06 regmask=[rcx] minReg=1 last regOptional> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V03 V05 V15 V16 V17 V34 V35} Has Critical Edges Prior to Resolution BB01 use def in out {V01} {V16 V17} {V00 V01} {V00 V16 V17} Var=Reg beg of BB01: V01=rdx V00=rsi Var=Reg end of BB01: V17=rbx V00=rsi V16=rdi BB02 use def in out {V17} {V02 V09 V33 V34} {V00 V16 V17} {V00 V02 V16 V17 V34} Var=Reg beg of BB02: V17=rbx V00=rsi V16=rdi Var=Reg end of BB02: V34=r14 V17=rbx V00=rsi V16=rdi BB03 use def in out {V00 V02 V17} {V03} {V00 V02 V16 V17 V34} {V02 V03 V16 V17 V34} Var=Reg beg of BB03: V34=r14 V17=rbx V00=rsi V16=rdi Var=Reg end of BB03: V34=r14 V03=rsi V17=rbx V16=rdi BB04 use def in out {V02} {} {V02 V03 V16 V17 V34} {V02 V03 V16 V17 V34} Var=Reg beg of BB04: V34=r14 V03=rsi V17=rbx V16=rdi Var=Reg end of BB04: V34=r14 V03=rsi V17=rbx V16=rdi BB05 use def in out {V02} {V35} {V02 V03 V16 V17 V34} {V02 V03 V16 V17 V34 V35} Var=Reg beg of BB05: V34=r14 V03=rsi V17=rbx V16=rdi Var=Reg end of BB05: V34=r14 V03=rsi V17=rbx V35=rcx V16=rdi BB06 use def in out {V03 V35} {} {V02 V03 V16 V17 V34 V35} {V02 V03 V16 V17 V34} Var=Reg beg of BB06: V34=r14 V03=rsi V17=rbx V35=rcx V16=rdi Var=Reg end of BB06: V34=r14 V03=rsi V17=rbx V16=rdi BB07 use def in out {V02 V03 V16 V17} {V13 V20 V21 V22 V23 V24 V29 V30} {V02 V03 V16 V17 V34} {V02 V03 V34} Var=Reg beg of BB07: V34=r14 V03=rsi V17=rbx V16=rdi Var=Reg end of BB07: V34=r14 V03=rsi BB08 use def in out {V03} {V05} {V02 V03 V34} {V02 V05 V34} Var=Reg beg of BB08: V34=r14 V03=rsi Var=Reg end of BB08: V34=r14 V05=rsi BB09 use def in out {} {} {V02} {V02} Var=Reg beg of BB09: none Var=Reg end of BB09: none BB10 use def in out {} {} {V02} {V02} Var=Reg beg of BB10: none Var=Reg end of BB10: none BB11 use def in out {} {} {V02} {V02} Var=Reg beg of BB11: none Var=Reg end of BB11: none BB12 use def in out {} {V08 V26 V27} {V02} {V02} Var=Reg beg of BB12: none Var=Reg end of BB12: none BB13 use def in out {V34} {V15} {V02 V05 V34} {V02 V05 V15} Var=Reg beg of BB13: V34=r14 V05=rsi Var=Reg end of BB13: V15=rcx V05=rsi BB14 use def in out {V02 V05 V15} {} {V02 V05 V15} {} Var=Reg beg of BB14: V15=rcx V05=rsi Var=Reg end of BB14: none BB15 use def in out {} {V15 V34} {V02} {V02 V15} Var=Reg beg of BB15: none Var=Reg end of BB15: V15=rcx BB16 use def in out {V02 V15} {} {V02 V15} {} Var=Reg beg of BB16: V15=rcx Var=Reg end of BB16: none RESOLVING EDGES Set V00 argument initial register to rsi Set V01 argument initial register to rdx Trees after linear scan register allocator (LSRA) -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [???..???), preds={} succs={BB02} N003 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 rdx REG rdx $c0 /--* t360 byref N005 (???,???) [000516] -c---------- t516 = * LEA(b+0) byref REG NA /--* t516 byref N007 ( 4, 3) [000363] x----------- t363 = * IND byref REG rdi /--* t363 byref N009 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 rdi REG rdi N011 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 rdx (last use) REG rdx $c0 /--* t366 byref N013 (???,???) [000517] -c---------- t517 = * LEA(b+8) byref REG NA /--* t517 byref N015 ( 4, 4) [000369] x----------- t369 = * IND int REG rbx /--* t369 int N017 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 rbx REG rbx ------------ BB02 [000..012), preds={BB01} succs={BB03} N021 ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 REG NA N023 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid REG NA $300 /--* t132 long N025 ( 5, 12) [000133] #----------- t133 = * IND long REG rcx $340 /--* t133 long N027 (???,???) [000518] ------------ t518 = * PUTARG_REG long REG rcx N029 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 REG rdx $45 /--* t134 int N031 (???,???) [000519] ------------ t519 = * PUTARG_REG int REG rdx /--* t518 long arg0 in rcx +--* t519 int arg1 in rdx N033 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t137 byref N035 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 r14 REG r14 N037 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 r14 REG r14 $143 /--* t500 byref N039 (???,???) [000520] -c---------- t520 = * LEA(b+888) byref REG NA /--* t520 byref N041 ( 24, 30) [000140] ---XG------- t140 = * IND ref REG rcx /--* t140 ref N043 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 rcx REG rcx N045 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 rcx REG rcx /--* t11 ref N047 (???,???) [000521] ------------ t521 = * PUTARG_REG ref REG rcx N049 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 rbx REG rbx /--* t145 int N051 (???,???) [000522] ------------ t522 = * PUTARG_REG int REG rdx N053 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 rcx (last use) REG rcx /--* t523 ref N055 ( 2, 2) [000524] -c---------- t524 = * LEA(b+0) byref REG NA /--* t524 byref N057 ( 5, 4) [000525] ------------ t525 = * IND long REG rax /--* t525 long N059 ( 6, 5) [000526] -c---------- t526 = * LEA(b+64) long REG NA /--* t526 long N061 ( 9, 7) [000527] ------------ t527 = * IND long REG rax /--* t527 long N063 ( 10, 8) [000528] -c---------- t528 = * LEA(b+32) long REG NA /--* t528 long N065 ( 13, 10) [000529] -c---------- t529 = * IND long REG NA /--* t521 ref this in rcx +--* t522 int arg1 in rdx +--* t529 long control expr N067 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 /--* t13 ref N069 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 rax REG rax N071 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 rax (last use) REG rax $3c3 /--* t496 ref N073 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 NA REG NA ------------ BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} N077 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 rsi REG rsi $80 /--* t19 ref N079 (???,???) [000530] ------------ t530 = * PUTARG_REG ref REG rcx N081 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 rdx REG rdx $3c3 /--* t20 ref N083 (???,???) [000531] ------------ t531 = * PUTARG_REG ref REG rdx N085 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 rbx REG rbx /--* t150 int N087 (???,???) [000532] ------------ t532 = * PUTARG_REG int REG r9 N089 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 REG r8 $40 /--* t21 int N091 (???,???) [000533] ------------ t533 = * PUTARG_REG int REG r8 N093 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this rsi (last use) REG rsi /--* t534 ref N095 ( 2, 2) [000535] -c---------- t535 = * LEA(b+0) byref REG NA /--* t535 byref N097 ( 5, 4) [000536] ------------ t536 = * IND long REG rax /--* t536 long N099 ( 6, 5) [000537] -c---------- t537 = * LEA(b+96) long REG NA /--* t537 long N101 ( 9, 7) [000538] ------------ t538 = * IND long REG rax /--* t538 long N103 ( 10, 8) [000539] -c---------- t539 = * LEA(b+16) long REG NA /--* t539 long N105 ( 13, 10) [000540] -c---------- t540 = * IND long REG NA /--* t530 ref this in rcx +--* t531 ref arg1 in rdx +--* t532 int arg3 in r9 +--* t533 int arg2 in r8 +--* t540 long control expr N107 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 /--* t27 int N109 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 rsi REG rsi N111 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 rsi REG rsi $246 /--* t34 int N113 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint REG rcx $440 N115 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 rbx REG rbx /--* t155 int N117 ( 2, 3) [000041] ------------ t41 = * CAST long <- int REG rdx /--* t35 long +--* t41 long N119 ( 5, 7) [000042] J------N---- * GT void REG NA N121 ( 7, 9) [000043] ------------ * JTRUE void REG NA ------------ BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} N125 ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 REG NA N127 ( 1, 1) [000046] -c---------- t46 = LCL_VAR ref V02 loc0 u:2 NA REG NA $3c3 N129 ( 1, 1) [000165] -c---------- t165 = CNS_INT ref null REG NA $VN.Null /--* t46 ref +--* t165 ref N131 ( 3, 3) [000166] J------N---- * EQ void REG NA $482 N133 ( 5, 5) [000167] ------------ * JTRUE void REG NA ------------ BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} N137 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 rcx REG rcx $3c3 /--* t196 ref N139 (???,???) [000541] -c---------- t541 = * LEA(b+8) byref REG NA /--* t541 byref N141 ( 5, 4) [000197] ---X-------- t197 = * IND int REG rcx $500 /--* t197 int N143 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 rcx REG rcx N145 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 rcx REG rcx $500 N147 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 0 REG NA $40 /--* t509 int +--* t195 int N149 ( 14, 11) [000199] N--X---N-U-- * LT void REG NA $483 N151 ( 16, 13) [000200] ---X-------- * JTRUE void REG NA ------------ BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} N155 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 rcx (last use) REG rcx $500 N157 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 rsi REG rsi $246 /--* t511 int +--* t244 int N159 ( 3, 3) [000249] N------N-U-- * LT void REG NA $484 N161 ( 5, 5) [000250] ------------ * JTRUE void REG NA ------------ BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} N165 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 rcx REG rcx $3c3 N167 ( 1, 1) [000419] -c---------- t419 = CNS_INT long 16 field offset Fseq[m_arrayData] REG NA $102 /--* t418 ref +--* t419 long N169 ( 5, 4) [000420] -------N---- t420 = * ADD byref REG rcx $146 /--* t420 byref N171 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 rcx REG rcx N173 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 rcx (last use) REG rcx $146 /--* t263 byref N175 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 rcx REG rcx N177 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 rcx (last use) REG rcx $146 /--* t427 byref N179 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 rcx REG rcx N181 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 REG NA N183 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 rcx (last use) REG rcx $146 /--* t430 byref N185 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 NA REG NA N187 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 rsi REG rsi $246 /--* t433 int N189 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 NA REG NA N191 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 REG NA N193 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 rdi (last use) REG rdi /--* t437 byref N195 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 rdi REG rdi N197 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 rbx (last use) REG rbx /--* t440 int N199 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 rbx REG rbx N201 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 REG NA N203 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 rcx * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 REG rcx /--* t278 byref N205 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 rcx REG rcx N207 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 rdx REG rdx /--* t447 byref N209 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 rdx REG rdx N211 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 rdx REG rdx $1c8 /--* t450 byref N213 (???,???) [000542] -c---------- t542 = * LEA(b+0) byref REG NA N215 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 rdi (last use) REG rdi /--* t542 byref +--* t454 byref N217 (???,???) [000512] -A---------- * STOREIND byref REG NA N219 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 rdx (last use) REG rdx $1c8 /--* t457 byref N221 (???,???) [000543] -c---------- t543 = * LEA(b+8) byref REG NA N223 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 rbx (last use) REG rbx /--* t543 byref +--* t461 int N225 (???,???) [000513] -A--------L- * STOREIND int REG NA N227 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 rcx (last use) REG rcx $1c6 /--* t466 byref N229 (???,???) [000544] ------------ t544 = * PUTARG_REG byref REG rcx N231 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 rdx REG rdx /--* t468 byref N233 (???,???) [000545] ------------ t545 = * PUTARG_REG byref REG rdx /--* t544 byref this in rcx +--* t545 byref arg1 in rdx N235 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c N237 ( 1, 1) [000286] -c---------- t286 = CNS_INT int 0 REG NA $40 /--* t280 int +--* t286 int N239 ( 45, 33) [000287] J--XG--N---- * EQ void REG NA $485 N241 ( 47, 35) [000288] ---XG------- * JTRUE void REG NA ------------ BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} N245 ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a REG NA N247 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 rsi (last use) REG rsi $246 /--* t73 int N249 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 rsi REG rsi ------------ BB09 [042..043) (throw), preds={BB07} succs={} N285 ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 REG NA N287 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void ------------ BB10 [000..000) (throw), preds={BB05,BB06} succs={} N291 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void ------------ BB11 [000..000) (throw), preds={BB04} succs={} N295 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 REG rcx $4a /--* t253 int N297 (???,???) [000546] ------------ t546 = * PUTARG_REG int REG rcx /--* t546 int arg0 in rcx N299 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB12 [02E..039) (throw), preds={BB03} succs={} N303 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method REG rcx $302 /--* t85 long N305 (???,???) [000547] ------------ t547 = * PUTARG_REG long REG rcx /--* t547 long arg0 in rcx N307 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 /--* t86 ref N309 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 r14 REG r14 N311 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 REG rcx $49 /--* t388 int N313 (???,???) [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx N315 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 /--* t390 ref N317 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 rcx REG rcx N319 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 rcx (last use) REG rcx $3cd /--* t395 ref N321 (???,???) [000549] ------------ t549 = * PUTARG_REG ref REG rcx N323 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null REG rdx $VN.Null /--* t159 ref N325 (???,???) [000550] ------------ t550 = * PUTARG_REG ref REG rdx /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx N327 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 /--* t160 ref N329 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 rdx REG rdx N331 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 rdx (last use) REG rdx $3d1 /--* t401 ref N333 (???,???) [000551] ------------ t551 = * PUTARG_REG ref REG rdx N335 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 r14 REG r14 $346 /--* t90 ref N337 (???,???) [000552] ------------ t552 = * PUTARG_REG ref REG rcx /--* t551 ref arg1 in rdx +--* t552 ref this in rcx N339 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void N341 ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 REG NA N343 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 r14 (last use) REG r14 $346 /--* t94 ref N345 (???,???) [000553] ------------ t553 = * PUTARG_REG ref REG rcx /--* t553 ref arg0 in rcx N347 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 ------------ BB13 [04E..05B), preds={BB08} succs={BB14} N253 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 r14 (last use) REG r14 $143 /--* t502 byref N255 (???,???) [000554] -c---------- t554 = * LEA(b+888) byref REG NA /--* t554 byref N257 ( 4, 7) [000334] ---XG------- t334 = * IND ref REG rcx /--* t334 ref N259 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 rcx REG rcx ------------ BB14 [05B..05D) (return), preds={BB13} succs={} N263 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 rcx (last use) REG rcx /--* t345 ref N265 (???,???) [000555] ------------ t555 = * PUTARG_REG ref REG rcx N267 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 rdx (last use) REG rdx $3c3 /--* t347 ref N269 (???,???) [000556] ------------ t556 = * PUTARG_REG ref REG rdx N271 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 REG r8 $40 /--* t349 int N273 (???,???) [000557] ------------ t557 = * PUTARG_REG int REG r8 /--* t555 ref this in rcx +--* t556 ref arg1 in rdx +--* t557 int arg2 in r8 N275 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N277 ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b REG NA N279 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 rsi (last use) REG rsi $246 /--* t78 int N281 ( 4, 3) [000079] ------------ * RETURN int REG NA $252 ------------ BB15 [04E..05B), preds={} succs={BB16} N351 ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e REG NA N353 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid REG NA $300 /--* t322 long N355 ( 5, 12) [000323] #----------- t323 = * IND long REG rcx $340 /--* t323 long N357 (???,???) [000558] ------------ t558 = * PUTARG_REG long REG rcx N359 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 REG rdx $45 /--* t324 int N361 (???,???) [000559] ------------ t559 = * PUTARG_REG int REG rdx /--* t558 long arg0 in rcx +--* t559 int arg1 in rdx N363 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 /--* t327 byref N365 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 r14 REG r14 N367 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 r14 (last use) REG r14 $143 /--* t505 byref N369 (???,???) [000560] -c---------- t560 = * LEA(b+888) byref REG NA /--* t560 byref N371 ( 24, 30) [000330] ---XG------- t330 = * IND ref REG rcx /--* t330 ref N373 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 rcx REG rcx ------------ BB16 [???..???) (finret), preds={BB15} succs={} N377 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 rcx (last use) REG rcx /--* t319 ref N379 (???,???) [000561] ------------ t561 = * PUTARG_REG ref REG rcx N381 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 rdx (last use) REG rdx $3c3 /--* t102 ref N383 (???,???) [000562] ------------ t562 = * PUTARG_REG ref REG rdx N385 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 REG r8 $40 /--* t103 int N387 (???,???) [000563] ------------ t563 = * PUTARG_REG int REG r8 /--* t561 ref this in rcx +--* t562 ref arg1 in rdx +--* t563 int arg2 in r8 N389 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void N391 ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a REG NA N393 ( 0, 0) [000108] ------------ RETFILT void REG NA $4c2 ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 0.#0 V1 Parm Alloc rdx | | |V1 a| | | | | | | | 0.#1 V0 Parm Alloc rsi | | |V1 a| | |V0 a| | | | | 1.#2 BB1 PredBB0 | | |V1 a| | |V0 a| | | | | 7.#3 V1 Use Keep rdx | | |V1 a| | |V0 a| | | | | 8.#4 I21 Def Alloc rdi | | |V1 a| | |V0 a|I21a| | | | 9.#5 I21 Use * Keep rdi | | |V1 a| | |V0 a|I21i| | | | 10.#6 V16 Def Alloc rdi | | |V1 a| | |V0 a|V16a| | | | 15.#7 V1 Use * Keep rdx | | |V1 i| | |V0 a|V16a| | | | 16.#8 I22 Def Alloc rbx | | | |I22a| |V0 a|V16a| | | | 17.#9 I22 Use * Keep rbx | | | |I22i| |V0 a|V16a| | | | 18.#10 V17 Def Alloc rbx | | | |V17a| |V0 a|V16a| | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 19.#11 BB2 PredBB1 | | | |V17a| |V0 a|V16a| | | | 26.#12 I23 Def Alloc rcx | |I23a| |V17a| |V0 a|V16a| | | | 27.#13 rcx Fixd Keep rcx | |I23a| |V17a| |V0 a|V16a| | | | 27.#14 I23 Use * Keep rcx | |I23i| |V17a| |V0 a|V16a| | | | 28.#15 rcx Fixd Keep rcx | | | |V17a| |V0 a|V16a| | | | 28.#16 I24 Def Alloc rcx | |I24a| |V17a| |V0 a|V16a| | | | 30.#17 C25 Def Alloc rdx | |I24a|C25a|V17a| |V0 a|V16a| | | | 31.#18 rdx Fixd Keep rdx | |I24a|C25a|V17a| |V0 a|V16a| | | | 31.#19 C25 Use * Keep rdx | |I24a|C25i|V17a| |V0 a|V16a| | | | 32.#20 rdx Fixd Keep rdx | |I24a| |V17a| |V0 a|V16a| | | | 32.#21 I26 Def Alloc rdx | |I24a|I26a|V17a| |V0 a|V16a| | | | 33.#22 rcx Fixd Keep rcx | |I24a|I26a|V17a| |V0 a|V16a| | | | 33.#23 I24 Use * Keep rcx | |I24i|I26a|V17a| |V0 a|V16a| | | | 33.#24 rdx Fixd Keep rdx | | |I26a|V17a| |V0 a|V16a| | | | 33.#25 I26 Use * Keep rdx | | |I26i|V17a| |V0 a|V16a| | | | 34.#26 rax Kill Keep rax | | | |V17a| |V0 a|V16a| | | | 34.#27 rcx Kill Keep rcx | | | |V17a| |V0 a|V16a| | | | 34.#28 rdx Kill Keep rdx | | | |V17a| |V0 a|V16a| | | | 34.#29 r8 Kill Keep r8 | | | |V17a| |V0 a|V16a| | | | 34.#30 r9 Kill Keep r9 | | | |V17a| |V0 a|V16a| | | | 34.#31 r10 Kill Keep r10 | | | |V17a| |V0 a|V16a| | | | 34.#32 r11 Kill Keep r11 | | | |V17a| |V0 a|V16a| | | | 34.#33 rax Fixd Keep rax | | | |V17a| |V0 a|V16a| | | | 34.#34 I27 Def Alloc rax |I27a| | |V17a| |V0 a|V16a| | | | 35.#35 I27 Use * Keep rax |I27i| | |V17a| |V0 a|V16a| | | | 36.#36 V34 Def Alloc r14 | | | |V17a| |V0 a|V16a| | |V34a| 41.#37 V34 Use Keep r14 | | | |V17a| |V0 a|V16a| | |V34a| 42.#38 I28 Def Alloc rcx | |I28a| |V17a| |V0 a|V16a| | |V34a| 43.#39 I28 Use * Keep rcx | |I28i| |V17a| |V0 a|V16a| | |V34a| 44.#40 V9 Def Alloc rcx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 47.#41 rcx Fixd Keep rcx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 47.#42 V9 Use Keep rcx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 48.#43 rcx Fixd Keep rcx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 48.#44 I29 Def PtArg rcx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 51.#45 rdx Fixd Keep rdx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 51.#46 V17 Use Copy rdx | |V9 a|V17a|V17a| |V0 a|V16a| | |V34a| 52.#47 rdx Fixd Keep rdx | |V9 a| |V17a| |V0 a|V16a| | |V34a| 52.#48 I30 Def Alloc rdx | |V9 a|I30a|V17a| |V0 a|V16a| | |V34a| 57.#49 V9 Use * Keep rcx | |V9 i|I30a|V17a| |V0 a|V16a| | |V34a| 58.#50 I31 Def Alloc rax |I31a| |I30a|V17a| |V0 a|V16a| | |V34a| 61.#51 I31 Use * Keep rax |I31i| |I30a|V17a| |V0 a|V16a| | |V34a| 62.#52 I32 Def Alloc rax |I32a| |I30a|V17a| |V0 a|V16a| | |V34a| 67.#53 rcx Fixd Keep rcx |I32a| |I30a|V17a| |V0 a|V16a| | |V34a| 67.#54 I29 Use * PtArg rcx |I32a| |I30a|V17a| |V0 a|V16a| | |V34a| 67.#55 rdx Fixd Keep rdx |I32a| |I30a|V17a| |V0 a|V16a| | |V34a| 67.#56 I30 Use * Keep rdx |I32a| |I30i|V17a| |V0 a|V16a| | |V34a| 67.#57 I32 Use * Keep rax |I32i| | |V17a| |V0 a|V16a| | |V34a| 68.#58 rax Kill Keep rax | | | |V17a| |V0 a|V16a| | |V34a| 68.#59 rcx Kill Keep rcx | | | |V17a| |V0 a|V16a| | |V34a| 68.#60 rdx Kill Keep rdx | | | |V17a| |V0 a|V16a| | |V34a| 68.#61 r8 Kill Keep r8 | | | |V17a| |V0 a|V16a| | |V34a| 68.#62 r9 Kill Keep r9 | | | |V17a| |V0 a|V16a| | |V34a| 68.#63 r10 Kill Keep r10 | | | |V17a| |V0 a|V16a| | |V34a| 68.#64 r11 Kill Keep r11 | | | |V17a| |V0 a|V16a| | |V34a| 68.#65 rax Fixd Keep rax | | | |V17a| |V0 a|V16a| | |V34a| 68.#66 I33 Def Alloc rax |I33a| | |V17a| |V0 a|V16a| | |V34a| 69.#67 I33 Use * Keep rax |I33i| | |V17a| |V0 a|V16a| | |V34a| 70.#68 V33 Def Alloc rax |V33a| | |V17a| |V0 a|V16a| | |V34a| 73.#69 V33 Use * Keep rax |V33i| | |V17a| |V0 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 75.#70 BB3 PredBB2 | | | |V17a| |V0 a|V16a| | |V34a| 79.#71 rcx Fixd Keep rcx | | | |V17a| |V0 a|V16a| | |V34a| 79.#72 V0 Use Copy rcx | |V0 a| |V17a| |V0 a|V16a| | |V34a| 80.#73 rcx Fixd Keep rcx | | | |V17a| |V0 a|V16a| | |V34a| 80.#74 I34 Def Alloc rcx | |I34a| |V17a| |V0 a|V16a| | |V34a| 82.#75 I35 Def Alloc rdx | |I34a|I35a|V17a| |V0 a|V16a| | |V34a| 83.#76 rdx Fixd Keep rdx | |I34a|I35a|V17a| |V0 a|V16a| | |V34a| 83.#77 I35 Use * Keep rdx | |I34a|I35i|V17a| |V0 a|V16a| | |V34a| 84.#78 rdx Fixd Keep rdx | |I34a| |V17a| |V0 a|V16a| | |V34a| 84.#79 I36 Def Alloc rdx | |I34a|I36a|V17a| |V0 a|V16a| | |V34a| 87.#80 r9 Fixd Keep r9 | |I34a|I36a|V17a| |V0 a|V16a| | |V34a| 87.#81 V17 Use Copy r9 | |I34a|I36a|V17a| |V0 a|V16a| |V17a|V34a| 88.#82 r9 Fixd Keep r9 | |I34a|I36a|V17a| |V0 a|V16a| | |V34a| 88.#83 I37 Def Alloc r9 | |I34a|I36a|V17a| |V0 a|V16a| |I37a|V34a| 90.#84 C38 Def Alloc r8 | |I34a|I36a|V17a| |V0 a|V16a|C38a|I37a|V34a| 91.#85 r8 Fixd Keep r8 | |I34a|I36a|V17a| |V0 a|V16a|C38a|I37a|V34a| 91.#86 C38 Use * Keep r8 | |I34a|I36a|V17a| |V0 a|V16a|C38i|I37a|V34a| 92.#87 r8 Fixd Keep r8 | |I34a|I36a|V17a| |V0 a|V16a| |I37a|V34a| 92.#88 I39 Def Alloc r8 | |I34a|I36a|V17a| |V0 a|V16a|I39a|I37a|V34a| 97.#89 V0 Use * Keep rsi | |I34a|I36a|V17a| |V0 i|V16a|I39a|I37a|V34a| 98.#90 I40 Def Alloc rax |I40a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 101.#91 I40 Use * Keep rax |I40i|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 102.#92 I41 Def Alloc rax |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#93 rcx Fixd Keep rcx |I41a|I34a|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#94 I34 Use * Keep rcx |I41a|I34i|I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#95 rdx Fixd Keep rdx |I41a| |I36a|V17a| | |V16a|I39a|I37a|V34a| 107.#96 I36 Use * Keep rdx |I41a| |I36i|V17a| | |V16a|I39a|I37a|V34a| 107.#97 r9 Fixd Keep r9 |I41a| | |V17a| | |V16a|I39a|I37a|V34a| 107.#98 I37 Use * Keep r9 |I41a| | |V17a| | |V16a|I39a|I37i|V34a| 107.#99 r8 Fixd Keep r8 |I41a| | |V17a| | |V16a|I39a| |V34a| 107.#100 I39 Use * Keep r8 |I41a| | |V17a| | |V16a|I39i| |V34a| 107.#101 I41 Use * Keep rax |I41i| | |V17a| | |V16a| | |V34a| 108.#102 rax Kill Keep rax | | | |V17a| | |V16a| | |V34a| 108.#103 rcx Kill Keep rcx | | | |V17a| | |V16a| | |V34a| 108.#104 rdx Kill Keep rdx | | | |V17a| | |V16a| | |V34a| 108.#105 r8 Kill Keep r8 | | | |V17a| | |V16a| | |V34a| 108.#106 r9 Kill Keep r9 | | | |V17a| | |V16a| | |V34a| 108.#107 r10 Kill Keep r10 | | | |V17a| | |V16a| | |V34a| 108.#108 r11 Kill Keep r11 | | | |V17a| | |V16a| | |V34a| 108.#109 rax Fixd Keep rax | | | |V17a| | |V16a| | |V34a| 108.#110 I42 Def Alloc rax |I42a| | |V17a| | |V16a| | |V34a| 109.#111 I42 Use * Keep rax |I42i| | |V17a| | |V16a| | |V34a| 110.#112 V3 Def Alloc rsi | | | |V17a| |V3 a|V16a| | |V34a| 113.#113 V3 Use Keep rsi | | | |V17a| |V3 a|V16a| | |V34a| 114.#114 I43 Def Alloc rcx | |I43a| |V17a| |V3 a|V16a| | |V34a| 117.#115 V17 Use Keep rbx | |I43a| |V17a| |V3 a|V16a| | |V34a| 118.#116 I44 Def Alloc rdx | |I43a|I44a|V17a| |V3 a|V16a| | |V34a| 119.#117 I43 Use * Keep rcx | |I43i|I44a|V17a| |V3 a|V16a| | |V34a| 119.#118 I44 Use * Keep rdx | | |I44i|V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 123.#119 BB4 PredBB3 | | | |V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 135.#120 BB5 PredBB4 | | | |V17a| |V3 a|V16a| | |V34a| 138.#121 I45 Def Alloc rcx | |I45a| |V17a| |V3 a|V16a| | |V34a| 141.#122 I45 Use * Keep rcx | |I45i| |V17a| |V3 a|V16a| | |V34a| 142.#123 I46 Def Alloc rcx | |I46a| |V17a| |V3 a|V16a| | |V34a| 143.#124 I46 Use * Keep rcx | |I46i| |V17a| |V3 a|V16a| | |V34a| 144.#125 V35 Def Alloc rcx | |V35a| |V17a| |V3 a|V16a| | |V34a| 149.#126 V35 Use Keep rcx | |V35a| |V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 153.#127 BB6 PredBB5 | |V35a| |V17a| |V3 a|V16a| | |V34a| 159.#128 V35 Use * Keep rcx | |V35i| |V17a| |V3 a|V16a| | |V34a| 159.#129 V3 Use Keep rsi | | | |V17a| |V3 a|V16a| | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 163.#130 BB7 PredBB6 | | | |V17a| |V3 a|V16a| | |V34a| 166.#131 I47 Def Alloc rcx | |I47a| |V17a| |V3 a|V16a| | |V34a| 169.#132 I47 Use * Keep rcx | |I47i| |V17a| |V3 a|V16a| | |V34a| 170.#133 I48 Def Alloc rcx | |I48a| |V17a| |V3 a|V16a| | |V34a| 171.#134 I48 Use * Keep rcx | |I48i| |V17a| |V3 a|V16a| | |V34a| 172.#135 V13 Def Alloc rcx | |V13a| |V17a| |V3 a|V16a| | |V34a| 175.#136 V13 Use * Keep rcx | |V13i| |V17a| |V3 a|V16a| | |V34a| 176.#137 V22 Def Alloc rcx | |V22a| |V17a| |V3 a|V16a| | |V34a| 179.#138 V22 Use * Keep rcx | |V22i| |V17a| |V3 a|V16a| | |V34a| 180.#139 V20 Def Alloc rcx | |V20a| |V17a| |V3 a|V16a| | |V34a| 185.#140 V20 Use * Keep rcx | |V20i| |V17a| |V3 a|V16a| | |V34a| 189.#141 V3 Use Keep rsi | | | |V17a| |V3 a|V16a| | |V34a| 195.#142 V16 Use * Keep rdi | | | |V17a| |V3 a|V16i| | |V34a| 196.#143 V23 Def Alloc rdi | | | |V17a| |V3 a|V23a| | |V34a| 199.#144 V17 Use * Keep rbx | | | |V17i| |V3 a|V23a| | |V34a| 200.#145 V24 Def Alloc rbx | | | |V24a| |V3 a|V23a| | |V34a| 204.#146 I49 Def Alloc rcx | |I49a| |V24a| |V3 a|V23a| | |V34a| 205.#147 I49 Use * Keep rcx | |I49i| |V24a| |V3 a|V23a| | |V34a| 206.#148 V30 Def Alloc rcx | |V30a| |V24a| |V3 a|V23a| | |V34a| 208.#149 I50 Def Alloc rdx | |V30a|I50a|V24a| |V3 a|V23a| | |V34a| 209.#150 I50 Use * Keep rdx | |V30a|I50i|V24a| |V3 a|V23a| | |V34a| 210.#151 V29 Def Alloc rdx | |V30a|V29a|V24a| |V3 a|V23a| | |V34a| 217.#152 V29 Use Keep rdx | |V30a|V29a|V24a| |V3 a|V23a| | |V34a| 217.#153 V23 Use * Keep rdi | |V30a|V29a|V24a| |V3 a|V23i| | |V34a| 225.#154 V29 Use * Keep rdx | |V30a|V29i|V24a| |V3 a| | | |V34a| 225.#155 V24 Use * Keep rbx | |V30a| |V24i| |V3 a| | | |V34a| 229.#156 rcx Fixd Keep rcx | |V30a| | | |V3 a| | | |V34a| 229.#157 V30 Use * Keep rcx | |V30i| | | |V3 a| | | |V34a| 230.#158 rcx Fixd Keep rcx | | | | | |V3 a| | | |V34a| 230.#159 I51 Def Alloc rcx | |I51a| | | |V3 a| | | |V34a| 232.#160 I52 Def Alloc rdx | |I51a|I52a| | |V3 a| | | |V34a| 233.#161 rdx Fixd Keep rdx | |I51a|I52a| | |V3 a| | | |V34a| 233.#162 I52 Use * Keep rdx | |I51a|I52i| | |V3 a| | | |V34a| 234.#163 rdx Fixd Keep rdx | |I51a| | | |V3 a| | | |V34a| 234.#164 I53 Def Alloc rdx | |I51a|I53a| | |V3 a| | | |V34a| 235.#165 rcx Fixd Keep rcx | |I51a|I53a| | |V3 a| | | |V34a| 235.#166 I51 Use * Keep rcx | |I51i|I53a| | |V3 a| | | |V34a| 235.#167 rdx Fixd Keep rdx | | |I53a| | |V3 a| | | |V34a| 235.#168 I53 Use * Keep rdx | | |I53i| | |V3 a| | | |V34a| 236.#169 rax Kill Keep rax | | | | | |V3 a| | | |V34a| 236.#170 rcx Kill Keep rcx | | | | | |V3 a| | | |V34a| 236.#171 rdx Kill Keep rdx | | | | | |V3 a| | | |V34a| 236.#172 r8 Kill Keep r8 | | | | | |V3 a| | | |V34a| 236.#173 r9 Kill Keep r9 | | | | | |V3 a| | | |V34a| 236.#174 r10 Kill Keep r10 | | | | | |V3 a| | | |V34a| 236.#175 r11 Kill Keep r11 | | | | | |V3 a| | | |V34a| 236.#176 rax Fixd Keep rax | | | | | |V3 a| | | |V34a| 236.#177 I54 Def Alloc rax |I54a| | | | |V3 a| | | |V34a| 239.#178 I54 Use * Keep rax |I54i| | | | |V3 a| | | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 243.#179 BB8 PredBB7 | | | | | |V3 a| | | |V34a| 249.#180 V3 Use * Keep rsi | | | | | |V3 i| | | |V34a| 250.#181 V5 Def Alloc rsi | | | | | |V5 a| | | |V34a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 251.#182 BB13 PredBB8 | | | | | |V5 a| | | |V34a| 257.#183 V34 Use * Keep r14 | | | | | |V5 a| | | |V34i| 258.#184 I55 Def Alloc rcx | |I55a| | | |V5 a| | | | | 259.#185 I55 Use * Keep rcx | |I55i| | | |V5 a| | | | | 260.#186 V15 Def Alloc rcx | |V15a| | | |V5 a| | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 261.#187 BB14 PredBB13 | |V15a| | | |V5 a| | | | | 265.#188 rcx Fixd Keep rcx | |V15a| | | |V5 a| | | | | 265.#189 V15 Use * Keep rcx | |V15i| | | |V5 a| | | | | 266.#190 rcx Fixd Keep rcx | | | | | |V5 a| | | | | 266.#191 I56 Def Alloc rcx | |I56a| | | |V5 a| | | | | 268.#192 I57 Def Alloc rdx | |I56a|I57a| | |V5 a| | | | | 269.#193 rdx Fixd Keep rdx | |I56a|I57a| | |V5 a| | | | | 269.#194 I57 Use * Keep rdx | |I56a|I57i| | |V5 a| | | | | 270.#195 rdx Fixd Keep rdx | |I56a| | | |V5 a| | | | | 270.#196 I58 Def Alloc rdx | |I56a|I58a| | |V5 a| | | | | 272.#197 C59 Def Alloc r8 | |I56a|I58a| | |V5 a| |C59a| | | 273.#198 r8 Fixd Keep r8 | |I56a|I58a| | |V5 a| |C59a| | | 273.#199 C59 Use * Keep r8 | |I56a|I58a| | |V5 a| |C59i| | | 274.#200 r8 Fixd Keep r8 | |I56a|I58a| | |V5 a| | | | | 274.#201 I60 Def Alloc r8 | |I56a|I58a| | |V5 a| |I60a| | | 275.#202 rcx Fixd Keep rcx | |I56a|I58a| | |V5 a| |I60a| | | 275.#203 I56 Use * Keep rcx | |I56i|I58a| | |V5 a| |I60a| | | 275.#204 rdx Fixd Keep rdx | | |I58a| | |V5 a| |I60a| | | 275.#205 I58 Use * Keep rdx | | |I58i| | |V5 a| |I60a| | | 275.#206 r8 Fixd Keep r8 | | | | | |V5 a| |I60a| | | 275.#207 I60 Use * Keep r8 | | | | | |V5 a| |I60i| | | 276.#208 rax Kill Keep rax | | | | | |V5 a| | | | | 276.#209 rcx Kill Keep rcx | | | | | |V5 a| | | | | 276.#210 rdx Kill Keep rdx | | | | | |V5 a| | | | | 276.#211 r8 Kill Keep r8 | | | | | |V5 a| | | | | 276.#212 r9 Kill Keep r9 | | | | | |V5 a| | | | | 276.#213 r10 Kill Keep r10 | | | | | |V5 a| | | | | 276.#214 r11 Kill Keep r11 | | | | | |V5 a| | | | | 281.#215 rax Fixd Keep rax | | | | | |V5 a| | | | | 281.#216 V5 Use * Copy rax |V5 i| | | | |V5 i| | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 283.#217 BB9 PredBB7 | | | | | | | | | | | 288.#218 rax Kill Keep rax | | | | | | | | | | | 288.#219 rcx Kill Keep rcx | | | | | | | | | | | 288.#220 rdx Kill Keep rdx | | | | | | | | | | | 288.#221 r8 Kill Keep r8 | | | | | | | | | | | 288.#222 r9 Kill Keep r9 | | | | | | | | | | | 288.#223 r10 Kill Keep r10 | | | | | | | | | | | 288.#224 r11 Kill Keep r11 | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 289.#225 BB10 PredBB5 | | | | | | | | | | | 292.#226 rax Kill Keep rax | | | | | | | | | | | 292.#227 rcx Kill Keep rcx | | | | | | | | | | | 292.#228 rdx Kill Keep rdx | | | | | | | | | | | 292.#229 r8 Kill Keep r8 | | | | | | | | | | | 292.#230 r9 Kill Keep r9 | | | | | | | | | | | 292.#231 r10 Kill Keep r10 | | | | | | | | | | | 292.#232 r11 Kill Keep r11 | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 293.#233 BB11 PredBB4 | | | | | | | | | | | 296.#234 C61 Def Alloc rcx | |C61a| | | | | | | | | 297.#235 rcx Fixd Keep rcx | |C61a| | | | | | | | | 297.#236 C61 Use * Keep rcx | |C61i| | | | | | | | | 298.#237 rcx Fixd Keep rcx | | | | | | | | | | | 298.#238 I62 Def Alloc rcx | |I62a| | | | | | | | | 299.#239 rcx Fixd Keep rcx | |I62a| | | | | | | | | 299.#240 I62 Use * Keep rcx | |I62i| | | | | | | | | 300.#241 rax Kill Keep rax | | | | | | | | | | | 300.#242 rcx Kill Keep rcx | | | | | | | | | | | 300.#243 rdx Kill Keep rdx | | | | | | | | | | | 300.#244 r8 Kill Keep r8 | | | | | | | | | | | 300.#245 r9 Kill Keep r9 | | | | | | | | | | | 300.#246 r10 Kill Keep r10 | | | | | | | | | | | 300.#247 r11 Kill Keep r11 | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 301.#248 BB12 PredBB3 | | | | | | | | | | | 304.#249 C63 Def Alloc rcx | |C63a| | | | | | | | | 305.#250 rcx Fixd Keep rcx | |C63a| | | | | | | | | 305.#251 C63 Use * Keep rcx | |C63i| | | | | | | | | 306.#252 rcx Fixd Keep rcx | | | | | | | | | | | 306.#253 I64 Def Alloc rcx | |I64a| | | | | | | | | 307.#254 rcx Fixd Keep rcx | |I64a| | | | | | | | | 307.#255 I64 Use * Keep rcx | |I64i| | | | | | | | | 308.#256 rax Kill Keep rax | | | | | | | | | | | 308.#257 rcx Kill Keep rcx | | | | | | | | | | | 308.#258 rdx Kill Keep rdx | | | | | | | | | | | 308.#259 r8 Kill Keep r8 | | | | | | | | | | | 308.#260 r9 Kill Keep r9 | | | | | | | | | | | 308.#261 r10 Kill Keep r10 | | | | | | | | | | | 308.#262 r11 Kill Keep r11 | | | | | | | | | | | 308.#263 rax Fixd Keep rax | | | | | | | | | | | 308.#264 I65 Def Alloc rax |I65a| | | | | | | | | | 309.#265 I65 Use * Keep rax |I65i| | | | | | | | | | 310.#266 V8 Def Alloc r14 | | | | | | | | | |V8 a| 312.#267 C66 Def Alloc rcx | |C66a| | | | | | | |V8 a| 313.#268 rcx Fixd Keep rcx | |C66a| | | | | | | |V8 a| 313.#269 C66 Use * Keep rcx | |C66i| | | | | | | |V8 a| 314.#270 rcx Fixd Keep rcx | | | | | | | | | |V8 a| 314.#271 I67 Def Alloc rcx | |I67a| | | | | | | |V8 a| 315.#272 rcx Fixd Keep rcx | |I67a| | | | | | | |V8 a| 315.#273 I67 Use * Keep rcx | |I67i| | | | | | | |V8 a| 316.#274 rax Kill Keep rax | | | | | | | | | |V8 a| 316.#275 rcx Kill Keep rcx | | | | | | | | | |V8 a| 316.#276 rdx Kill Keep rdx | | | | | | | | | |V8 a| 316.#277 r8 Kill Keep r8 | | | | | | | | | |V8 a| 316.#278 r9 Kill Keep r9 | | | | | | | | | |V8 a| 316.#279 r10 Kill Keep r10 | | | | | | | | | |V8 a| 316.#280 r11 Kill Keep r11 | | | | | | | | | |V8 a| 316.#281 rax Fixd Keep rax | | | | | | | | | |V8 a| 316.#282 I68 Def Alloc rax |I68a| | | | | | | | |V8 a| 317.#283 I68 Use * Keep rax |I68i| | | | | | | | |V8 a| 318.#284 V26 Def Alloc rcx | |V26a| | | | | | | |V8 a| 321.#285 rcx Fixd Keep rcx | |V26a| | | | | | | |V8 a| 321.#286 V26 Use * Keep rcx | |V26i| | | | | | | |V8 a| 322.#287 rcx Fixd Keep rcx | | | | | | | | | |V8 a| 322.#288 I69 Def Alloc rcx | |I69a| | | | | | | |V8 a| 324.#289 C70 Def Alloc rdx | |I69a|C70a| | | | | | |V8 a| 325.#290 rdx Fixd Keep rdx | |I69a|C70a| | | | | | |V8 a| 325.#291 C70 Use * Keep rdx | |I69a|C70i| | | | | | |V8 a| 326.#292 rdx Fixd Keep rdx | |I69a| | | | | | | |V8 a| 326.#293 I71 Def Alloc rdx | |I69a|I71a| | | | | | |V8 a| 327.#294 rcx Fixd Keep rcx | |I69a|I71a| | | | | | |V8 a| 327.#295 I69 Use * Keep rcx | |I69i|I71a| | | | | | |V8 a| 327.#296 rdx Fixd Keep rdx | | |I71a| | | | | | |V8 a| 327.#297 I71 Use * Keep rdx | | |I71i| | | | | | |V8 a| 328.#298 rax Kill Keep rax | | | | | | | | | |V8 a| 328.#299 rcx Kill Keep rcx | | | | | | | | | |V8 a| 328.#300 rdx Kill Keep rdx | | | | | | | | | |V8 a| 328.#301 r8 Kill Keep r8 | | | | | | | | | |V8 a| 328.#302 r9 Kill Keep r9 | | | | | | | | | |V8 a| 328.#303 r10 Kill Keep r10 | | | | | | | | | |V8 a| 328.#304 r11 Kill Keep r11 | | | | | | | | | |V8 a| 328.#305 rax Fixd Keep rax | | | | | | | | | |V8 a| 328.#306 I72 Def Alloc rax |I72a| | | | | | | | |V8 a| 329.#307 I72 Use * Keep rax |I72i| | | | | | | | |V8 a| 330.#308 V27 Def Alloc rdx | | |V27a| | | | | | |V8 a| 333.#309 rdx Fixd Keep rdx | | |V27a| | | | | | |V8 a| 333.#310 V27 Use * Keep rdx | | |V27i| | | | | | |V8 a| 334.#311 rdx Fixd Keep rdx | | | | | | | | | |V8 a| 334.#312 I73 Def Alloc rdx | | |I73a| | | | | | |V8 a| 337.#313 rcx Fixd Keep rcx | | |I73a| | | | | | |V8 a| --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 337.#314 V8 Use Copy rcx | |V8 a|I73a| | | | | | |V8 a| 338.#315 rcx Fixd Keep rcx | | |I73a| | | | | | |V8 a| 338.#316 I74 Def Alloc rcx | |I74a|I73a| | | | | | |V8 a| 339.#317 rdx Fixd Keep rdx | |I74a|I73a| | | | | | |V8 a| 339.#318 I73 Use * Keep rdx | |I74a|I73i| | | | | | |V8 a| 339.#319 rcx Fixd Keep rcx | |I74a| | | | | | | |V8 a| 339.#320 I74 Use * Keep rcx | |I74i| | | | | | | |V8 a| 340.#321 rax Kill Keep rax | | | | | | | | | |V8 a| 340.#322 rcx Kill Keep rcx | | | | | | | | | |V8 a| 340.#323 rdx Kill Keep rdx | | | | | | | | | |V8 a| 340.#324 r8 Kill Keep r8 | | | | | | | | | |V8 a| 340.#325 r9 Kill Keep r9 | | | | | | | | | |V8 a| 340.#326 r10 Kill Keep r10 | | | | | | | | | |V8 a| 340.#327 r11 Kill Keep r11 | | | | | | | | | |V8 a| 345.#328 rcx Fixd Keep rcx | | | | | | | | | |V8 a| 345.#329 V8 Use * Copy rcx | |V8 i| | | | | | | |V8 i| 346.#330 rcx Fixd Keep rcx | | | | | | | | | | | 346.#331 I75 Def Alloc rcx | |I75a| | | | | | | | | 347.#332 rcx Fixd Keep rcx | |I75a| | | | | | | | | 347.#333 I75 Use * Keep rcx | |I75i| | | | | | | | | 348.#334 rax Kill Keep rax | | | | | | | | | | | 348.#335 rcx Kill Keep rcx | | | | | | | | | | | 348.#336 rdx Kill Keep rdx | | | | | | | | | | | 348.#337 r8 Kill Keep r8 | | | | | | | | | | | 348.#338 r9 Kill Keep r9 | | | | | | | | | | | 348.#339 r10 Kill Keep r10 | | | | | | | | | | | 348.#340 r11 Kill Keep r11 | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 349.#341 BB15 PredBB12 | | | | | | | | | | | 356.#342 I76 Def Alloc rcx | |I76a| | | | | | | | | 357.#343 rcx Fixd Keep rcx | |I76a| | | | | | | | | 357.#344 I76 Use * Keep rcx | |I76i| | | | | | | | | 358.#345 rcx Fixd Keep rcx | | | | | | | | | | | 358.#346 I77 Def Alloc rcx | |I77a| | | | | | | | | 360.#347 C78 Def Alloc rdx | |I77a|C78a| | | | | | | | 361.#348 rdx Fixd Keep rdx | |I77a|C78a| | | | | | | | 361.#349 C78 Use * Keep rdx | |I77a|C78i| | | | | | | | 362.#350 rdx Fixd Keep rdx | |I77a| | | | | | | | | 362.#351 I79 Def Alloc rdx | |I77a|I79a| | | | | | | | 363.#352 rcx Fixd Keep rcx | |I77a|I79a| | | | | | | | 363.#353 I77 Use * Keep rcx | |I77i|I79a| | | | | | | | 363.#354 rdx Fixd Keep rdx | | |I79a| | | | | | | | 363.#355 I79 Use * Keep rdx | | |I79i| | | | | | | | 364.#356 rax Kill Keep rax | | | | | | | | | | | 364.#357 rcx Kill Keep rcx | | | | | | | | | | | 364.#358 rdx Kill Keep rdx | | | | | | | | | | | 364.#359 r8 Kill Keep r8 | | | | | | | | | | | 364.#360 r9 Kill Keep r9 | | | | | | | | | | | 364.#361 r10 Kill Keep r10 | | | | | | | | | | | 364.#362 r11 Kill Keep r11 | | | | | | | | | | | 364.#363 rax Fixd Keep rax | | | | | | | | | | | 364.#364 I80 Def Alloc rax |I80a| | | | | | | | | | 365.#365 I80 Use * Keep rax |I80i| | | | | | | | | | 366.#366 V34 Def Alloc r14 | | | | | | | | | |V34a| 371.#367 V34 Use * Keep r14 | | | | | | | | | |V34i| 372.#368 I81 Def Alloc rcx | |I81a| | | | | | | | | 373.#369 I81 Use * Keep rcx | |I81i| | | | | | | | | 374.#370 V15 Def Alloc rcx | |V15a| | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 375.#371 BB16 PredBB15 | |V15a| | | | | | | | | 379.#372 rcx Fixd Keep rcx | |V15a| | | | | | | | | 379.#373 V15 Use * Keep rcx | |V15i| | | | | | | | | 380.#374 rcx Fixd Keep rcx | | | | | | | | | | | 380.#375 I82 Def Alloc rcx | |I82a| | | | | | | | | 382.#376 I83 Def Alloc rdx | |I82a|I83a| | | | | | | | 383.#377 rdx Fixd Keep rdx | |I82a|I83a| | | | | | | | 383.#378 I83 Use * Keep rdx | |I82a|I83i| | | | | | | | 384.#379 rdx Fixd Keep rdx | |I82a| | | | | | | | | 384.#380 I84 Def Alloc rdx | |I82a|I84a| | | | | | | | 386.#381 C85 Def Alloc r8 | |I82a|I84a| | | | |C85a| | | 387.#382 r8 Fixd Keep r8 | |I82a|I84a| | | | |C85a| | | 387.#383 C85 Use * Keep r8 | |I82a|I84a| | | | |C85i| | | 388.#384 r8 Fixd Keep r8 | |I82a|I84a| | | | | | | | 388.#385 I86 Def Alloc r8 | |I82a|I84a| | | | |I86a| | | 389.#386 rcx Fixd Keep rcx | |I82a|I84a| | | | |I86a| | | 389.#387 I82 Use * Keep rcx | |I82i|I84a| | | | |I86a| | | 389.#388 rdx Fixd Keep rdx | | |I84a| | | | |I86a| | | 389.#389 I84 Use * Keep rdx | | |I84i| | | | |I86a| | | 389.#390 r8 Fixd Keep r8 | | | | | | | |I86a| | | 389.#391 I86 Use * Keep r8 | | | | | | | |I86i| | | 390.#392 rax Kill Keep rax | | | | | | | | | | | 390.#393 rcx Kill Keep rcx | | | | | | | | | | | 390.#394 rdx Kill Keep rdx | | | | | | | | | | | 390.#395 r8 Kill Keep r8 | | | | | | | | | | | 390.#396 r9 Kill Keep r9 | | | | | | | | | | | 390.#397 r10 Kill Keep r10 | | | | | | | | | | | 390.#398 r11 Kill Keep r11 | | | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 23 Total Reg Cand Vars: 21 Total number of Intervals: 86 Total number of RefPositions: 398 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V01(rdx) V00(rcx=>rsi) BB01 [???..???), preds={} succs={BB02} ===== N003. V01(rdx) N005. STK = LEA(b+0) ; rdx N007. rdi = IND ; STK * N009. V16(rdi); rdi N011. V01(rdx*) N013. STK = LEA(b+8) ; rdx* N015. rbx = IND ; STK * N017. V17(rbx); rbx Var=Reg end of BB01: V17=rbx V00=rsi V16=rdi BB02 [000..012), preds={BB01} succs={BB03} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V17=rbx V00=rsi V16=rdi N021. IL_OFFSET IL offset: 0x0 REG NA N023. CNS_INT(h) 0x17dd3b1e7b0 cid/mid REG NA N025. rcx = IND N027. rcx = PUTARG_REG; rcx N029. rdx = CNS_INT 327 REG rdx N031. rdx = PUTARG_REG; rdx N033. rax* = CALL help; rcx,rdx * N035. V34(r14); rax* N037. V34(r14) N039. STK = LEA(b+888); r14 N041. rcx = IND ; STK * N043. V09(rcx); rcx N045. V09(rcx) N047. rcx = PUTARG_REG; rcx N049. V17(rbx) N051. rdx = PUTARG_REG; rbx N053. V09(rcx*) N055. STK = LEA(b+0) ; rcx* N057. rax = IND ; STK N059. STK = LEA(b+64); rax N061. rax = IND ; STK N063. STK = LEA(b+32); rax N065. STK = IND ; STK N067. rax = CALLV ind; rcx,rdx,STK * N069. V33(rax); rax N071. V33(rax*) N073. V02 MEM; rax* Var=Reg end of BB02: V34=r14 V17=rbx V00=rsi V16=rdi BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V34=r14 V17=rbx V00=rsi V16=rdi N077. V00(rsi) N079. rcx = PUTARG_REG; rsi N081. rdx = V02 MEM N083. rdx = PUTARG_REG; rdx N085. V17(rbx) N087. r9 = PUTARG_REG; rbx N089. r8 = CNS_INT 0 REG r8 N091. r8 = PUTARG_REG; r8 N093. V00(rsi*) N095. STK = LEA(b+0) ; rsi* N097. rax = IND ; STK N099. STK = LEA(b+96); rax N101. rax = IND ; STK N103. STK = LEA(b+16); rax N105. STK = IND ; STK N107. rax = CALLV ind; rcx,rdx,r9,r8,STK * N109. V03(rsi); rax N111. V03(rsi) N113. rcx = CAST ; rsi N115. V17(rbx) N117. rdx = CAST ; rbx N119. GT ; rcx,rdx N121. JTRUE Var=Reg end of BB03: V34=r14 V03=rsi V17=rbx V16=rdi BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB04: V34=r14 V03=rsi V17=rbx V16=rdi N125. IL_OFFSET IL offset: 0x39 REG NA N127. V02 MEM N129. CNS_INT null REG NA N131. EQ N133. JTRUE Var=Reg end of BB04: V34=r14 V03=rsi V17=rbx V16=rdi BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: V34=r14 V03=rsi V17=rbx V16=rdi N137. rcx = V02 MEM N139. STK = LEA(b+8) ; rcx N141. rcx = IND ; STK * N143. V35(rcx); rcx N145. V35(rcx) N147. CNS_INT 0 REG NA N149. LT ; rcx N151. JTRUE Var=Reg end of BB05: V34=r14 V03=rsi V17=rbx V35=rcx V16=rdi BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB06: V34=r14 V03=rsi V17=rbx V35=rcx V16=rdi N155. V35(rcx*) N157. V03(rsi) N159. LT ; rcx*,rsi N161. JTRUE Var=Reg end of BB06: V34=r14 V03=rsi V17=rbx V16=rdi BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: V34=r14 V03=rsi V17=rbx V16=rdi N165. rcx = V02 MEM N167. CNS_INT 16 field offset Fseq[m_arrayData] REG NA N169. rcx = ADD ; rcx * N171. V13(rcx); rcx N173. V13(rcx*) * N175. V22(rcx); rcx* N177. V22(rcx*) * N179. V20(rcx); rcx* N181. IL_OFFSET IL offset: 0x41 REG NA N183. V20(rcx*) N185. V18 MEM; rcx* N187. V03(rsi) N189. V19 MEM; rsi N191. IL_OFFSET IL offset: 0x42 REG NA N193. V16(rdi*) * N195. V23(rdi); rdi* N197. V17(rbx*) * N199. V24(rbx); rbx* N201. IL_OFFSET IL offset: 0x42 REG NA N203. rcx = LCL_VAR_ADDR V04 loc2 rcx byref V04._pointer (offs=0x00) -> V18 tmp12 int V04._length (offs=0x08) -> V19 tmp13 REG rcx * N205. V30(rcx); rcx N207. rdx = LCL_VAR_ADDR V28 tmp22 rdx REG rdx * N209. V29(rdx); rdx N211. V29(rdx) N213. STK = LEA(b+0) ; rdx N215. V23(rdi*) N217. STOREIND ; STK,rdi* N219. V29(rdx*) N221. STK = LEA(b+8) ; rdx* N223. V24(rbx*) N225. STOREIND ; STK,rbx* N227. V30(rcx*) N229. rcx = PUTARG_REG; rcx* N231. rdx = LCL_VAR_ADDR V28 tmp22 rdx REG rdx N233. rdx = PUTARG_REG; rdx N235. rax = CALL ; rcx,rdx N237. CNS_INT 0 REG NA N239. EQ ; rax N241. JTRUE Var=Reg end of BB07: V34=r14 V03=rsi BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB08: V34=r14 V03=rsi N245. IL_OFFSET IL offset: 0x4a REG NA N247. V03(rsi*) * N249. V05(rsi); rsi* Var=Reg end of BB08: V34=r14 V05=rsi BB13 [04E..05B), preds={BB08} succs={BB14} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB13: V34=r14 V05=rsi N253. V34(r14*) N255. STK = LEA(b+888); r14* N257. rcx = IND ; STK * N259. V15(rcx); rcx Var=Reg end of BB13: V15=rcx V05=rsi BB14 [05B..05D) (return), preds={BB13} succs={} ===== Predecessor for variable locations: BB13 Var=Reg beg of BB14: V15=rcx V05=rsi N263. V15(rcx*) N265. rcx = PUTARG_REG; rcx* N267. rdx* = V02 MEM N269. rdx = PUTARG_REG; rdx* N271. r8 = CNS_INT 0 REG r8 N273. r8 = PUTARG_REG; r8 N275. CALL nullcheck; rcx,rdx,r8 N277. IL_OFFSET IL offset: 0x5b REG NA N279. V05(rsi*) N281. RETURN ; rsi* Var=Reg end of BB14: none BB09 [042..043) (throw), preds={BB07} succs={} ===== Predecessor for variable locations: BB07 Var=Reg beg of BB09: none N285. IL_OFFSET IL offset: 0x42 REG NA N287. CALL Var=Reg end of BB09: none BB10 [000..000) (throw), preds={BB05,BB06} succs={} ===== Predecessor for variable locations: BB05 Var=Reg beg of BB10: none N291. CALL Var=Reg end of BB10: none BB11 [000..000) (throw), preds={BB04} succs={} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB11: none N295. rcx = CNS_INT 2 REG rcx N297. rcx = PUTARG_REG; rcx N299. CALL ; rcx Var=Reg end of BB11: none BB12 [02E..039) (throw), preds={BB03} succs={} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB12: none N303. rcx = CNS_INT(h) 0x17dd3b22ac8 method REG rcx N305. rcx = PUTARG_REG; rcx N307. rax = CALL help; rcx * N309. V08(r14); rax N311. rcx = CNS_INT 0xE904 REG rcx N313. rcx = PUTARG_REG; rcx N315. rax = CALL help; rcx * N317. V26(rcx); rax N319. V26(rcx*) N321. rcx = PUTARG_REG; rcx* N323. rdx = CNS_INT null REG rdx N325. rdx = PUTARG_REG; rdx N327. rax = CALL ; rcx,rdx * N329. V27(rdx); rax N331. V27(rdx*) N333. rdx = PUTARG_REG; rdx* N335. V08(r14) N337. rcx = PUTARG_REG; r14 N339. CALL ; rdx,rcx N341. IL_OFFSET IL offset: 0x38 REG NA N343. V08(r14*) N345. rcx = PUTARG_REG; r14* N347. CALL help; rcx Var=Reg end of BB12: none BB15 [04E..05B), preds={} succs={BB16} ===== Predecessor for variable locations: BB12 Var=Reg beg of BB15: none N351. IL_OFFSET IL offset: 0x4e REG NA N353. CNS_INT(h) 0x17dd3b1e7b0 cid/mid REG NA N355. rcx = IND N357. rcx = PUTARG_REG; rcx N359. rdx = CNS_INT 327 REG rdx N361. rdx = PUTARG_REG; rdx N363. rax* = CALL help; rcx,rdx * N365. V34(r14); rax* N367. V34(r14*) N369. STK = LEA(b+888); r14* N371. rcx = IND ; STK * N373. V15(rcx); rcx Var=Reg end of BB15: V15=rcx BB16 [???..???) (finret), preds={BB15} succs={} ===== Predecessor for variable locations: BB15 Var=Reg beg of BB16: V15=rcx N377. V15(rcx*) N379. rcx = PUTARG_REG; rcx* N381. rdx* = V02 MEM N383. rdx = PUTARG_REG; rdx* N385. r8 = CNS_INT 0 REG r8 N387. r8 = PUTARG_REG; r8 N389. CALL nullcheck; rcx,rdx,r8 N391. IL_OFFSET IL offset: 0x5a REG NA N393. RETFILT Var=Reg end of BB16: none *************** In genGenerateCode() -------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight [IL range] [jump] [EH region] [flags] -------------------------------------------------------------------------------------------------------------------------------------- BB01 [0047] 1 1 [???..???) i internal label target LIR BB02 [0000] 1 BB01 1 [000..012) i gcsafe LIR BB03 [0001] 1 0 BB02 1 [012..02E)-> BB12 ( cond ) T0 try { keep i try label gcsafe LIR BB04 [0003] 1 0 BB03 1 [000..04E)-> BB11 ( cond ) T0 i label target gcsafe LIR BB05 [0021] 1 0 BB04 0.50 [000..000)-> BB10 ( cond ) T0 i internal label target gcsafe idxlen newobj LIR BB06 [0025] 1 0 BB05 0.50 [000..000)-> BB10 ( cond ) T0 i internal gcsafe idxlen LIR BB07 [0027] 1 0 BB06 1 [000..043)-> BB09 ( cond ) T0 i label target gcsafe LIR BB08 [0034] 1 0 BB07 1 [042..043)-> BB13 (always) T0 i label target gcsafe LIR BB09 [0033] 1 0 BB07 0 [042..043) (throw ) T0 i rare label target gcsafe LIR BB10 [0026] 2 0 BB05,BB06 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB11 [0020] 1 0 BB04 0 [000..000) (throw ) T0 i internal rare label target gcsafe LIR BB12 [0002] 1 0 BB03 0 [02E..039) (throw ) T0 } i rare label target gcsafe newobj LIR BB13 [0043] 1 BB08 1 [04E..05B) keep i label target gcsafe LIR cfb BB14 [0046] 1 BB13 1 [05B..05D) (return) keep i label gcsafe LIR cfe ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ funclets follow BB15 [0004] 1 0 0 [04E..05B) H0 F fault { keep i rare label target flet LIR BB16 [0041] 1 0 BB15 0 [???..???) (finret) H0 } keep internal rare label gcsafe LIR -------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V01(rdx) V00(rsi) Modified regs: [rax rcx rdx rbx rsi rdi r8-r11 r14] Callee-saved registers pushed: 4 [rbx rsi rdi r14] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V04 loc2, size=16, stkOffs=-0x40 Assign V28 tmp22, size=16, stkOffs=-0x50 Assign V02 loc0, size=8, stkOffs=-0x58 Assign V32 PSPSym, size=8, stkOffs=-0x60 Assign V31 OutArgs, size=32, stkOffs=-0x80 ; Final local variable assignments ; ; V00 this [V00,T05] ( 4, 4 ) ref -> rsi this class-hnd ; V01 arg1 [V01,T00] ( 8, 8 ) byref -> rdx ld-addr-op ; V02 loc0 [V02,T01] ( 9, 7 ) ref -> [rbp-0x48] do-not-enreg[H] class-hnd ; V03 loc1 [V03,T03] ( 6, 5 ) int -> rsi ; V04 loc2 [V04 ] ( 3, 3 ) struct (16) [rbp-0x30] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V05 loc3 [V05,T17] ( 2, 2 ) int -> rsi ;* V06 tmp0 [V06 ] ( 0, 0 ) ref -> zero-ref class-hnd ;* V07 tmp1 [V07 ] ( 0, 0 ) struct (16) zero-ref ; V08 tmp2 [V08,T20] ( 3, 0 ) ref -> r14 class-hnd exact ; V09 tmp3 [V09,T08] ( 4, 4 ) ref -> rcx class-hnd ;* V10 tmp4 [V10 ] ( 0, 0 ) ubyte -> zero-ref ld-addr-op ;* V11 tmp5 [V11 ] ( 0, 0 ) ref -> zero-ref class-hnd exact ;* V12 tmp6 [V12 ] ( 0, 0 ) struct ( 8) zero-ref ; V13 tmp7 [V13,T06] ( 3, 6 ) byref -> rcx ;* V14 tmp8 [V14 ] ( 0, 0 ) struct (16) zero-ref ; V15 tmp9 [V15,T10] ( 6, 3 ) ref -> rcx class-hnd ; V16 tmp10 [V16,T12] ( 2, 3 ) byref -> rdi V25._pointer(offs=0x00) P-INDEP ; V17 tmp11 [V17,T04] ( 5, 6 ) int -> rbx V25._length(offs=0x08) P-INDEP ; V18 tmp12 [V18 ] ( 2, 2 ) byref -> [rbp-0x30] do-not-enreg[X] addr-exposed V04._pointer(offs=0x00) P-DEP ; V19 tmp13 [V19 ] ( 2, 2 ) int -> [rbp-0x28] do-not-enreg[X] addr-exposed V04._length(offs=0x08) P-DEP ; V20 tmp14 [V20,T13] ( 2, 2 ) byref -> rcx V07._pointer(offs=0x00) P-INDEP ;* V21 tmp15 [V21,T19] ( 0, 0 ) int -> zero-ref V07._length(offs=0x08) P-INDEP ; V22 tmp16 [V22,T14] ( 2, 2 ) byref -> rcx V12._value(offs=0x00) P-INDEP ; V23 tmp17 [V23,T15] ( 2, 2 ) byref -> rdi V14._pointer(offs=0x00) P-INDEP ; V24 tmp18 [V24,T18] ( 2, 2 ) int -> rbx V14._length(offs=0x08) P-INDEP ;* V25 tmp19 [V25 ] ( 0, 0 ) struct (16) zero-ref ; V26 tmp20 [V26,T21] ( 2, 0 ) ref -> rcx ; V27 tmp21 [V27,T22] ( 2, 0 ) ref -> rdx ; V28 tmp22 [V28 ] ( 3, 6 ) struct (16) [rbp-0x40] do-not-enreg[XSB] must-init addr-exposed ; V29 tmp23 [V29,T07] ( 3, 6 ) byref -> rdx stack-byref ; V30 tmp24 [V30,T09] ( 2, 4 ) byref -> rcx ; V31 OutArgs [V31 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] ; V32 PSPSym [V32 ] ( 1, 1 ) long -> [rbp-0x50] do-not-enreg[X] addr-exposed ; V33 tmp27 [V33,T16] ( 2, 2 ) ref -> rax ; V34 cse0 [V34,T02] ( 10, 6 ) byref -> r14 ; V35 cse1 [V35,T11] ( 6, 3 ) int -> rcx ; ; Lcl frame size = 80 =============== Generating BB01 [???..???), preds={} succs={BB02} flags=0x00000000.40030060: i internal label target LIR BB01 IN (2)={V01 V00 } + ByrefExposed + GcHeap OUT(3)={ V17 V00 V16} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V01(rdx) V00(rsi) Change life 0000000000000000 {} -> 0000000000000021 {V00 V01} V01 in reg rdx is becoming live [------] Live regs: 00000000 {} => 00000004 {rdx} V00 in reg rsi is becoming live [------] Live regs: 00000004 {rdx} => 00000044 {rdx rsi} Live regs: (unchanged) 00000044 {rdx rsi} GC regs: (unchanged) 00000040 {rsi} Byref regs: (unchanged) 00000004 {rdx} L_M5191_BB01: Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx} Setting stack level from -1 to 0 Scope info: begin block BB01, IL range [???..???) Scope info: ignoring block beginning Generating: N003 ( 1, 1) [000360] ------------ t360 = LCL_VAR byref V01 arg1 u:2 rdx REG rdx $c0 /--* t360 byref Generating: N005 (???,???) [000516] -c---------- t516 = * LEA(b+0) byref REG NA /--* t516 byref Generating: N007 ( 4, 3) [000363] x----------- t363 = * IND byref REG rdi IN0001: mov rdi, bword ptr [rdx] Byref regs: 00000004 {rdx} => 00000084 {rdx rdi} /--* t363 byref Generating: N009 ( 4, 3) [000364] DA---------- * STORE_LCL_VAR byref V16 tmp10 d:2 rdi REG rdi Byref regs: 00000084 {rdx rdi} => 00000004 {rdx} V16 in reg rdi is becoming live [000364] Live regs: 00000044 {rdx rsi} => 000000C4 {rdx rsi rdi} Live vars: {V00 V01} => {V00 V01 V16} Byref regs: 00000004 {rdx} => 00000084 {rdx rdi} Generating: N011 ( 1, 1) [000366] ------------ t366 = LCL_VAR byref V01 arg1 u:2 rdx (last use) REG rdx $c0 /--* t366 byref Generating: N013 (???,???) [000517] -c---------- t517 = * LEA(b+8) byref REG NA /--* t517 byref Generating: N015 ( 4, 4) [000369] x----------- t369 = * IND int REG rbx V01 in reg rdx is becoming dead [000366] Live regs: 000000C4 {rdx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V16} => {V00 V16} Byref regs: 00000084 {rdx rdi} => 00000080 {rdi} IN0002: mov ebx, dword ptr [rdx+8] /--* t369 int Generating: N017 ( 4, 4) [000370] DA---------- * STORE_LCL_VAR int V17 tmp11 d:2 rbx REG rbx V17 in reg rbx is becoming live [000370] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V16} => {V00 V16 V17} Scope info: end block BB01, IL range [???..???) Scope info: ignoring block end =============== Generating BB02 [000..012), preds={BB01} succs={BB03} flags=0x00000000.40080020: i gcsafe LIR BB02 IN (3)={ V17 V00 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V17 V00 V16} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V17(rbx) V00(rsi) V16(rdi) Liveness not changing: 0000000000001030 {V00 V16 V17} Live regs: 00000000 {} => 000000C8 {rbx rsi rdi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00000080 {rdi} L_M5191_BB02: Scope info: begin block BB02, IL range [000..012) Scope info: open scopes = 0 (V00 this) [000..05D) Added IP mapping: 0x0000 STACK_EMPTY (G_M5191_IG02,ins#2,ofs#6) label Generating: N021 ( 24, 30) [000128] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N023 ( 3, 10) [000132] -c---------- t132 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid REG NA $300 /--* t132 long Generating: N025 ( 5, 12) [000133] #----------- t133 = * IND long REG rcx $340 IN0003: mov rcx, qword ptr [(reloc 0x17dd3b1e7b0)] /--* t133 long Generating: N027 (???,???) [000518] ------------ t518 = * PUTARG_REG long REG rcx Generating: N029 ( 1, 4) [000134] ------------ t134 = CNS_INT int 327 REG rdx $45 IN0004: mov edx, 327 /--* t134 int Generating: N031 (???,???) [000519] ------------ t519 = * PUTARG_REG int REG rdx /--* t518 long arg0 in rcx +--* t519 int arg1 in rdx Generating: N033 ( 20, 23) [000137] H-CXG------- t137 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000080 {rdi} IN0005: call CORINFO_HELP_GETSHARED_GCSTATIC_BASE Byref regs: 00000080 {rdi} => 00000081 {rax rdi} /--* t137 byref Generating: N035 ( 20, 23) [000499] DA-XG------- * STORE_LCL_VAR byref V34 cse0 r14 REG r14 Byref regs: 00000081 {rax rdi} => 00000080 {rdi} IN0006: mov r14, rax V34 in reg r14 is becoming live [000499] Live regs: 000000C8 {rbx rsi rdi} => 000040C8 {rbx rsi rdi r14} Live vars: {V00 V16 V17} => {V00 V16 V17 V34} Byref regs: 00000080 {rdi} => 00004080 {rdi r14} Generating: N037 ( 1, 1) [000500] ------------ t500 = LCL_VAR byref V34 cse0 r14 REG r14 $143 /--* t500 byref Generating: N039 (???,???) [000520] -c---------- t520 = * LEA(b+888) byref REG NA /--* t520 byref Generating: N041 ( 24, 30) [000140] ---XG------- t140 = * IND ref REG rcx IN0007: mov rcx, gword ptr [r14+888] GC regs: 00000040 {rsi} => 00000042 {rcx rsi} /--* t140 ref Generating: N043 ( 24, 30) [000127] DA-XG------- * STORE_LCL_VAR ref V09 tmp3 d:2 rcx REG rcx GC regs: 00000042 {rcx rsi} => 00000040 {rsi} V09 in reg rcx is becoming live [000127] Live regs: 000040C8 {rbx rsi rdi r14} => 000040CA {rcx rbx rsi rdi r14} Live vars: {V00 V16 V17 V34} => {V00 V09 V16 V17 V34} GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N045 ( 1, 1) [000011] ------------ t11 = LCL_VAR ref V09 tmp3 u:2 rcx REG rcx /--* t11 ref Generating: N047 (???,???) [000521] ------------ t521 = * PUTARG_REG ref REG rcx Generating: N049 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V17 tmp11 u:2 rbx REG rbx /--* t145 int Generating: N051 (???,???) [000522] ------------ t522 = * PUTARG_REG int REG rdx IN0008: mov edx, ebx Generating: N053 ( 1, 1) [000523] ------------ t523 = LCL_VAR ref V09 tmp3 rcx (last use) REG rcx /--* t523 ref Generating: N055 ( 2, 2) [000524] -c---------- t524 = * LEA(b+0) byref REG NA /--* t524 byref Generating: N057 ( 5, 4) [000525] ------------ t525 = * IND long REG rax V09 in reg rcx is becoming dead [000523] Live regs: 000040CA {rcx rbx rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V00 V09 V16 V17 V34} => {V00 V16 V17 V34} GC regs: 00000042 {rcx rsi} => 00000040 {rsi} IN0009: mov rax, qword ptr [rcx] /--* t525 long Generating: N059 ( 6, 5) [000526] -c---------- t526 = * LEA(b+64) long REG NA /--* t526 long Generating: N061 ( 9, 7) [000527] ------------ t527 = * IND long REG rax IN000a: mov rax, qword ptr [rax+64] /--* t527 long Generating: N063 ( 10, 8) [000528] -c---------- t528 = * LEA(b+32) long REG NA /--* t528 long Generating: N065 ( 13, 10) [000529] -c---------- t529 = * IND long REG NA /--* t521 ref this in rcx +--* t522 int arg1 in rdx +--* t529 long control expr Generating: N067 ( 22, 12) [000013] --CXG------- t13 = * CALLV ind ref ArrayPool`1.Rent $3c3 Call: GCvars=0000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14} IN000b: call gword ptr [rax+32]ArrayPool`1:Rent(int):ref:this GC regs: 00000040 {rsi} => 00000041 {rax rsi} /--* t13 ref Generating: N069 ( 26, 15) [000495] DA-XG------- * STORE_LCL_VAR ref V33 tmp27 d:2 rax REG rax GC regs: 00000041 {rax rsi} => 00000040 {rsi} V33 in reg rax is becoming live [000495] Live regs: 000040C8 {rbx rsi rdi r14} => 000040C9 {rax rbx rsi rdi r14} Live vars: {V00 V16 V17 V34} => {V00 V16 V17 V33 V34} GC regs: 00000040 {rsi} => 00000041 {rax rsi} Generating: N071 ( 3, 2) [000496] ------------ t496 = LCL_VAR ref V33 tmp27 u:2 rax (last use) REG rax $3c3 /--* t496 ref Generating: N073 ( 3, 3) [000497] DA---------- * STORE_LCL_VAR ref V02 loc0 d:2 NA REG NA V33 in reg rax is becoming dead [000496] Live regs: 000040C9 {rax rbx rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V00 V16 V17 V33 V34} => {V00 V16 V17 V34} GC regs: 00000041 {rax rsi} => 00000040 {rsi} IN000c: mov gword ptr [V02 rbp-48H], rax Live vars: {V00 V16 V17 V34} => {V00 V02 V16 V17 V34} GCvars: {} => {V02} Scope info: end block BB02, IL range [000..012) Scope info: open scopes = 0 (V00 this) [000..05D) =============== Generating BB03 [012..02E) -> BB12 (cond), preds={BB02} succs={BB04,BB12} flags=0x00000000.40090130: keep i try label gcsafe LIR BB03 IN (5)={V02 V34 V17 V00 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V34(r14) V17(rbx) V00(rsi) V16(rdi) Liveness not changing: 0000000000001036 {V00 V02 V16 V17 V34} Live regs: 00000000 {} => 000040C8 {rbx rsi rdi r14} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000000 {} => 00004080 {rdi r14} L_M5191_BB03: G_M5191_IG02: ; offs=000000H, funclet=00 Label: IG03, GCvars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14} Scope info: begin block BB03, IL range [012..02E) Scope info: open scopes = 0 (V00 this) [000..05D) 2 (V02 loc0) [000..05D) Generating: N077 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V00 this u:2 rsi REG rsi $80 /--* t19 ref Generating: N079 (???,???) [000530] ------------ t530 = * PUTARG_REG ref REG rcx IN000d: mov rcx, rsi GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N081 ( 1, 1) [000020] ------------ t20 = LCL_VAR ref V02 loc0 u:2 rdx REG rdx $3c3 IN000e: mov rdx, gword ptr [V02 rbp-48H] GC regs: 00000042 {rcx rsi} => 00000046 {rcx rdx rsi} /--* t20 ref Generating: N083 (???,???) [000531] ------------ t531 = * PUTARG_REG ref REG rdx GC regs: 00000046 {rcx rdx rsi} => 00000042 {rcx rsi} GC regs: 00000042 {rcx rsi} => 00000046 {rcx rdx rsi} Generating: N085 ( 1, 1) [000150] ------------ t150 = LCL_VAR int V17 tmp11 u:2 rbx REG rbx /--* t150 int Generating: N087 (???,???) [000532] ------------ t532 = * PUTARG_REG int REG r9 IN000f: mov r9d, ebx Generating: N089 ( 1, 1) [000021] ------------ t21 = CNS_INT int 0 REG r8 $40 IN0010: xor r8d, r8d /--* t21 int Generating: N091 (???,???) [000533] ------------ t533 = * PUTARG_REG int REG r8 Generating: N093 ( 1, 1) [000534] ------------ t534 = LCL_VAR ref V00 this rsi (last use) REG rsi /--* t534 ref Generating: N095 ( 2, 2) [000535] -c---------- t535 = * LEA(b+0) byref REG NA /--* t535 byref Generating: N097 ( 5, 4) [000536] ------------ t536 = * IND long REG rax V00 in reg rsi is becoming dead [000534] Live regs: 000040C8 {rbx rsi rdi r14} => 00004088 {rbx rdi r14} Live vars: {V00 V02 V16 V17 V34} => {V02 V16 V17 V34} GC regs: 00000046 {rcx rdx rsi} => 00000006 {rcx rdx} IN0011: mov rax, qword ptr [rsi] /--* t536 long Generating: N099 ( 6, 5) [000537] -c---------- t537 = * LEA(b+96) long REG NA /--* t537 long Generating: N101 ( 9, 7) [000538] ------------ t538 = * IND long REG rax IN0012: mov rax, qword ptr [rax+96] /--* t538 long Generating: N103 ( 10, 8) [000539] -c---------- t539 = * LEA(b+16) long REG NA /--* t539 long Generating: N105 ( 13, 10) [000540] -c---------- t540 = * IND long REG NA /--* t530 ref this in rcx +--* t531 ref arg1 in rdx +--* t532 int arg3 in r9 +--* t533 int arg2 in r8 +--* t540 long control expr Generating: N107 ( 24, 16) [000027] --CXG------- t27 = * CALLV ind int Stream.Read $246 GC regs: 00000006 {rcx rdx} => 00000004 {rdx} GC regs: 00000004 {rdx} => 00000000 {} Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14} IN0013: call qword ptr [rax+16]Stream:Read(ref,int,int):int:this /--* t27 int Generating: N109 ( 24, 16) [000032] DA-XG------- * STORE_LCL_VAR int V03 loc1 d:2 rsi REG rsi IN0014: mov esi, eax V03 in reg rsi is becoming live [000032] Live regs: 00004088 {rbx rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V16 V17 V34} => {V02 V03 V16 V17 V34} Generating: N111 ( 1, 1) [000034] ------------ t34 = LCL_VAR int V03 loc1 u:2 rsi REG rsi $246 /--* t34 int Generating: N113 ( 2, 3) [000035] ---------U-- t35 = * CAST long <- ulong <- uint REG rcx $440 IN0015: mov ecx, esi Generating: N115 ( 1, 1) [000155] ------------ t155 = LCL_VAR int V17 tmp11 u:2 rbx REG rbx /--* t155 int Generating: N117 ( 2, 3) [000041] ------------ t41 = * CAST long <- int REG rdx IN0016: movsxd rdx, ebx /--* t35 long +--* t41 long Generating: N119 ( 5, 7) [000042] J------N---- * GT void REG NA IN0017: cmp rcx, rdx Generating: N121 ( 7, 9) [000043] ------------ * JTRUE void REG NA IN0018: jg L_M5191_BB12 Scope info: end block BB03, IL range [012..02E) Scope info: open scopes = 2 (V02 loc0) [000..05D) =============== Generating BB04 [000..04E) -> BB11 (cond), preds={BB03} succs={BB05,BB11} flags=0x00000000.400b0020: i label target gcsafe LIR BB04 IN (5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V34(r14) V03(rsi) V17(rbx) V16(rdi) Liveness not changing: 000000000000101E {V02 V03 V16 V17 V34} Live regs: 00000000 {} => 000040C8 {rbx rsi rdi r14} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00004080 {rdi r14} L_M5191_BB04: G_M5191_IG03: ; offs=000031H, funclet=00 Label: IG04, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14} Scope info: begin block BB04, IL range [000..04E) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) Added IP mapping: 0x0039 STACK_EMPTY (G_M5191_IG04,ins#0,ofs#0) label Generating: N125 ( 0, 0) [000052] ------------ IL_OFFSET void IL offset: 0x39 REG NA Generating: N127 ( 1, 1) [000046] -c---------- t46 = LCL_VAR ref V02 loc0 u:2 NA REG NA $3c3 Generating: N129 ( 1, 1) [000165] -c---------- t165 = CNS_INT ref null REG NA $VN.Null /--* t46 ref +--* t165 ref Generating: N131 ( 3, 3) [000166] J------N---- * EQ void REG NA $482 IN0019: cmp gword ptr [V02 rbp-48H], 0 Generating: N133 ( 5, 5) [000167] ------------ * JTRUE void REG NA IN001a: je L_M5191_BB11 Scope info: end block BB04, IL range [000..04E) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) =============== Generating BB05 [000..000) -> BB10 (cond), preds={BB04} succs={BB06,BB10} flags=0x00000000.40ab0060: i internal label target gcsafe idxlen newobj LIR BB05 IN (5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap OUT(6)={V02 V34 V03 V17 V35 V16} + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V34(r14) V03(rsi) V17(rbx) V16(rdi) Liveness not changing: 000000000000101E {V02 V03 V16 V17 V34} Live regs: 00000000 {} => 000040C8 {rbx rsi rdi r14} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00004080 {rdi r14} L_M5191_BB05: G_M5191_IG04: ; offs=000058H, funclet=00 Label: IG05, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14} Scope info: begin block BB05, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) Added IP mapping: NO_MAP STACK_EMPTY (G_M5191_IG05,ins#0,ofs#0) label Generating: N137 ( 3, 2) [000196] ------------ t196 = LCL_VAR ref V02 loc0 u:2 rcx REG rcx $3c3 IN001b: mov rcx, gword ptr [V02 rbp-48H] GC regs: 00000000 {} => 00000002 {rcx} /--* t196 ref Generating: N139 (???,???) [000541] -c---------- t541 = * LEA(b+8) byref REG NA /--* t541 byref Generating: N141 ( 5, 4) [000197] ---X-------- t197 = * IND int REG rcx $500 GC regs: 00000002 {rcx} => 00000000 {} IN001c: mov ecx, dword ptr [rcx+8] /--* t197 int Generating: N143 ( 9, 7) [000508] DA-X-------- * STORE_LCL_VAR int V35 cse1 rcx REG rcx V35 in reg rcx is becoming live [000508] Live regs: 000040C8 {rbx rsi rdi r14} => 000040CA {rcx rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V34} => {V02 V03 V16 V17 V34 V35} Generating: N145 ( 3, 2) [000509] ------------ t509 = LCL_VAR int V35 cse1 rcx REG rcx $500 Generating: N147 ( 1, 1) [000195] -c---------- t195 = CNS_INT int 0 REG NA $40 /--* t509 int +--* t195 int Generating: N149 ( 14, 11) [000199] N--X---N-U-- * LT void REG NA $483 IN001d: test ecx, ecx Generating: N151 ( 16, 13) [000200] ---X-------- * JTRUE void REG NA IN001e: jb L_M5191_BB10 Scope info: end block BB05, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) =============== Generating BB06 [000..000) -> BB10 (cond), preds={BB05} succs={BB07,BB10} flags=0x00000000.40280060: i internal gcsafe idxlen LIR BB06 IN (6)={V02 V34 V03 V17 V35 V16} + ByrefExposed + GcHeap OUT(5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V34(r14) V03(rsi) V17(rbx) V35(rcx) V16(rdi) Liveness not changing: 000000000000181E {V02 V03 V16 V17 V34 V35} Live regs: 00000000 {} => 000040CA {rcx rbx rsi rdi r14} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00004080 {rdi r14} L_M5191_BB06: Scope info: begin block BB06, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Generating: N155 ( 1, 1) [000511] ------------ t511 = LCL_VAR int V35 cse1 rcx (last use) REG rcx $500 Generating: N157 ( 1, 1) [000244] ------------ t244 = LCL_VAR int V03 loc1 u:2 rsi REG rsi $246 /--* t511 int +--* t244 int Generating: N159 ( 3, 3) [000249] N------N-U-- * LT void REG NA $484 V35 in reg rcx is becoming dead [000511] Live regs: 000040CA {rcx rbx rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V34 V35} => {V02 V03 V16 V17 V34} IN001f: cmp ecx, esi Generating: N161 ( 5, 5) [000250] ------------ * JTRUE void REG NA IN0020: jb L_M5191_BB10 Scope info: end block BB06, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) =============== Generating BB07 [000..043) -> BB09 (cond), preds={BB06} succs={BB08,BB09} flags=0x00000000.400b0420: i label target gcsafe LIR BB07 IN (5)={V02 V34 V03 V17 V16} + ByrefExposed + GcHeap OUT(3)={V02 V34 V03 } + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V34(r14) V03(rsi) V17(rbx) V16(rdi) Liveness not changing: 000000000000101E {V02 V03 V16 V17 V34} Live regs: 00000000 {} => 000040C8 {rbx rsi rdi r14} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00004080 {rdi r14} L_M5191_BB07: G_M5191_IG05: ; offs=000063H, funclet=00 Label: IG06, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14} Scope info: begin block BB07, IL range [000..043) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) Generating: N165 ( 3, 2) [000418] ------------ t418 = LCL_VAR ref V02 loc0 u:2 rcx REG rcx $3c3 IN0021: mov rcx, gword ptr [V02 rbp-48H] GC regs: 00000000 {} => 00000002 {rcx} Generating: N167 ( 1, 1) [000419] -c---------- t419 = CNS_INT long 16 field offset Fseq[m_arrayData] REG NA $102 /--* t418 ref +--* t419 long Generating: N169 ( 5, 4) [000420] -------N---- t420 = * ADD byref REG rcx $146 GC regs: 00000002 {rcx} => 00000000 {} IN0022: add rcx, 16 Byref regs: 00004080 {rdi r14} => 00004082 {rcx rdi r14} /--* t420 byref Generating: N171 ( 5, 4) [000265] DA--G------- * STORE_LCL_VAR byref V13 tmp7 d:2 rcx REG rcx Byref regs: 00004082 {rcx rdi r14} => 00004080 {rdi r14} V13 in reg rcx is becoming live [000265] Live regs: 000040C8 {rbx rsi rdi r14} => 000040CA {rcx rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V34} => {V02 V03 V13 V16 V17 V34} Byref regs: 00004080 {rdi r14} => 00004082 {rcx rdi r14} Generating: N173 ( 1, 1) [000263] ------------ t263 = LCL_VAR byref V13 tmp7 u:2 rcx (last use) REG rcx $146 /--* t263 byref Generating: N175 ( 1, 3) [000230] DA---------- * STORE_LCL_VAR byref V22 tmp16 d:2 rcx REG rcx V13 in reg rcx is becoming dead [000263] Live regs: 000040CA {rcx rbx rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V03 V13 V16 V17 V34} => {V02 V03 V16 V17 V34} Byref regs: 00004082 {rcx rdi r14} => 00004080 {rdi r14} V22 in reg rcx is becoming live [000230] Live regs: 000040C8 {rbx rsi rdi r14} => 000040CA {rcx rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V34} => {V02 V03 V16 V17 V22 V34} Byref regs: 00004080 {rdi r14} => 00004082 {rcx rdi r14} Generating: N177 ( 1, 1) [000427] -------N---- t427 = LCL_VAR byref V22 tmp16 u:2 rcx (last use) REG rcx $146 /--* t427 byref Generating: N179 ( 1, 3) [000428] DA---------- * STORE_LCL_VAR byref V20 tmp14 d:2 rcx REG rcx V22 in reg rcx is becoming dead [000427] Live regs: 000040CA {rcx rbx rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V22 V34} => {V02 V03 V16 V17 V34} Byref regs: 00004082 {rcx rdi r14} => 00004080 {rdi r14} V20 in reg rcx is becoming live [000428] Live regs: 000040C8 {rbx rsi rdi r14} => 000040CA {rcx rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V34} => {V02 V03 V16 V17 V20 V34} Byref regs: 00004080 {rdi r14} => 00004082 {rcx rdi r14} Added IP mapping: 0x0041 (G_M5191_IG06,ins#2,ofs#8) label Generating: N181 ( 10, 8) [000064] ------------ IL_OFFSET void IL offset: 0x41 REG NA Generating: N183 ( 1, 1) [000430] -------N---- t430 = LCL_VAR byref V20 tmp14 u:2 rcx (last use) REG rcx $146 /--* t430 byref Generating: N185 ( 5, 4) [000431] DA--G------- * STORE_LCL_VAR byref (AX) V18 tmp12 NA REG NA V20 in reg rcx is becoming dead [000430] Live regs: 000040CA {rcx rbx rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V03 V16 V17 V20 V34} => {V02 V03 V16 V17 V34} Byref regs: 00004082 {rcx rdi r14} => 00004080 {rdi r14} IN0023: mov bword ptr [V18 rbp-30H], rcx Generating: N187 ( 1, 1) [000433] -------N---- t433 = LCL_VAR int V03 loc1 u:2 rsi REG rsi $246 /--* t433 int Generating: N189 ( 5, 4) [000434] DA--G------- * STORE_LCL_VAR int (AX) V19 tmp13 NA REG NA IN0024: mov dword ptr [V19 rbp-28H], esi Added IP mapping: 0x0042 STACK_EMPTY (G_M5191_IG06,ins#4,ofs#15) Generating: N191 ( 10, 8) [000297] ------------ IL_OFFSET void IL offset: 0x42 REG NA Generating: N193 ( 1, 1) [000437] -------N---- t437 = LCL_VAR byref V16 tmp10 u:2 rdi (last use) REG rdi /--* t437 byref Generating: N195 ( 5, 4) [000438] DA---------- * STORE_LCL_VAR byref V23 tmp17 d:2 rdi REG rdi V16 in reg rdi is becoming dead [000437] Live regs: 000040C8 {rbx rsi rdi r14} => 00004048 {rbx rsi r14} Live vars: {V02 V03 V16 V17 V34} => {V02 V03 V17 V34} Byref regs: 00004080 {rdi r14} => 00004000 {r14} V23 in reg rdi is becoming live [000438] Live regs: 00004048 {rbx rsi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V03 V17 V34} => {V02 V03 V17 V23 V34} Byref regs: 00004000 {r14} => 00004080 {rdi r14} Generating: N197 ( 1, 1) [000440] -------N---- t440 = LCL_VAR int V17 tmp11 u:2 rbx (last use) REG rbx /--* t440 int Generating: N199 ( 5, 4) [000441] DA---------- * STORE_LCL_VAR int V24 tmp18 d:2 rbx REG rbx V17 in reg rbx is becoming dead [000440] Live regs: 000040C8 {rbx rsi rdi r14} => 000040C0 {rsi rdi r14} Live vars: {V02 V03 V17 V23 V34} => {V02 V03 V23 V34} V24 in reg rbx is becoming live [000441] Live regs: 000040C0 {rsi rdi r14} => 000040C8 {rbx rsi rdi r14} Live vars: {V02 V03 V23 V34} => {V02 V03 V23 V24 V34} genIPmappingAdd: ignoring duplicate IL offset 0x42 Generating: N201 ( 47, 35) [000289] ------------ IL_OFFSET void IL offset: 0x42 REG NA Generating: N203 ( 3, 2) [000278] -------N---- t278 = LCL_VAR_ADDR byref V04 loc2 rcx * byref V04._pointer (offs=0x00) -> V18 tmp12 * int V04._length (offs=0x08) -> V19 tmp13 REG rcx IN0025: lea rcx, bword ptr [V04 rbp-30H] Byref regs: 00004080 {rdi r14} => 00004082 {rcx rdi r14} /--* t278 byref Generating: N205 ( 3, 3) [000465] DA--------L- * STORE_LCL_VAR byref V30 tmp24 d:2 rcx REG rcx Byref regs: 00004082 {rcx rdi r14} => 00004080 {rdi r14} V30 in reg rcx is becoming live [000465] Live regs: 000040C8 {rbx rsi rdi r14} => 000040CA {rcx rbx rsi rdi r14} Live vars: {V02 V03 V23 V24 V34} => {V02 V03 V23 V24 V30 V34} Byref regs: 00004080 {rdi r14} => 00004082 {rcx rdi r14} Generating: N207 ( 3, 2) [000447] -------N---- t447 = LCL_VAR_ADDR byref V28 tmp22 rdx REG rdx IN0026: lea rdx, bword ptr [V28 rbp-40H] Byref regs: 00004082 {rcx rdi r14} => 00004086 {rcx rdx rdi r14} /--* t447 byref Generating: N209 ( 3, 3) [000449] DA---------- * STORE_LCL_VAR byref V29 tmp23 d:2 rdx REG rdx Byref regs: 00004086 {rcx rdx rdi r14} => 00004082 {rcx rdi r14} V29 in reg rdx is becoming live [000449] Live regs: 000040CA {rcx rbx rsi rdi r14} => 000040CE {rcx rdx rbx rsi rdi r14} Live vars: {V02 V03 V23 V24 V30 V34} => {V02 V03 V23 V24 V29 V30 V34} Byref regs: 00004082 {rcx rdi r14} => 00004086 {rcx rdx rdi r14} Generating: N211 ( 1, 1) [000450] ------------ t450 = LCL_VAR byref V29 tmp23 u:2 rdx REG rdx $1c8 /--* t450 byref Generating: N213 (???,???) [000542] -c---------- t542 = * LEA(b+0) byref REG NA Generating: N215 ( 3, 2) [000454] -------N---- t454 = LCL_VAR byref V23 tmp17 u:2 rdi (last use) REG rdi /--* t542 byref +--* t454 byref Generating: N217 (???,???) [000512] -A---------- * STOREIND byref REG NA V23 in reg rdi is becoming dead [000454] Live regs: 000040CE {rcx rdx rbx rsi rdi r14} => 0000404E {rcx rdx rbx rsi r14} Live vars: {V02 V03 V23 V24 V29 V30 V34} => {V02 V03 V24 V29 V30 V34} Byref regs: 00004086 {rcx rdx rdi r14} => 00004006 {rcx rdx r14} IN0027: mov bword ptr [rdx], rdi Generating: N219 ( 1, 1) [000457] ------------ t457 = LCL_VAR byref V29 tmp23 u:2 rdx (last use) REG rdx $1c8 /--* t457 byref Generating: N221 (???,???) [000543] -c---------- t543 = * LEA(b+8) byref REG NA Generating: N223 ( 3, 2) [000461] -------N---- t461 = LCL_VAR int V24 tmp18 u:2 rbx (last use) REG rbx /--* t543 byref +--* t461 int Generating: N225 (???,???) [000513] -A--------L- * STOREIND int REG NA V29 in reg rdx is becoming dead [000457] Live regs: 0000404E {rcx rdx rbx rsi r14} => 0000404A {rcx rbx rsi r14} Live vars: {V02 V03 V24 V29 V30 V34} => {V02 V03 V24 V30 V34} Byref regs: 00004006 {rcx rdx r14} => 00004002 {rcx r14} V24 in reg rbx is becoming dead [000461] Live regs: 0000404A {rcx rbx rsi r14} => 00004042 {rcx rsi r14} Live vars: {V02 V03 V24 V30 V34} => {V02 V03 V30 V34} IN0028: mov dword ptr [rdx+8], ebx Generating: N227 ( 1, 1) [000466] ------------ t466 = LCL_VAR byref V30 tmp24 u:2 rcx (last use) REG rcx $1c6 /--* t466 byref Generating: N229 (???,???) [000544] ------------ t544 = * PUTARG_REG byref REG rcx V30 in reg rcx is becoming dead [000466] Live regs: 00004042 {rcx rsi r14} => 00004040 {rsi r14} Live vars: {V02 V03 V30 V34} => {V02 V03 V34} Byref regs: 00004002 {rcx r14} => 00004000 {r14} Byref regs: 00004000 {r14} => 00004002 {rcx r14} Generating: N231 ( 3, 2) [000468] -------N---- t468 = LCL_VAR_ADDR byref V28 tmp22 rdx REG rdx IN0029: lea rdx, bword ptr [V28 rbp-40H] Byref regs: 00004002 {rcx r14} => 00004006 {rcx rdx r14} /--* t468 byref Generating: N233 (???,???) [000545] ------------ t545 = * PUTARG_REG byref REG rdx Byref regs: 00004006 {rcx rdx r14} => 00004002 {rcx r14} Byref regs: 00004002 {rcx r14} => 00004006 {rcx rdx r14} /--* t544 byref this in rcx +--* t545 byref arg1 in rdx Generating: N235 ( 43, 31) [000280] --CXG------- t280 = * CALL int Span`1.TryCopyTo $24c Byref regs: 00004006 {rcx rdx r14} => 00004004 {rdx r14} Byref regs: 00004004 {rdx r14} => 00004000 {r14} Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14} IN002a: call Span`1:TryCopyTo(struct):bool:this Generating: N237 ( 1, 1) [000286] -c---------- t286 = CNS_INT int 0 REG NA $40 /--* t280 int +--* t286 int Generating: N239 ( 45, 33) [000287] J--XG--N---- * EQ void REG NA $485 IN002b: test eax, eax Generating: N241 ( 47, 35) [000288] ---XG------- * JTRUE void REG NA IN002c: je L_M5191_BB09 Scope info: end block BB07, IL range [000..043) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) =============== Generating BB08 [042..043) -> BB13 (always), preds={BB07} succs={BB13} flags=0x00000000.400b0020: i label target gcsafe LIR BB08 IN (3)={V02 V34 V03 } + ByrefExposed + GcHeap OUT(3)={V02 V34 V05} + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V34(r14) V03(rsi) Liveness not changing: 000000000000000E {V02 V03 V34} Live regs: 00000000 {} => 00004040 {rsi r14} GC regs: (unchanged) 00000000 {} Byref regs: 00000000 {} => 00004000 {r14} L_M5191_BB08: G_M5191_IG06: ; offs=00007AH, funclet=00 Label: IG07, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14} Scope info: begin block BB08, IL range [042..043) Scope info: open scopes = 2 (V02 loc0) [000..05D) 3 (V03 loc1) [000..05D) Added IP mapping: 0x004A STACK_EMPTY (G_M5191_IG07,ins#0,ofs#0) label Generating: N245 ( 5, 4) [000076] ------------ IL_OFFSET void IL offset: 0x4a REG NA Generating: N247 ( 1, 1) [000073] ------------ t73 = LCL_VAR int V03 loc1 u:2 rsi (last use) REG rsi $246 /--* t73 int Generating: N249 ( 5, 4) [000075] DA---------- * STORE_LCL_VAR int V05 loc3 d:2 rsi REG rsi V03 in reg rsi is becoming dead [000073] Live regs: 00004040 {rsi r14} => 00004000 {r14} Live vars: {V02 V03 V34} => {V02 V34} V05 in reg rsi is becoming live [000075] Live regs: 00004000 {r14} => 00004040 {rsi r14} Live vars: {V02 V34} => {V02 V05 V34} Scope info: end block BB08, IL range [042..043) Scope info: open scopes = 2 (V02 loc0) [000..05D) IN002d: jmp L_M5191_BB13 =============== Generating BB09 [042..043) (throw), preds={BB07} succs={} flags=0x00000000.400b1020: i rare label target gcsafe LIR BB09 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB09 Change life 0000000000020006 {V02 V05 V34} -> 0000000000000002 {V02} V34 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg rsi is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M5191_BB09: G_M5191_IG07: ; offs=0000A8H, funclet=00 Label: IG08, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB09, IL range [042..043) Scope info: open scopes = 2 (V02 loc0) [000..05D) Added IP mapping: 0x0042 STACK_EMPTY (G_M5191_IG08,ins#0,ofs#0) label Generating: N285 ( 14, 5) [000293] ------------ IL_OFFSET void IL offset: 0x42 REG NA Generating: N287 ( 14, 5) [000292] --CXG------- CALL void ThrowHelper.ThrowArgumentException_DestinationTooShort $VN.Void Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN002e: call ThrowHelper:ThrowArgumentException_DestinationTooShort() Scope info: end block BB09, IL range [042..043) Scope info: open scopes = 2 (V02 loc0) [000..05D) =============== Generating BB10 [000..000) (throw), preds={BB05,BB06} succs={} flags=0x00000000.400b1060: i internal rare label target gcsafe LIR BB10 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB10 Liveness not changing: 0000000000000002 {V02} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M5191_BB10: G_M5191_IG08: ; offs=0000ADH, funclet=00 Label: IG09, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB10, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) Added IP mapping: NO_MAP STACK_EMPTY (G_M5191_IG09,ins#0,ofs#0) label Generating: N291 ( 14, 5) [000203] --CXG------- CALL void ThrowHelper.ThrowArgumentOutOfRangeException $VN.Void Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN002f: call ThrowHelper:ThrowArgumentOutOfRangeException() Scope info: end block BB10, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) =============== Generating BB11 [000..000) (throw), preds={BB04} succs={} flags=0x00000000.400b1060: i internal rare label target gcsafe LIR BB11 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB11 Liveness not changing: 0000000000000002 {V02} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M5191_BB11: G_M5191_IG09: ; offs=0000B2H, funclet=00 Label: IG10, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB11, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) genIPmappingAdd: ignoring duplicate IL offset 0xffffffff Generating: N295 ( 1, 1) [000253] ------------ t253 = CNS_INT int 2 REG rcx $4a IN0030: mov ecx, 2 /--* t253 int Generating: N297 (???,???) [000546] ------------ t546 = * PUTARG_REG int REG rcx /--* t546 int arg0 in rcx Generating: N299 ( 15, 7) [000254] --CXG------- * CALL void ThrowHelper.ThrowArgumentNullException $VN.Void Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0031: call ThrowHelper:ThrowArgumentNullException(int) Scope info: end block BB11, IL range [000..000) Scope info: open scopes = 2 (V02 loc0) [000..05D) =============== Generating BB12 [02E..039) (throw), preds={BB03} succs={} flags=0x00000000.408b1020: i rare label target gcsafe newobj LIR BB12 IN (1)={V02} + ByrefExposed + GcHeap OUT(1)={V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB12 Liveness not changing: 0000000000000002 {V02} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M5191_BB12: G_M5191_IG10: ; offs=0000B7H, funclet=00 Label: IG11, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB12, IL range [02E..039) Scope info: open scopes = 2 (V02 loc0) [000..05D) Generating: N303 ( 3, 10) [000085] ------------ t85 = CNS_INT(h) long 0x17dd3b22ac8 method REG rcx $302 IN0032: lea rcx, [(reloc 0x17dd3b22ac8)] /--* t85 long Generating: N305 (???,???) [000547] ------------ t547 = * PUTARG_REG long REG rcx /--* t547 long arg0 in rcx Generating: N307 ( 17, 16) [000086] --C--------- t86 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $346 Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0033: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t86 ref Generating: N309 ( 21, 19) [000088] DA---------- * STORE_LCL_VAR ref V08 tmp2 d:2 r14 REG r14 GC regs: 00000001 {rax} => 00000000 {} IN0034: mov r14, rax V08 in reg r14 is becoming live [000088] Live regs: 00000000 {} => 00004000 {r14} Live vars: {V02} => {V02 V08} GC regs: 00000000 {} => 00004000 {r14} Generating: N311 ( 1, 4) [000388] ------------ t388 = CNS_INT int 0xE904 REG rcx $49 IN0035: mov ecx, 0xE904 /--* t388 int Generating: N313 (???,???) [000548] ------------ t548 = * PUTARG_REG int REG rcx /--* t548 int arg0 in rcx Generating: N315 ( 15, 10) [000390] --CXG------- t390 = * CALL help ref HELPER.CORINFO_HELP_STRCNS_CURRENT_MODULE $347 Call: GCvars=0000000000000002 {V02}, gcrefRegs=00004000 {r14}, byrefRegs=00000000 {} IN0036: call CORINFO_HELP_STRCNS_CURRENT_MODULE GC regs: 00004000 {r14} => 00004001 {rax r14} /--* t390 ref Generating: N317 ( 19, 13) [000394] DA-XG-----L- * STORE_LCL_VAR ref V26 tmp20 d:2 rcx REG rcx GC regs: 00004001 {rax r14} => 00004000 {r14} IN0037: mov rcx, rax V26 in reg rcx is becoming live [000394] Live regs: 00004000 {r14} => 00004002 {rcx r14} Live vars: {V02 V08} => {V02 V08 V26} GC regs: 00004000 {r14} => 00004002 {rcx r14} Generating: N319 ( 3, 2) [000395] ------------ t395 = LCL_VAR ref V26 tmp20 u:2 rcx (last use) REG rcx $3cd /--* t395 ref Generating: N321 (???,???) [000549] ------------ t549 = * PUTARG_REG ref REG rcx V26 in reg rcx is becoming dead [000395] Live regs: 00004002 {rcx r14} => 00004000 {r14} Live vars: {V02 V08 V26} => {V02 V08} GC regs: 00004002 {rcx r14} => 00004000 {r14} GC regs: 00004000 {r14} => 00004002 {rcx r14} Generating: N323 ( 1, 1) [000159] ------------ t159 = CNS_INT ref null REG rdx $VN.Null IN0038: xor rdx, rdx GC regs: 00004002 {rcx r14} => 00004006 {rcx rdx r14} /--* t159 ref Generating: N325 (???,???) [000550] ------------ t550 = * PUTARG_REG ref REG rdx GC regs: 00004006 {rcx rdx r14} => 00004002 {rcx r14} GC regs: 00004002 {rcx r14} => 00004006 {rcx rdx r14} /--* t549 ref arg0 in rcx +--* t550 ref arg1 in rdx Generating: N327 ( 40, 23) [000160] --CXG------- t160 = * CALL ref SR.GetResourceString $3d1 GC regs: 00004006 {rcx rdx r14} => 00004004 {rdx r14} GC regs: 00004004 {rdx r14} => 00004000 {r14} Call: GCvars=0000000000000002 {V02}, gcrefRegs=00004000 {r14}, byrefRegs=00000000 {} IN0039: call SR:GetResourceString(ref,ref):ref GC regs: 00004000 {r14} => 00004001 {rax r14} /--* t160 ref Generating: N329 ( 44, 26) [000400] DA-XG-----L- * STORE_LCL_VAR ref V27 tmp21 d:2 rdx REG rdx GC regs: 00004001 {rax r14} => 00004000 {r14} IN003a: mov rdx, rax V27 in reg rdx is becoming live [000400] Live regs: 00004000 {r14} => 00004004 {rdx r14} Live vars: {V02 V08} => {V02 V08 V27} GC regs: 00004000 {r14} => 00004004 {rdx r14} Generating: N331 ( 3, 2) [000401] ------------ t401 = LCL_VAR ref V27 tmp21 u:2 rdx (last use) REG rdx $3d1 /--* t401 ref Generating: N333 (???,???) [000551] ------------ t551 = * PUTARG_REG ref REG rdx V27 in reg rdx is becoming dead [000401] Live regs: 00004004 {rdx r14} => 00004000 {r14} Live vars: {V02 V08 V27} => {V02 V08} GC regs: 00004004 {rdx r14} => 00004000 {r14} GC regs: 00004000 {r14} => 00004004 {rdx r14} Generating: N335 ( 3, 2) [000090] ------------ t90 = LCL_VAR ref V08 tmp2 u:2 r14 REG r14 $346 /--* t90 ref Generating: N337 (???,???) [000552] ------------ t552 = * PUTARG_REG ref REG rcx IN003b: mov rcx, r14 GC regs: 00004004 {rdx r14} => 00004006 {rcx rdx r14} /--* t551 ref arg1 in rdx +--* t552 ref this in rcx Generating: N339 ( 67, 38) [000091] --CXG------- * CALL void IOException..ctor $VN.Void GC regs: 00004006 {rcx rdx r14} => 00004002 {rcx r14} GC regs: 00004002 {rcx r14} => 00004000 {r14} Call: GCvars=0000000000000002 {V02}, gcrefRegs=00004000 {r14}, byrefRegs=00000000 {} IN003c: call IOException:.ctor(ref):this Added IP mapping: 0x0038 (G_M5191_IG11,ins#11,ofs#46) label Generating: N341 ( 17, 8) [000097] ------------ IL_OFFSET void IL offset: 0x38 REG NA Generating: N343 ( 3, 2) [000094] ------------ t94 = LCL_VAR ref V08 tmp2 u:2 r14 (last use) REG r14 $346 /--* t94 ref Generating: N345 (???,???) [000553] ------------ t553 = * PUTARG_REG ref REG rcx V08 in reg r14 is becoming dead [000094] Live regs: 00004000 {r14} => 00000000 {} Live vars: {V02 V08} => {V02} GC regs: 00004000 {r14} => 00000000 {} IN003d: mov rcx, r14 GC regs: 00000000 {} => 00000002 {rcx} /--* t553 ref arg0 in rcx Generating: N347 ( 17, 8) [000096] --CXG------- * CALL help void HELPER.CORINFO_HELP_THROW $348 GC regs: 00000002 {rcx} => 00000000 {} Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN003e: call CORINFO_HELP_THROW Scope info: end block BB12, IL range [02E..039) Scope info: open scopes = 2 (V02 loc0) [000..05D) IN003f: int3 =============== Generating BB13 [04E..05B), preds={BB08} succs={BB14} flags=0x00000001.400b0030: keep i label target gcsafe LIR cfb BB13 IN (3)={V02 V34 V05} + ByrefExposed + GcHeap OUT(3)={V02 V15 V05} + ByrefExposed + GcHeap Recording Var Locations at start of BB13 V34(r14) V05(rsi) Change life 0000000000000002 {V02} -> 0000000000020006 {V02 V05 V34} V34 in reg r14 is becoming live [------] Live regs: 00000000 {} => 00004000 {r14} V05 in reg rsi is becoming live [------] Live regs: 00004000 {r14} => 00004040 {rsi r14} Live regs: (unchanged) 00004040 {rsi r14} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00004000 {r14} L_M5191_BB13: G_M5191_IG11: ; offs=0000C1H, funclet=00 Label: IG12, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14} Scope info: begin block BB13, IL range [04E..05B) Scope info: open scopes = 2 (V02 loc0) [000..05D) 5 (V05 loc3) [000..05D) Generating: N253 ( 1, 1) [000502] ------------ t502 = LCL_VAR byref V34 cse0 r14 (last use) REG r14 $143 /--* t502 byref Generating: N255 (???,???) [000554] -c---------- t554 = * LEA(b+888) byref REG NA /--* t554 byref Generating: N257 ( 4, 7) [000334] ---XG------- t334 = * IND ref REG rcx V34 in reg r14 is becoming dead [000502] Live regs: 00004040 {rsi r14} => 00000040 {rsi} Live vars: {V02 V05 V34} => {V02 V05} Byref regs: 00004000 {r14} => 00000000 {} IN0040: mov rcx, gword ptr [r14+888] GC regs: 00000000 {} => 00000002 {rcx} /--* t334 ref Generating: N259 ( 4, 7) [000332] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:3 rcx REG rcx GC regs: 00000002 {rcx} => 00000000 {} V15 in reg rcx is becoming live [000332] Live regs: 00000040 {rsi} => 00000042 {rcx rsi} Live vars: {V02 V05} => {V02 V05 V15} GC regs: 00000000 {} => 00000002 {rcx} Scope info: end block BB13, IL range [04E..05B) Scope info: open scopes = 2 (V02 loc0) [000..05D) 5 (V05 loc3) [000..05D) =============== Generating BB14 [05B..05D) (return), preds={BB13} succs={} flags=0x00000002.40090030: keep i label gcsafe LIR cfe BB14 IN (3)={V02 V15 V05} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB14 V15(rcx) V05(rsi) Liveness not changing: 0000000000020402 {V02 V05 V15} Live regs: 00000000 {} => 00000042 {rcx rsi} GC regs: 00000000 {} => 00000002 {rcx} Byref regs: (unchanged) 00000000 {} L_M5191_BB14: G_M5191_IG12: ; offs=0000F8H, funclet=00 Label: IG13, GCvars=0000000000000002 {V02}, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {} Scope info: begin block BB14, IL range [05B..05D) Scope info: open scopes = 2 (V02 loc0) [000..05D) 5 (V05 loc3) [000..05D) Generating: N263 ( 3, 2) [000345] ------------ t345 = LCL_VAR ref V15 tmp9 u:3 rcx (last use) REG rcx /--* t345 ref Generating: N265 (???,???) [000555] ------------ t555 = * PUTARG_REG ref REG rcx V15 in reg rcx is becoming dead [000345] Live regs: 00000042 {rcx rsi} => 00000040 {rsi} Live vars: {V02 V05 V15} => {V02 V05} GC regs: 00000002 {rcx} => 00000000 {} GC regs: 00000000 {} => 00000002 {rcx} Generating: N267 ( 1, 1) [000347] ------------ t347 = LCL_VAR ref V02 loc0 u:2 rdx (last use) REG rdx $3c3 IN0041: mov rdx, gword ptr [V02 rbp-48H] Live vars: {V02 V05} => {V05} GCvars: {V02} => {} GC regs: 00000002 {rcx} => 00000006 {rcx rdx} /--* t347 ref Generating: N269 (???,???) [000556] ------------ t556 = * PUTARG_REG ref REG rdx GC regs: 00000006 {rcx rdx} => 00000002 {rcx} GC regs: 00000002 {rcx} => 00000006 {rcx rdx} Generating: N271 ( 1, 1) [000349] ------------ t349 = CNS_INT int 0 REG r8 $40 IN0042: xor r8d, r8d /--* t349 int Generating: N273 (???,???) [000557] ------------ t557 = * PUTARG_REG int REG r8 /--* t555 ref this in rcx +--* t556 ref arg1 in rdx +--* t557 int arg2 in r8 Generating: N275 ( 19, 13) [000344] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void GC regs: 00000006 {rcx rdx} => 00000004 {rdx} GC regs: 00000004 {rdx} => 00000000 {} IN0043: cmp dword ptr [rcx], ecx Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0044: call TlsOverPerCoreLockedStacksArrayPool`1:Return(ref,bool):this Added IP mapping: 0x005B STACK_EMPTY (G_M5191_IG13,ins#4,ofs#14) label Generating: N277 ( 4, 3) [000080] ------------ IL_OFFSET void IL offset: 0x5b REG NA Generating: N279 ( 3, 2) [000078] ------------ t78 = LCL_VAR int V05 loc3 u:2 rsi (last use) REG rsi $246 /--* t78 int Generating: N281 ( 4, 3) [000079] ------------ * RETURN int REG NA $252 V05 in reg rsi is becoming dead [000078] Live regs: 00000040 {rsi} => 00000000 {} Live vars: {V05} => {} IN0045: mov eax, esi Scope info: end block BB14, IL range [05B..05D) Scope info: ending scope, LVnum=1 [000..05D) Scope info: ending scope, LVnum=2 [000..05D) Scope info: ending scope, LVnum=3 [000..05D) Scope info: ending scope, LVnum=4 [000..05D) Scope info: ending scope, LVnum=5 [000..05D) Scope info: ending scope, LVnum=0 [000..05D) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M5191_IG13,ins#5,ofs#16) label Reserving epilog IG for block BB14 G_M5191_IG13: ; offs=0000FFH, funclet=00 *************** After placeholder IG creation G_M5191_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M5191_IG02: ; offs=000000H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref G_M5191_IG03: ; offs=000031H, size=0027H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref G_M5191_IG04: ; offs=000058H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG05: ; offs=000063H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG06: ; offs=00007AH, size=002EH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG07: ; offs=0000A8H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG08: ; offs=0000ADH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG09: ; offs=0000B2H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG10: ; offs=0000B7H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG11: ; offs=0000C1H, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG12: ; offs=0000F8H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG13: ; offs=0000FFH, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG14: ; epilog placeholder, next placeholder=, BB14 [0046], epilog, emitadd <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000002 {rcx}, InitByrefRegs=00000000 {} G_M5191_IG15: ; offs=00020FH, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB15 [04E..05B), preds={} succs={BB16} flags=0x00000004.40031230: keep i rare label target flet LIR BB15 IN (1)={V02 } + ByrefExposed + GcHeap OUT(2)={V02 V15} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 Change life 0000000000000000 {} -> 0000000000000002 {V02} V02 becoming live Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M5191_BB15: Label: IG15, GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: found beginning of funclet region at block BB15; ignoring following blocks Reserving funclet prolog IG for block BB15 Added IP mapping: PROLOG STACK_EMPTY (G_M5191_IG15,ins#0,ofs#256) label *************** After placeholder IG creation G_M5191_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M5191_IG02: ; offs=000000H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref G_M5191_IG03: ; offs=000031H, size=0027H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref G_M5191_IG04: ; offs=000058H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG05: ; offs=000063H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG06: ; offs=00007AH, size=002EH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG07: ; offs=0000A8H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG08: ; offs=0000ADH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG09: ; offs=0000B2H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG10: ; offs=0000B7H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG11: ; offs=0000C1H, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG12: ; offs=0000F8H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG13: ; offs=0000FFH, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG14: ; epilog placeholder, next placeholder=IG15 , BB14 [0046], epilog, emitadd <-- First placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000002 {rcx}, InitByrefRegs=00000000 {} G_M5191_IG15: ; func=01, funclet prolog placeholder, next placeholder=, BB15 [0004], funclet prolog <-- Last placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M5191_IG16: ; offs=00030FH, size=0000H, gcrefRegs=00000000 {} <-- Current IG Added IP mapping: 0x004E STACK_EMPTY (G_M5191_IG16,ins#0,ofs#0) label Generating: N351 ( 24, 30) [000318] ------------ IL_OFFSET void IL offset: 0x4e REG NA Generating: N353 ( 3, 10) [000322] -c---------- t322 = CNS_INT(h) long 0x17dd3b1e7b0 cid/mid REG NA $300 /--* t322 long Generating: N355 ( 5, 12) [000323] #----------- t323 = * IND long REG rcx $340 IN0046: mov rcx, qword ptr [(reloc 0x17dd3b1e7b0)] /--* t323 long Generating: N357 (???,???) [000558] ------------ t558 = * PUTARG_REG long REG rcx Generating: N359 ( 1, 4) [000324] ------------ t324 = CNS_INT int 327 REG rdx $45 IN0047: mov edx, 327 /--* t324 int Generating: N361 (???,???) [000559] ------------ t559 = * PUTARG_REG int REG rdx /--* t558 long arg0 in rcx +--* t559 int arg1 in rdx Generating: N363 ( 20, 23) [000327] H-CXG------- t327 = * CALL help byref HELPER.CORINFO_HELP_GETSHARED_GCSTATIC_BASE $143 Call: GCvars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0048: call CORINFO_HELP_GETSHARED_GCSTATIC_BASE Byref regs: 00000000 {} => 00000001 {rax} /--* t327 byref Generating: N365 ( 20, 23) [000504] DA-XG------- * STORE_LCL_VAR byref V34 cse0 r14 REG r14 Byref regs: 00000001 {rax} => 00000000 {} IN0049: mov r14, rax V34 in reg r14 is becoming live [000504] Live regs: 00000000 {} => 00004000 {r14} Live vars: {V02} => {V02 V34} Byref regs: 00000000 {} => 00004000 {r14} Generating: N367 ( 1, 1) [000505] ------------ t505 = LCL_VAR byref V34 cse0 r14 (last use) REG r14 $143 /--* t505 byref Generating: N369 (???,???) [000560] -c---------- t560 = * LEA(b+888) byref REG NA /--* t560 byref Generating: N371 ( 24, 30) [000330] ---XG------- t330 = * IND ref REG rcx V34 in reg r14 is becoming dead [000505] Live regs: 00004000 {r14} => 00000000 {} Live vars: {V02 V34} => {V02} Byref regs: 00004000 {r14} => 00000000 {} IN004a: mov rcx, gword ptr [r14+888] GC regs: 00000000 {} => 00000002 {rcx} /--* t330 ref Generating: N373 ( 24, 30) [000317] DA-XG------- * STORE_LCL_VAR ref V15 tmp9 d:2 rcx REG rcx GC regs: 00000002 {rcx} => 00000000 {} V15 in reg rcx is becoming live [000317] Live regs: 00000000 {} => 00000002 {rcx} Live vars: {V02} => {V02 V15} GC regs: 00000000 {} => 00000002 {rcx} =============== Generating BB16 [???..???) (finret), preds={BB15} succs={} flags=0x00000004.40091050: keep internal rare label gcsafe LIR BB16 IN (2)={V02 V15} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB16 V15(rcx) Liveness not changing: 0000000000000402 {V02 V15} Live regs: 00000000 {} => 00000002 {rcx} GC regs: 00000000 {} => 00000002 {rcx} Byref regs: (unchanged) 00000000 {} L_M5191_BB16: G_M5191_IG16: ; offs=00030FH, funclet=01 Label: IG17, GCvars=0000000000000002 {V02}, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {} Added IP mapping: NO_MAP STACK_EMPTY (G_M5191_IG17,ins#0,ofs#0) label Generating: N377 ( 3, 2) [000319] ------------ t319 = LCL_VAR ref V15 tmp9 u:2 rcx (last use) REG rcx /--* t319 ref Generating: N379 (???,???) [000561] ------------ t561 = * PUTARG_REG ref REG rcx V15 in reg rcx is becoming dead [000319] Live regs: 00000002 {rcx} => 00000000 {} Live vars: {V02 V15} => {V02} GC regs: 00000002 {rcx} => 00000000 {} GC regs: 00000000 {} => 00000002 {rcx} Generating: N381 ( 1, 1) [000102] ------------ t102 = LCL_VAR ref V02 loc0 u:2 rdx (last use) REG rdx $3c3 IN004b: mov rdx, gword ptr [V02 rbp-48H] Live vars: {V02} => {} GCvars: {V02} => {} GC regs: 00000002 {rcx} => 00000006 {rcx rdx} /--* t102 ref Generating: N383 (???,???) [000562] ------------ t562 = * PUTARG_REG ref REG rdx GC regs: 00000006 {rcx rdx} => 00000002 {rcx} GC regs: 00000002 {rcx} => 00000006 {rcx rdx} Generating: N385 ( 1, 1) [000103] ------------ t103 = CNS_INT int 0 REG r8 $40 IN004c: xor r8d, r8d /--* t103 int Generating: N387 (???,???) [000563] ------------ t563 = * PUTARG_REG int REG r8 /--* t561 ref this in rcx +--* t562 ref arg1 in rdx +--* t563 int arg2 in r8 Generating: N389 ( 19, 13) [000104] --CXG------- * CALL nullcheck void TlsOverPerCoreLockedStacksArrayPool`1.Return $VN.Void GC regs: 00000006 {rcx rdx} => 00000004 {rdx} GC regs: 00000004 {rdx} => 00000000 {} IN004d: cmp dword ptr [rcx], ecx Call: GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN004e: call TlsOverPerCoreLockedStacksArrayPool`1:Return(ref,bool):this Added IP mapping: 0x005A STACK_EMPTY (G_M5191_IG17,ins#4,ofs#14) label Generating: N391 ( 0, 0) [000109] ------------ IL_OFFSET void IL offset: 0x5a REG NA Generating: N393 ( 0, 0) [000108] ------------ RETFILT void REG NA $4c2 Reserving funclet epilog IG for block BB16 IN004f: nop G_M5191_IG17: ; offs=00032AH, funclet=01 Added IP mapping: EPILOG STACK_EMPTY (G_M5191_IG18,ins#0,ofs#256) label *************** After placeholder IG creation G_M5191_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M5191_IG02: ; offs=000000H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref G_M5191_IG03: ; offs=000031H, size=0027H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref G_M5191_IG04: ; offs=000058H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG05: ; offs=000063H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG06: ; offs=00007AH, size=002EH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG07: ; offs=0000A8H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG08: ; offs=0000ADH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG09: ; offs=0000B2H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG10: ; offs=0000B7H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG11: ; offs=0000C1H, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG12: ; offs=0000F8H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG13: ; offs=0000FFH, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG14: ; epilog placeholder, next placeholder=IG15 , BB14 [0046], epilog, emitadd <-- First placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000002 {rcx}, InitByrefRegs=00000000 {} G_M5191_IG15: ; func=01, funclet prolog placeholder, next placeholder=IG18 , BB15 [0004], funclet prolog ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M5191_IG16: ; offs=00030FH, size=001BH, gcVars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M5191_IG17: ; offs=00032AH, size=000FH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG18: ; funclet epilog placeholder, next placeholder=, BB16 [0041], funclet epilog, emitadd <-- Last placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000002 {rcx}, InitByrefRegs=00000000 {} Liveness not changing: 0000000000000000 {} # compCycleEstimate = 416, compSizeEstimate = 319 Stream:Read(struct):int:this ; Final local variable assignments ; ; V00 this [V00,T05] ( 4, 4 ) ref -> rsi this class-hnd ; V01 arg1 [V01,T00] ( 8, 8 ) byref -> rdx ld-addr-op ; V02 loc0 [V02,T01] ( 9, 7 ) ref -> [rbp-0x48] do-not-enreg[H] class-hnd ; V03 loc1 [V03,T03] ( 6, 5 ) int -> rsi ; V04 loc2 [V04 ] ( 3, 3 ) struct (16) [rbp-0x30] do-not-enreg[XS] must-init addr-exposed ld-addr-op ; V05 loc3 [V05,T17] ( 2, 2 ) int -> rsi ;* V06 tmp0 [V06 ] ( 0, 0 ) ref -> zero-ref class-hnd ;* V07 tmp1 [V07 ] ( 0, 0 ) struct (16) zero-ref ; V08 tmp2 [V08,T20] ( 3, 0 ) ref -> r14 class-hnd exact ; V09 tmp3 [V09,T08] ( 4, 4 ) ref -> rcx class-hnd ;* V10 tmp4 [V10 ] ( 0, 0 ) ubyte -> zero-ref ld-addr-op ;* V11 tmp5 [V11 ] ( 0, 0 ) ref -> zero-ref class-hnd exact ;* V12 tmp6 [V12 ] ( 0, 0 ) struct ( 8) zero-ref ; V13 tmp7 [V13,T06] ( 3, 6 ) byref -> rcx ;* V14 tmp8 [V14 ] ( 0, 0 ) struct (16) zero-ref ; V15 tmp9 [V15,T10] ( 6, 3 ) ref -> rcx class-hnd ; V16 tmp10 [V16,T12] ( 2, 3 ) byref -> rdi V25._pointer(offs=0x00) P-INDEP ; V17 tmp11 [V17,T04] ( 5, 6 ) int -> rbx V25._length(offs=0x08) P-INDEP ; V18 tmp12 [V18 ] ( 2, 2 ) byref -> [rbp-0x30] do-not-enreg[X] addr-exposed V04._pointer(offs=0x00) P-DEP ; V19 tmp13 [V19 ] ( 2, 2 ) int -> [rbp-0x28] do-not-enreg[X] addr-exposed V04._length(offs=0x08) P-DEP ; V20 tmp14 [V20,T13] ( 2, 2 ) byref -> rcx V07._pointer(offs=0x00) P-INDEP ;* V21 tmp15 [V21,T19] ( 0, 0 ) int -> zero-ref V07._length(offs=0x08) P-INDEP ; V22 tmp16 [V22,T14] ( 2, 2 ) byref -> rcx V12._value(offs=0x00) P-INDEP ; V23 tmp17 [V23,T15] ( 2, 2 ) byref -> rdi V14._pointer(offs=0x00) P-INDEP ; V24 tmp18 [V24,T18] ( 2, 2 ) int -> rbx V14._length(offs=0x08) P-INDEP ;* V25 tmp19 [V25 ] ( 0, 0 ) struct (16) zero-ref ; V26 tmp20 [V26,T21] ( 2, 0 ) ref -> rcx ; V27 tmp21 [V27,T22] ( 2, 0 ) ref -> rdx ; V28 tmp22 [V28 ] ( 3, 6 ) struct (16) [rbp-0x40] do-not-enreg[XSB] must-init addr-exposed ; V29 tmp23 [V29,T07] ( 3, 6 ) byref -> rdx stack-byref ; V30 tmp24 [V30,T09] ( 2, 4 ) byref -> rcx ; V31 OutArgs [V31 ] ( 1, 1 ) lclBlk (32) [rsp+0x00] ; V32 PSPSym [V32 ] ( 1, 1 ) long -> [rbp-0x50] do-not-enreg[X] addr-exposed ; V33 tmp27 [V33,T16] ( 2, 2 ) ref -> rax ; V34 cse0 [V34,T02] ( 10, 6 ) byref -> r14 ; V35 cse1 [V35,T11] ( 6, 3 ) int -> rcx ; ; Lcl frame size = 80 *************** Before prolog / epilog generation G_M5191_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M5191_IG02: ; offs=000000H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref G_M5191_IG03: ; offs=000031H, size=0027H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref G_M5191_IG04: ; offs=000058H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG05: ; offs=000063H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG06: ; offs=00007AH, size=002EH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG07: ; offs=0000A8H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG08: ; offs=0000ADH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG09: ; offs=0000B2H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG10: ; offs=0000B7H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG11: ; offs=0000C1H, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG12: ; offs=0000F8H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG13: ; offs=0000FFH, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG14: ; epilog placeholder, next placeholder=IG15 , BB14 [0046], epilog, emitadd <-- First placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000002 {rcx}, InitByrefRegs=00000000 {} G_M5191_IG15: ; func=01, funclet prolog placeholder, next placeholder=IG18 , BB15 [0004], funclet prolog ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00004000 {r14} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M5191_IG16: ; offs=00030FH, size=001BH, gcVars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M5191_IG17: ; offs=00032AH, size=000FH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG18: ; funclet epilog placeholder, next placeholder=, BB16 [0041], funclet epilog, emitadd <-- Last placeholder ; PrevGCVars=0000000000000002 {V02}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000002 {V02}, InitGCrefRegs=00000002 {rcx}, InitByrefRegs=00000000 {} Recording Var Locations at start of BB01 V01(rdx) V00(rsi) *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M5191_IG01,ins#0,ofs#0) label __prolog: Found 8 lvMustInit stk vars, frame offsets 64 through 32 IN0050: push rbp IN0051: push r14 IN0052: push rdi IN0053: push rsi IN0054: push rbx IN0055: sub rsp, 80 IN0056: lea rbp, [rsp+70H] IN0057: mov rsi, rcx IN0058: lea rdi, [rbp-40H] IN0059: mov ecx, 8 IN005a: xor rax, rax IN005b: rep stosd IN005c: mov rcx, rsi IN005d: mov qword ptr [V32 rbp-50H], rsp *************** In genFnPrologCalleeRegArgs() for int regs IN005e: mov rsi, rcx *************** In genEnregisterIncomingStackArgs() 1 tracked GC refs are at stack offsets -0048 ... FFFFFFC0 G_M5191_IG01: ; offs=000000H, funclet=00 Funclet prolog / epilog info Function InitialSP-to-FP delta: 112 SP delta: 48 PSP slot Initial SP offset: 32 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000002 {V02}, gcRegGCrefSetCur=00000002 {rcx}, gcRegByrefSetCur=00000000 {} IN005f: lea rsp, [rbp-20H] IN0060: pop rbx IN0061: pop rsi IN0062: pop rdi IN0063: pop r14 IN0064: pop rbp IN0065: ret G_M5191_IG14: ; offs=00010FH, funclet=00 *************** In genFuncletProlog() IN0066: push rbp IN0067: push r14 IN0068: push rdi IN0069: push rsi IN006a: push rbx IN006b: sub rsp, 48 IN006c: mov rbp, qword ptr [rcx+32] Marking regs modified: [rbp] ([rax rcx rdx rbx rsi rdi r8-r11 r14] => [rax rcx rdx rbx rbp rsi rdi r8-r11 r14]) IN006d: mov qword ptr [rsp+20H], rbp IN006e: lea rbp, [rbp+70H] Removing modified regs: [rbp] ([rax rcx rdx rbx rbp rsi rdi r8-r11 r14] => [rax rcx rdx rbx rsi rdi r8-r11 r14]) G_M5191_IG15: ; offs=00020FH, funclet=01 *************** In genFuncletEpilog() IN006f: add rsp, 48 IN0070: pop rbx IN0071: pop rsi IN0072: pop rdi IN0073: pop r14 IN0074: pop rbp IN0075: ret G_M5191_IG18: ; offs=000339H, funclet=01 0 prologs, 1 epilogs, 1 funclet prologs, 1 funclet epilogs *************** After prolog / epilog generation G_M5191_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M5191_IG02: ; offs=000029H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref G_M5191_IG03: ; offs=00005AH, size=0027H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref G_M5191_IG04: ; offs=000081H, size=000BH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG05: ; offs=00008CH, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG06: ; offs=0000A3H, size=002EH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref G_M5191_IG07: ; offs=0000D1H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG08: ; offs=0000D6H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG09: ; offs=0000DBH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG10: ; offs=0000E0H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG11: ; offs=0000EAH, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M5191_IG12: ; offs=000121H, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref G_M5191_IG13: ; offs=000128H, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG14: ; offs=000138H, size=000BH, epilog, nogc, emitadd G_M5191_IG15: ; func=01, offs=000143H, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, funclet prolog, nogc G_M5191_IG16: ; offs=00015AH, size=001BH, gcVars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M5191_IG17: ; offs=000175H, size=000FH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref G_M5191_IG18: ; offs=000184H, size=000BH, funclet epilog, nogc, emitadd *************** In emitJumpDistBind() Binding: IN0018: 000000 jg L_M5191_BB12 Binding L_M5191_BB12 to G_M5191_IG11 Estimate of fwd jump [D51757DC/024]: 007B -> 00EA = 006D Shrinking jump [D51757DC/024] Binding: IN001a: 000000 je L_M5191_BB11 Binding L_M5191_BB11 to G_M5191_IG10 Estimate of fwd jump [D5175964/026]: 0082 -> 00DC = 0058 Shrinking jump [D5175964/026] Binding: IN001e: 000000 jb L_M5191_BB10 Binding L_M5191_BB10 to G_M5191_IG09 Estimate of fwd jump [D5175BAC/030]: 008D -> 00D3 = 0044 Shrinking jump [D5175BAC/030] Binding: IN0020: 000000 jb L_M5191_BB10 Binding L_M5191_BB10 to G_M5191_IG09 Estimate of fwd jump [D5175BF4/032]: 0091 -> 00CF = 003C Shrinking jump [D5175BF4/032] Binding: IN002c: 000000 je L_M5191_BB09 Binding L_M5191_BB09 to G_M5191_IG08 Estimate of fwd jump [D5176084/044]: 00BB -> 00C6 = 0009 Shrinking jump [D5176084/044] Binding: IN002d: 000000 jmp L_M5191_BB13 Binding L_M5191_BB13 to G_M5191_IG12 Estimate of fwd jump [D517619C/045]: 00BD -> 010D = 004E Shrinking jump [D517619C/045] Total shrinkage = 23, min extra jump size = 4294967295 Hot code size = 0x178 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x10) reserveUnwindInfo(isFunclet=TRUE, isColdCode=FALSE, unwindSize=0x10) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M5191_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0050: 000000 55 push rbp IN0051: 000001 4156 push r14 IN0052: 000003 57 push rdi IN0053: 000004 56 push rsi IN0054: 000005 53 push rbx IN0055: 000006 4883EC50 sub rsp, 80 IN0056: 00000A 488D6C2470 lea rbp, [rsp+70H] IN0057: 00000F 488BF1 mov rsi, rcx IN0058: 000012 488D7DC0 lea rdi, [rbp-40H] IN0059: 000016 B908000000 mov ecx, 8 IN005a: 00001B 33C0 xor rax, rax IN005b: 00001D F3AB rep stosd IN005c: 00001F 488BCE mov rcx, rsi IN005d: 000022 488965B0 mov qword ptr [rbp-50H], rsp gcrReg +[rsi] IN005e: 000026 488BF1 mov rsi, rcx G_M5191_IG02: ; func=00, offs=000029H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref New byrReg live regs=00000004 {rdx} byrReg +[rdx] byrReg +[rdi] IN0001: 000029 488B3A mov rdi, bword ptr [rdx] IN0002: 00002C 8B5A08 mov ebx, dword ptr [rdx+8] IN0003: 00002F 488B0D00000000 mov rcx, qword ptr [(reloc 0x17dd3b1e7b0)] byrReg -[rdx] IN0004: 000036 BA47010000 mov edx, 327 New byrReg live regs=00000081 {rax rdi} byrReg +[rax] [D51783C0] ptr arg pop 0 IN0005: 00003B E800000000 call CORINFO_HELP_GETSHARED_GCSTATIC_BASE byrReg +[r14] IN0006: 000040 4C8BF0 mov r14, rax gcrReg +[rcx] IN0007: 000043 498B8E78030000 mov rcx, gword ptr [r14+888] IN0008: 00004A 8BD3 mov edx, ebx byrReg -[rax] IN0009: 00004C 488B01 mov rax, qword ptr [rcx] IN000a: 00004F 488B4040 mov rax, qword ptr [rax+64] New gcrReg live regs=00000041 {rax rsi} gcrReg +[rax] gcrReg -[rcx] [D5178480] ptr arg pop 0 IN000b: 000053 FF5020 call gword ptr [rax+32]ArrayPool`1:Rent(int):ref:this [D51784C0] gcr var born at [rbp-48H] IN000c: 000056 488945B8 mov gword ptr [rbp-48H], rax G_M5191_IG03: ; func=00, offs=00005AH, size=0023H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref, isz New GC ref live vars=0000000000000002 {V02} New gcrReg live regs=00000040 {rsi} gcrReg -[rax] gcrReg +[rcx] IN000d: 00005A 488BCE mov rcx, rsi gcrReg +[rdx] IN000e: 00005D 488B55B8 mov rdx, gword ptr [rbp-48H] IN000f: 000061 448BCB mov r9d, ebx IN0010: 000064 4533C0 xor r8d, r8d IN0011: 000067 488B06 mov rax, qword ptr [rsi] IN0012: 00006A 488B4060 mov rax, qword ptr [rax+96] New gcrReg live regs=00000000 {} gcrReg -[rcx] gcrReg -[rdx] gcrReg -[rsi] [D51785C8] ptr arg pop 0 IN0013: 00006E FF5010 call qword ptr [rax+16]Stream:Read(ref,int,int):int:this IN0014: 000071 8BF0 mov esi, eax IN0015: 000073 8BCE mov ecx, esi IN0016: 000075 4863D3 movsxd rdx, ebx IN0017: 000078 483BCA cmp rcx, rdx IN0018: 00007B 7F56 jg SHORT G_M5191_IG11 G_M5191_IG04: ; func=00, offs=00007DH, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref, isz IN0019: 00007D 48837DB800 cmp gword ptr [rbp-48H], 0 IN001a: 000082 7445 je SHORT G_M5191_IG10 G_M5191_IG05: ; func=00, offs=000084H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref, isz gcrReg +[rcx] IN001b: 000084 488B4DB8 mov rcx, gword ptr [rbp-48H] gcrReg -[rcx] IN001c: 000088 8B4908 mov ecx, dword ptr [rcx+8] IN001d: 00008B 85C9 test ecx, ecx IN001e: 00008D 7235 jb SHORT G_M5191_IG09 IN001f: 00008F 3BCE cmp ecx, esi IN0020: 000091 7231 jb SHORT G_M5191_IG09 G_M5191_IG06: ; func=00, offs=000093H, size=002AH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref, isz gcrReg +[rcx] IN0021: 000093 488B4DB8 mov rcx, gword ptr [rbp-48H] gcrReg -[rcx] byrReg +[rcx] IN0022: 000097 4883C110 add rcx, 16 IN0023: 00009B 48894DD0 mov bword ptr [rbp-30H], rcx IN0024: 00009F 8975D8 mov dword ptr [rbp-28H], esi IN0025: 0000A2 488D4DD0 lea rcx, bword ptr [rbp-30H] byrReg +[rdx] IN0026: 0000A6 488D55C0 lea rdx, bword ptr [rbp-40H] IN0027: 0000AA 48893A mov bword ptr [rdx], rdi IN0028: 0000AD 895A08 mov dword ptr [rdx+8], ebx IN0029: 0000B0 488D55C0 lea rdx, bword ptr [rbp-40H] New byrReg live regs=00004000 {r14} byrReg -[rcx] byrReg -[rdx] byrReg -[rdi] [D5178730] ptr arg pop 0 IN002a: 0000B4 E800000000 call Span`1:TryCopyTo(struct):bool:this IN002b: 0000B9 85C0 test eax, eax IN002c: 0000BB 7402 je SHORT G_M5191_IG08 G_M5191_IG07: ; func=00, offs=0000BDH, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref, isz IN002d: 0000BD EB4B jmp SHORT G_M5191_IG12 G_M5191_IG08: ; func=00, offs=0000BFH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref New byrReg live regs=00000000 {} byrReg -[r14] [D5178798] ptr arg pop 0 IN002e: 0000BF E800000000 call ThrowHelper:ThrowArgumentException_DestinationTooShort() G_M5191_IG09: ; func=00, offs=0000C4H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref [D51787F8] ptr arg pop 0 IN002f: 0000C4 E800000000 call ThrowHelper:ThrowArgumentOutOfRangeException() G_M5191_IG10: ; func=00, offs=0000C9H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0030: 0000C9 B902000000 mov ecx, 2 [D5178848] ptr arg pop 0 IN0031: 0000CE E800000000 call ThrowHelper:ThrowArgumentNullException(int) G_M5191_IG11: ; func=00, offs=0000D3H, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0032: 0000D3 488D0D00000000 lea rcx, [(reloc 0x17dd3b22ac8)] New gcrReg live regs=00000001 {rax} gcrReg +[rax] [D51788B8] ptr arg pop 0 IN0033: 0000DA E800000000 call CORINFO_HELP_NEWSFAST gcrReg +[r14] IN0034: 0000DF 4C8BF0 mov r14, rax IN0035: 0000E2 B904E90000 mov ecx, 0xE904 [D51788F8] ptr arg pop 0 IN0036: 0000E7 E800000000 call CORINFO_HELP_STRCNS_CURRENT_MODULE gcrReg +[rcx] IN0037: 0000EC 488BC8 mov rcx, rax gcrReg +[rdx] IN0038: 0000EF 33D2 xor rdx, rdx New gcrReg live regs=00004001 {rax r14} gcrReg -[rcx] gcrReg -[rdx] [D5178998] ptr arg pop 0 IN0039: 0000F1 E800000000 call SR:GetResourceString(ref,ref):ref gcrReg +[rdx] IN003a: 0000F6 488BD0 mov rdx, rax gcrReg +[rcx] IN003b: 0000F9 498BCE mov rcx, r14 New gcrReg live regs=00004000 {r14} gcrReg -[rax] gcrReg -[rcx] gcrReg -[rdx] [D5178A80] ptr arg pop 0 IN003c: 0000FC E800000000 call IOException:.ctor(ref):this gcrReg +[rcx] IN003d: 000101 498BCE mov rcx, r14 New gcrReg live regs=00000000 {} gcrReg -[rcx] gcrReg -[r14] [D5178B88] ptr arg pop 0 IN003e: 000104 E800000000 call CORINFO_HELP_THROW IN003f: 000109 CC int3 G_M5191_IG12: ; func=00, offs=00010AH, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref New byrReg live regs=00004000 {r14} byrReg +[r14] gcrReg +[rcx] IN0040: 00010A 498B8E78030000 mov rcx, gword ptr [r14+888] G_M5191_IG13: ; func=00, offs=000111H, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref New byrReg live regs=00000000 {} byrReg -[r14] gcrReg +[rdx] IN0041: 000111 488B55B8 mov rdx, gword ptr [rbp-48H] IN0042: 000115 4533C0 xor r8d, r8d IN0043: 000118 3909 cmp dword ptr [rcx], ecx New GC ref live vars=0000000000000000 {} [D51784C0] gcr var died at [rbp-48H] New gcrReg live regs=00000000 {} gcrReg -[rcx] gcrReg -[rdx] [D5178C80] ptr arg pop 0 IN0044: 00011A E800000000 call TlsOverPerCoreLockedStacksArrayPool`1:Return(ref,bool):this IN0045: 00011F 8BC6 mov eax, esi G_M5191_IG14: ; func=00, offs=000121H, size=000BH, epilog, nogc, emitadd IN005f: 000121 488D65E0 lea rsp, [rbp-20H] IN0060: 000125 5B pop rbx IN0061: 000126 5E pop rsi IN0062: 000127 5F pop rdi IN0063: 000128 415E pop r14 IN0064: 00012A 5D pop rbp IN0065: 00012B C3 ret G_M5191_IG15: ; func=01, offs=00012CH, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, funclet prolog, nogc IN0066: 00012C 55 push rbp IN0067: 00012D 4156 push r14 IN0068: 00012F 57 push rdi IN0069: 000130 56 push rsi IN006a: 000131 53 push rbx IN006b: 000132 4883EC30 sub rsp, 48 IN006c: 000136 488B6920 mov rbp, qword ptr [rcx+32] IN006d: 00013A 48896C2420 mov qword ptr [rsp+20H], rbp IN006e: 00013F 488D6D70 lea rbp, [rbp+70H] G_M5191_IG16: ; func=01, offs=000143H, size=001BH, gcVars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref New GC ref live vars=0000000000000002 {V02} [D5178D10] gcr var born at [rbp-48H] IN0046: 000143 488B0D00000000 mov rcx, qword ptr [(reloc 0x17dd3b1e7b0)] IN0047: 00014A BA47010000 mov edx, 327 New byrReg live regs=00000001 {rax} byrReg +[rax] [D5178D48] ptr arg pop 0 IN0048: 00014F E800000000 call CORINFO_HELP_GETSHARED_GCSTATIC_BASE byrReg +[r14] IN0049: 000154 4C8BF0 mov r14, rax gcrReg +[rcx] IN004a: 000157 498B8E78030000 mov rcx, gword ptr [r14+888] G_M5191_IG17: ; func=01, offs=00015EH, size=000FH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref New byrReg live regs=00000000 {} byrReg -[rax] byrReg -[r14] gcrReg +[rdx] IN004b: 00015E 488B55B8 mov rdx, gword ptr [rbp-48H] IN004c: 000162 4533C0 xor r8d, r8d IN004d: 000165 3909 cmp dword ptr [rcx], ecx New GC ref live vars=0000000000000000 {} [D5178D10] gcr var died at [rbp-48H] New gcrReg live regs=00000000 {} gcrReg -[rcx] gcrReg -[rdx] [D5178E60] ptr arg pop 0 IN004e: 000167 E800000000 call TlsOverPerCoreLockedStacksArrayPool`1:Return(ref,bool):this IN004f: 00016C 90 nop G_M5191_IG18: ; func=01, offs=00016DH, size=000BH, funclet epilog, nogc, emitadd IN006f: 00016D 4883C430 add rsp, 48 IN0070: 000171 5B pop rbx IN0071: 000172 5E pop rsi IN0072: 000173 5F pop rdi IN0073: 000174 415E pop r14 IN0074: 000176 5D pop rbp IN0075: 000177 C3 ret Allocated method code size = 376 , actual size = 376 *************** After end code gen, before unwindEmit() G_M5191_IG01: ; func=00, offs=000000H, size=0029H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0050: 000000 push rbp IN0051: 000001 push r14 IN0052: 000003 push rdi IN0053: 000004 push rsi IN0054: 000005 push rbx IN0055: 000006 sub rsp, 80 IN0056: 00000A lea rbp, [rsp+70H] IN0057: 00000F mov rsi, rcx IN0058: 000012 lea rdi, [rbp-40H] IN0059: 000016 mov ecx, 8 IN005a: 00001B xor rax, rax IN005b: 00001D rep stosd IN005c: 00001F mov rcx, rsi IN005d: 000022 mov qword ptr [V32 rbp-50H], rsp IN005e: 000026 mov rsi, rcx G_M5191_IG02: ; offs=000029H, size=0031H, gcrefRegs=00000040 {rsi}, byrefRegs=00000004 {rdx}, byref IN0001: 000029 mov rdi, bword ptr [rdx] IN0002: 00002C mov ebx, dword ptr [rdx+8] IN0003: 00002F mov rcx, qword ptr [(reloc 0x17dd3b1e7b0)] IN0004: 000036 mov edx, 327 IN0005: 00003B call CORINFO_HELP_GETSHARED_GCSTATIC_BASE IN0006: 000040 mov r14, rax IN0007: 000043 mov rcx, gword ptr [r14+888] IN0008: 00004A mov edx, ebx IN0009: 00004C mov rax, qword ptr [rcx] IN000a: 00004F mov rax, qword ptr [rax+64] IN000b: 000053 call gword ptr [rax+32]ArrayPool`1:Rent(int):ref:this IN000c: 000056 mov gword ptr [V02 rbp-48H], rax G_M5191_IG03: ; offs=00005AH, size=0023H, gcVars=0000000000000002 {V02}, gcrefRegs=00000040 {rsi}, byrefRegs=00004080 {rdi r14}, gcvars, byref, isz IN000d: 00005A mov rcx, rsi IN000e: 00005D mov rdx, gword ptr [V02 rbp-48H] IN000f: 000061 mov r9d, ebx IN0010: 000064 xor r8d, r8d IN0011: 000067 mov rax, qword ptr [rsi] IN0012: 00006A mov rax, qword ptr [rax+96] IN0013: 00006E call qword ptr [rax+16]Stream:Read(ref,int,int):int:this IN0014: 000071 mov esi, eax IN0015: 000073 mov ecx, esi IN0016: 000075 movsxd rdx, ebx IN0017: 000078 cmp rcx, rdx IN0018: 00007B jg SHORT G_M5191_IG11 G_M5191_IG04: ; offs=00007DH, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref, isz IN0019: 00007D cmp gword ptr [V02 rbp-48H], 0 IN001a: 000082 je SHORT G_M5191_IG10 G_M5191_IG05: ; offs=000084H, size=000FH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref, isz IN001b: 000084 mov rcx, gword ptr [V02 rbp-48H] IN001c: 000088 mov ecx, dword ptr [rcx+8] IN001d: 00008B test ecx, ecx IN001e: 00008D jb SHORT G_M5191_IG09 IN001f: 00008F cmp ecx, esi IN0020: 000091 jb SHORT G_M5191_IG09 G_M5191_IG06: ; offs=000093H, size=002AH, gcrefRegs=00000000 {}, byrefRegs=00004080 {rdi r14}, byref, isz IN0021: 000093 mov rcx, gword ptr [V02 rbp-48H] IN0022: 000097 add rcx, 16 IN0023: 00009B mov bword ptr [V18 rbp-30H], rcx IN0024: 00009F mov dword ptr [V19 rbp-28H], esi IN0025: 0000A2 lea rcx, bword ptr [V04 rbp-30H] IN0026: 0000A6 lea rdx, bword ptr [V28 rbp-40H] IN0027: 0000AA mov bword ptr [rdx], rdi IN0028: 0000AD mov dword ptr [rdx+8], ebx IN0029: 0000B0 lea rdx, bword ptr [V28 rbp-40H] IN002a: 0000B4 call Span`1:TryCopyTo(struct):bool:this IN002b: 0000B9 test eax, eax IN002c: 0000BB je SHORT G_M5191_IG08 G_M5191_IG07: ; offs=0000BDH, size=0002H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref, isz IN002d: 0000BD jmp SHORT G_M5191_IG12 G_M5191_IG08: ; offs=0000BFH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN002e: 0000BF call ThrowHelper:ThrowArgumentException_DestinationTooShort() G_M5191_IG09: ; offs=0000C4H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN002f: 0000C4 call ThrowHelper:ThrowArgumentOutOfRangeException() G_M5191_IG10: ; offs=0000C9H, size=000AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0030: 0000C9 mov ecx, 2 IN0031: 0000CE call ThrowHelper:ThrowArgumentNullException(int) G_M5191_IG11: ; offs=0000D3H, size=0037H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0032: 0000D3 lea rcx, [(reloc 0x17dd3b22ac8)] IN0033: 0000DA call CORINFO_HELP_NEWSFAST IN0034: 0000DF mov r14, rax IN0035: 0000E2 mov ecx, 0xE904 IN0036: 0000E7 call CORINFO_HELP_STRCNS_CURRENT_MODULE IN0037: 0000EC mov rcx, rax IN0038: 0000EF xor rdx, rdx IN0039: 0000F1 call SR:GetResourceString(ref,ref):ref IN003a: 0000F6 mov rdx, rax IN003b: 0000F9 mov rcx, r14 IN003c: 0000FC call IOException:.ctor(ref):this IN003d: 000101 mov rcx, r14 IN003e: 000104 call CORINFO_HELP_THROW IN003f: 000109 int3 G_M5191_IG12: ; offs=00010AH, size=0007H, gcrefRegs=00000000 {}, byrefRegs=00004000 {r14}, byref IN0040: 00010A mov rcx, gword ptr [r14+888] G_M5191_IG13: ; offs=000111H, size=0010H, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref IN0041: 000111 mov rdx, gword ptr [V02 rbp-48H] IN0042: 000115 xor r8d, r8d IN0043: 000118 cmp dword ptr [rcx], ecx IN0044: 00011A call TlsOverPerCoreLockedStacksArrayPool`1:Return(ref,bool):this IN0045: 00011F mov eax, esi G_M5191_IG14: ; offs=000121H, size=000BH, epilog, nogc, emitadd IN005f: 000121 lea rsp, [rbp-20H] IN0060: 000125 pop rbx IN0061: 000126 pop rsi IN0062: 000127 pop rdi IN0063: 000128 pop r14 IN0064: 00012A pop rbp IN0065: 00012B ret G_M5191_IG15: ; func=01, offs=00012CH, size=0017H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, funclet prolog, nogc IN0066: 00012C push rbp IN0067: 00012D push r14 IN0068: 00012F push rdi IN0069: 000130 push rsi IN006a: 000131 push rbx IN006b: 000132 sub rsp, 48 IN006c: 000136 mov rbp, qword ptr [rcx+32] IN006d: 00013A mov qword ptr [rsp+20H], rbp IN006e: 00013F lea rbp, [rbp+70H] G_M5191_IG16: ; offs=000143H, size=001BH, gcVars=0000000000000002 {V02}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref IN0046: 000143 mov rcx, qword ptr [(reloc 0x17dd3b1e7b0)] IN0047: 00014A mov edx, 327 IN0048: 00014F call CORINFO_HELP_GETSHARED_GCSTATIC_BASE IN0049: 000154 mov r14, rax IN004a: 000157 mov rcx, gword ptr [r14+888] G_M5191_IG17: ; offs=00015EH, size=000FH, gcrefRegs=00000002 {rcx}, byrefRegs=00000000 {}, byref IN004b: 00015E mov rdx, gword ptr [V02 rbp-48H] IN004c: 000162 xor r8d, r8d IN004d: 000165 cmp dword ptr [rcx], ecx IN004e: 000167 call TlsOverPerCoreLockedStacksArrayPool`1:Return(ref,bool):this IN004f: 00016C nop G_M5191_IG18: ; offs=00016DH, size=000BH, funclet epilog, nogc, emitadd IN006f: 00016D add rsp, 48 IN0070: 000171 pop rbx IN0071: 000172 pop rsi IN0072: 000173 pop rdi IN0073: 000174 pop r14 IN0074: 000176 pop rbp IN0075: 000177 ret Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x00012c (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x0A CountOfUnwindCodes: 6 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x0A UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 9 * 8 + 8 = 80 = 0x50 CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x05 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x0000017DD3EE5170, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x12c, unwindSize=0x10, pUnwindBlock=0x0000017DD4E752D0, funKind=0 (main function)) Unwind Info: >> Start offset : 0x00012c (not in unwind data) >> End offset : 0x000178 (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x0A CountOfUnwindCodes: 6 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x0A UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 5 * 8 + 8 = 48 = 0x30 CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x05 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x0000017DD3EE5170, pColdCode=0x0000000000000000, startOffset=0x12c, endOffset=0x178, unwindSize=0x10, pUnwindBlock=0x0000017DD4E75508, funKind=1 (handler)) *************** In genIPmappingGen() IP mapping count : 17 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x0000002F ( STACK_EMPTY ) IL offs 0x0039 : 0x0000007D ( STACK_EMPTY ) IL offs NO_MAP : 0x00000084 ( STACK_EMPTY ) IL offs 0x0041 : 0x0000009B IL offs 0x0042 : 0x000000A2 ( STACK_EMPTY ) IL offs 0x004A : 0x000000BD ( STACK_EMPTY ) IL offs 0x0042 : 0x000000BF ( STACK_EMPTY ) IL offs NO_MAP : 0x000000C4 ( STACK_EMPTY ) IL offs 0x0038 : 0x00000101 IL offs 0x005B : 0x0000011F ( STACK_EMPTY ) IL offs EPILOG : 0x00000121 ( STACK_EMPTY ) IL offs PROLOG : 0x0000012C ( STACK_EMPTY ) IL offs 0x004E : 0x00000143 ( STACK_EMPTY ) IL offs NO_MAP : 0x0000015E ( STACK_EMPTY ) IL offs 0x005A : 0x0000016C ( STACK_EMPTY ) IL offs EPILOG : 0x0000016D ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 6 *************** Variable debug info 6 vars 1( UNKNOWN) : From 00000000h to 00000029h, in rdx 0( UNKNOWN) : From 00000000h to 00000029h, in rcx 0( UNKNOWN) : From 0000002Fh to 00000067h, in rsi 3( UNKNOWN) : From 0000007Dh to 000000BDh, in rsi 2( UNKNOWN) : From 0000005Ah to 00000115h, in rbp[-72] (1 slot) 5( UNKNOWN) : From 0000010Ah to 0000011Fh, in rsi *************** EH table for Stream:Read(struct):int:this 1 EH table entries, 0 duplicate clauses, 0 cloned finallys, 1 total EH entries reported to VM setEHcount(cEH=1) EH#0: try [005A..010A) handled by [012C..0178) (fault) *************** In gcInfoBlockHdrSave() Set code length to 376. Set ReturnKind to Scalar. Set stack base register to rbp. Set PSPSym stack slot to 32. Set WantsReportOnlyLeaf. Set Outgoing stack arg area size to 32. Stack slot id for offset -48 (0xffffffd0) (frame) (byref, untracked) = 0. Stack slot id for offset -64 (0xffffffc0) (frame) (byref, untracked) = 1. Stack slot id for offset -72 (0xffffffb8) (frame) = 2. Register slot id for reg rsi = 3. Register slot id for reg rdx (byref) = 4. Register slot id for reg rdi (byref) = 5. Register slot id for reg rax (byref) = 6. Register slot id for reg r14 (byref) = 7. Register slot id for reg rcx = 8. Register slot id for reg rax = 9. Register slot id for reg rdx = 10. Register slot id for reg rcx (byref) = 11. Register slot id for reg r14 = 12. Set state of slot 2 at instr offset 0x5a to Live. Set state of slot 2 at instr offset 0x11a to Dead. Set state of slot 2 at instr offset 0x143 to Live. Set state of slot 2 at instr offset 0x167 to Dead. Set state of slot 3 at instr offset 0x29 to Live. Set state of slot 4 at instr offset 0x29 to Live. Set state of slot 5 at instr offset 0x2c to Live. Set state of slot 4 at instr offset 0x3b to Dead. Set state of slot 6 at instr offset 0x40 to Live. Set state of slot 7 at instr offset 0x43 to Live. Set state of slot 8 at instr offset 0x4a to Live. Set state of slot 6 at instr offset 0x4f to Dead. Set state of slot 9 at instr offset 0x56 to Live. Set state of slot 8 at instr offset 0x56 to Dead. Set state of slot 9 at instr offset 0x5a to Dead. Set state of slot 8 at instr offset 0x5d to Live. Set state of slot 10 at instr offset 0x61 to Live. Set state of slot 8 at instr offset 0x71 to Dead. Set state of slot 10 at instr offset 0x71 to Dead. Set state of slot 3 at instr offset 0x71 to Dead. Set state of slot 8 at instr offset 0x88 to Live. Set state of slot 8 at instr offset 0x8b to Dead. Set state of slot 8 at instr offset 0x97 to Live. Set state of slot 8 at instr offset 0x9b to Dead. Set state of slot 11 at instr offset 0x9b to Live. Set state of slot 4 at instr offset 0xaa to Live. Set state of slot 11 at instr offset 0xb9 to Dead. Set state of slot 4 at instr offset 0xb9 to Dead. Set state of slot 5 at instr offset 0xb9 to Dead. Set state of slot 7 at instr offset 0xbf to Dead. Set state of slot 9 at instr offset 0xdf to Live. Set state of slot 12 at instr offset 0xe2 to Live. Set state of slot 8 at instr offset 0xef to Live. Set state of slot 10 at instr offset 0xf1 to Live. Set state of slot 8 at instr offset 0xf6 to Dead. Set state of slot 10 at instr offset 0xf6 to Dead. Set state of slot 10 at instr offset 0xf9 to Live. Set state of slot 8 at instr offset 0xfc to Live. Set state of slot 9 at instr offset 0x101 to Dead. Set state of slot 8 at instr offset 0x101 to Dead. Set state of slot 10 at instr offset 0x101 to Dead. Set state of slot 8 at instr offset 0x104 to Live. Set state of slot 8 at instr offset 0x109 to Dead. Set state of slot 12 at instr offset 0x109 to Dead. Set state of slot 7 at instr offset 0x10a to Live. Set state of slot 8 at instr offset 0x111 to Live. Set state of slot 7 at instr offset 0x111 to Dead. Set state of slot 10 at instr offset 0x115 to Live. Set state of slot 8 at instr offset 0x11f to Dead. Set state of slot 10 at instr offset 0x11f to Dead. Set state of slot 6 at instr offset 0x154 to Live. Set state of slot 7 at instr offset 0x157 to Live. Set state of slot 8 at instr offset 0x15e to Live. Set state of slot 6 at instr offset 0x15e to Dead. Set state of slot 7 at instr offset 0x15e to Dead. Set state of slot 10 at instr offset 0x162 to Live. Set state of slot 8 at instr offset 0x16c to Dead. Set state of slot 10 at instr offset 0x16c to Dead. Defining interruptible range: [0x29, 0x121). Defining interruptible range: [0x143, 0x16d). Method code size: 376 Allocations for Stream:Read(struct):int:this (MethodHash=dbd77fdf) count: 4278, size: 282215, max = 5168 allocateMemory: 393216, nraUsed: 364304 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 2.29% ASTNode | 45480 | 16.12% InstDesc | 11396 | 4.04% ImpStack | 0 | 0.00% BasicBlock | 6184 | 2.19% fgArgInfo | 1568 | 0.56% fgArgInfoPtrArr | 224 | 0.08% FlowList | 1312 | 0.46% TreeStatementList | 256 | 0.09% SiScope | 400 | 0.14% FlatFPStateX87 | 0 | 0.00% DominatorMemory | 632 | 0.22% LSRA | 5412 | 1.92% LSRA_Interval | 7656 | 2.71% LSRA_RefPosition | 25536 | 9.05% Reachability | 16 | 0.01% SSA | 7816 | 2.77% ValueNumber | 23161 | 8.21% LvaTable | 11314 | 4.01% UnwindInfo | 32 | 0.01% hashBv | 1336 | 0.47% bitset | 784 | 0.28% FixedBitVect | 0 | 0.00% Generic | 6196 | 2.20% IndirAssignMap | 176 | 0.06% FieldSeqStore | 0 | 0.00% ZeroOffsetFieldMap | 56 | 0.02% ArrayInfoMap | 112 | 0.04% MemoryPhiArg | 224 | 0.08% CSE | 2032 | 0.72% GC | 5516 | 1.95% CorSig | 1144 | 0.41% Inlining | 9144 | 3.24% ArrayStack | 3392 | 1.20% DebugInfo | 968 | 0.34% DebugOnly | 88986 | 31.53% Codegen | 0 | 0.00% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 1342 | 0.48% RangeCheck | 0 | 0.00% CopyProp | 5952 | 2.11% ****** DONE compiling Stream:Read(struct):int:this Microsoft (R) CoreCLR Native Image Generator - Version 4.5.22220.0 Copyright (c) Microsoft Corporation. All rights reserved. Native image C:\GitHub\coreclr\bin\tests\Windows_NT.x64.Release\Tests\Core_Root-diff\System.Private.CoreLib.ni.dll generated successfully.